Lines Matching +full:num +full:- +full:irqs
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
243 #define PCI_QUIRK_DISABLE_FLR 8 /* Function-Level Reset (FLR) not working. */
256 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
257 * or the CMIC-SL (AKA ServerWorks GC_LE).
275 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
358 "firmware-assigned ranges fail to allocate during the initial device scan.");
371 "Transition from D3 -> D0 on resume.");
376 "Transition from D0 -> D3 on suspend.");
384 "Enable support for MSI-X interrupts");
389 "Rewrite entire MSI-X table when updating MSI-X entries");
393 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
408 "Ignore firmware-assigned resources for BARs.");
412 "Ignore firmware-assigned bus numbers.");
442 &pci_intx_reroute, 0, "Re-route INTx interrupts when scanning devices");
449 for (q = &pci_quirks[0]; q->devid; q++) { in pci_has_quirk()
450 if (q->devid == devid && q->type == quirk) in pci_has_quirk()
473 if ((dinfo->cfg.domain == domain) && in pci_find_dbsf()
474 (dinfo->cfg.bus == bus) && in pci_find_dbsf()
475 (dinfo->cfg.slot == slot) && in pci_find_dbsf()
476 (dinfo->cfg.func == func)) { in pci_find_dbsf()
481 return (dinfo != NULL ? dinfo->cfg.dev : NULL); in pci_find_dbsf()
492 if ((dinfo->cfg.vendor == vendor) && in pci_find_device()
493 (dinfo->cfg.device == device)) { in pci_find_device()
494 return (dinfo->cfg.dev); in pci_find_device()
507 if (dinfo->cfg.baseclass == class && in pci_find_class()
508 dinfo->cfg.subclass == subclass) { in pci_find_class()
509 return (dinfo->cfg.dev); in pci_find_class()
524 if (from != dinfo->cfg.dev) in pci_find_class_from()
529 if (dinfo->cfg.baseclass == class && in pci_find_class_from()
530 dinfo->cfg.subclass == subclass) { in pci_find_class_from()
531 return (dinfo->cfg.dev); in pci_find_class_from()
546 if (from != dinfo->cfg.dev) in pci_find_base_class_from()
551 if (dinfo->cfg.baseclass == class) { in pci_find_base_class_from()
552 return (dinfo->cfg.dev); in pci_find_base_class_from()
565 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, in pci_printf()
566 cfg->func); in pci_printf()
674 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) in pci_fixancient()
678 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) in pci_fixancient()
679 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; in pci_fixancient()
688 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_hdrtypedata()
690 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); in pci_hdrtypedata()
691 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); in pci_hdrtypedata()
692 cfg->mingnt = REG(PCIR_MINGNT, 1); in pci_hdrtypedata()
693 cfg->maxlat = REG(PCIR_MAXLAT, 1); in pci_hdrtypedata()
694 cfg->nummaps = PCI_MAXMAPS_0; in pci_hdrtypedata()
697 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); in pci_hdrtypedata()
698 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); in pci_hdrtypedata()
699 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); in pci_hdrtypedata()
700 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); in pci_hdrtypedata()
701 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); in pci_hdrtypedata()
702 cfg->nummaps = PCI_MAXMAPS_1; in pci_hdrtypedata()
705 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); in pci_hdrtypedata()
706 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); in pci_hdrtypedata()
707 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); in pci_hdrtypedata()
708 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); in pci_hdrtypedata()
709 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); in pci_hdrtypedata()
710 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); in pci_hdrtypedata()
711 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); in pci_hdrtypedata()
712 cfg->nummaps = PCI_MAXMAPS_2; in pci_hdrtypedata()
751 cfg = &devlist_entry->cfg; in pci_fill_devinfo()
753 cfg->domain = d; in pci_fill_devinfo()
754 cfg->bus = b; in pci_fill_devinfo()
755 cfg->slot = s; in pci_fill_devinfo()
756 cfg->func = f; in pci_fill_devinfo()
757 cfg->vendor = vid; in pci_fill_devinfo()
758 cfg->device = did; in pci_fill_devinfo()
759 cfg->cmdreg = REG(PCIR_COMMAND, 2); in pci_fill_devinfo()
760 cfg->statreg = REG(PCIR_STATUS, 2); in pci_fill_devinfo()
761 cfg->baseclass = REG(PCIR_CLASS, 1); in pci_fill_devinfo()
762 cfg->subclass = REG(PCIR_SUBCLASS, 1); in pci_fill_devinfo()
763 cfg->progif = REG(PCIR_PROGIF, 1); in pci_fill_devinfo()
764 cfg->revid = REG(PCIR_REVID, 1); in pci_fill_devinfo()
765 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); in pci_fill_devinfo()
766 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); in pci_fill_devinfo()
767 cfg->lattimer = REG(PCIR_LATTIMER, 1); in pci_fill_devinfo()
768 cfg->intpin = REG(PCIR_INTPIN, 1); in pci_fill_devinfo()
769 cfg->intline = REG(PCIR_INTLINE, 1); in pci_fill_devinfo()
771 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; in pci_fill_devinfo()
772 cfg->hdrtype &= ~PCIM_MFDEV; in pci_fill_devinfo()
773 STAILQ_INIT(&cfg->maps); in pci_fill_devinfo()
775 cfg->iov = NULL; in pci_fill_devinfo()
785 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; in pci_fill_devinfo()
786 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; in pci_fill_devinfo()
787 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; in pci_fill_devinfo()
788 devlist_entry->conf.pc_sel.pc_func = cfg->func; in pci_fill_devinfo()
789 devlist_entry->conf.pc_hdr = cfg->hdrtype; in pci_fill_devinfo()
791 devlist_entry->conf.pc_subvendor = cfg->subvendor; in pci_fill_devinfo()
792 devlist_entry->conf.pc_subdevice = cfg->subdevice; in pci_fill_devinfo()
793 devlist_entry->conf.pc_vendor = cfg->vendor; in pci_fill_devinfo()
794 devlist_entry->conf.pc_device = cfg->device; in pci_fill_devinfo()
796 devlist_entry->conf.pc_class = cfg->baseclass; in pci_fill_devinfo()
797 devlist_entry->conf.pc_subclass = cfg->subclass; in pci_fill_devinfo()
798 devlist_entry->conf.pc_progif = cfg->progif; in pci_fill_devinfo()
799 devlist_entry->conf.pc_revid = cfg->revid; in pci_fill_devinfo()
811 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ in pci_ea_fill_info()
812 cfg->ea.ea_location + (n), w) in pci_ea_fill_info()
822 if (cfg->ea.ea_location == 0) in pci_ea_fill_info()
825 STAILQ_INIT(&cfg->ea.ea_entries); in pci_ea_fill_info()
835 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) in pci_ea_fill_info()
840 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; in pci_ea_fill_info()
852 eae->eae_flags = val; in pci_ea_fill_info()
853 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; in pci_ea_fill_info()
868 eae->eae_base = base; in pci_ea_fill_info()
869 eae->eae_max_offset = max_offset; in pci_ea_fill_info()
871 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); in pci_ea_fill_info()
875 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, in pci_ea_fill_info()
876 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); in pci_ea_fill_info()
885 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) in pci_read_cap()
886 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) in pci_read_cap()
893 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_read_cap()
923 cfg->pp.pp_location = ptr; in pci_read_cap()
924 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); in pci_read_cap()
927 /* Determine HT-specific capability type. */ in pci_read_cap()
931 cfg->ht.ht_slave = ptr; in pci_read_cap()
945 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", in pci_read_cap()
946 cfg->domain, cfg->bus, in pci_read_cap()
947 cfg->slot, cfg->func, in pci_read_cap()
952 cfg->ht.ht_msimap = ptr; in pci_read_cap()
953 cfg->ht.ht_msictrl = val; in pci_read_cap()
954 cfg->ht.ht_msiaddr = addr; in pci_read_cap()
960 cfg->msi.msi_location = ptr; in pci_read_cap()
961 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); in pci_read_cap()
963 case PCIY_MSIX: /* PCI MSI-X */ in pci_read_cap()
964 cfg->msix.msix_location = ptr; in pci_read_cap()
965 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); in pci_read_cap()
967 cfg->msix.msix_table_bar = PCIR_BAR(val & in pci_read_cap()
969 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; in pci_read_cap()
971 cfg->msix.msix_pba_bar = PCIR_BAR(val & in pci_read_cap()
973 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; in pci_read_cap()
976 cfg->vpd.vpd_reg = ptr; in pci_read_cap()
980 if ((cfg->hdrtype & PCIM_HDRTYPE) == in pci_read_cap()
983 cfg->subvendor = val & 0xffff; in pci_read_cap()
984 cfg->subdevice = val >> 16; in pci_read_cap()
987 case PCIY_PCIX: /* PCI-X */ in pci_read_cap()
989 * Assume we have a PCI-X chipset if we have in pci_read_cap()
990 * at least one PCI-PCI bridge with a PCI-X in pci_read_cap()
992 * PCI-express or HT chipsets might match on in pci_read_cap()
995 if ((cfg->hdrtype & PCIM_HDRTYPE) == in pci_read_cap()
998 cfg->pcix.pcix_location = ptr; in pci_read_cap()
1000 case PCIY_EXPRESS: /* PCI-express */ in pci_read_cap()
1002 * Assume we have a PCI-express chipset if we have in pci_read_cap()
1003 * at least one PCI-express device. in pci_read_cap()
1006 cfg->pcie.pcie_location = ptr; in pci_read_cap()
1008 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; in pci_read_cap()
1011 cfg->ea.ea_location = ptr; in pci_read_cap()
1022 * slaves. PCI-PCI bridges have their windows enabled via in pci_read_cap()
1025 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && in pci_read_cap()
1026 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { in pci_read_cap()
1029 cfg->domain, cfg->bus, cfg->slot, cfg->func); in pci_read_cap()
1030 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; in pci_read_cap()
1031 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, in pci_read_cap()
1051 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); in pci_read_vpd_reg()
1053 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { in pci_read_vpd_reg()
1054 if (--count < 0) in pci_read_vpd_reg()
1058 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); in pci_read_vpd_reg()
1071 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
1072 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
1073 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
1074 if (--count < 0)
1094 /* return 0 and one byte in *data if no read error, -1 else */
1101 if (vrs->bytesinval == 0) { in vpd_nextbyte()
1102 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) in vpd_nextbyte()
1103 return (-1); in vpd_nextbyte()
1104 vrs->val = le32toh(reg); in vpd_nextbyte()
1105 vrs->off += 4; in vpd_nextbyte()
1106 byte = vrs->val & 0xff; in vpd_nextbyte()
1107 vrs->bytesinval = 3; in vpd_nextbyte()
1109 vrs->val = vrs->val >> 8; in vpd_nextbyte()
1110 byte = vrs->val & 0xff; in vpd_nextbyte()
1111 vrs->bytesinval--; in vpd_nextbyte()
1114 vrs->cksum += byte; in vpd_nextbyte()
1119 /* return 0 on match, -1 and "unget" byte on no match */
1126 return (-1); in vpd_expectbyte()
1131 vrs->cksum -= data; in vpd_expectbyte()
1132 vrs->val = (vrs->val << 8) + data; in vpd_expectbyte()
1133 vrs->bytesinval++; in vpd_expectbyte()
1134 return (-1); in vpd_expectbyte()
1137 /* return size if tag matches, -1 on no match, -2 on read error */
1144 return (-1); in vpd_read_tag_size()
1150 return (-2); in vpd_read_tag_size()
1152 return (-2); in vpd_read_tag_size()
1173 /* read VPD keyword and return element size, return -1 on read error */
1180 return (-1); in vpd_read_elem_head()
1182 return (-1); in vpd_read_elem_head()
1184 return (-1); in vpd_read_elem_head()
1218 return (-1); in vpd_read_elem_data()
1234 vrs->cksum -= fixup; in vpd_fixup_cksum()
1237 /* fetch one read-only element and return size of heading + data */
1246 cfg = vrs->cfg; in next_vpd_ro_elem()
1247 vpd = &cfg->vpd; in next_vpd_ro_elem()
1250 return (-1); in next_vpd_ro_elem()
1251 vpd->vpd_ros = alloc_buffer(vpd->vpd_ros, sizeof(*vpd->vpd_ros), vpd->vpd_rocnt); in next_vpd_ro_elem()
1252 vpd_ros = &vpd->vpd_ros[vpd->vpd_rocnt]; in next_vpd_ro_elem()
1253 maxsize -= 3; in next_vpd_ro_elem()
1254 len = vpd_read_elem_data(vrs, vpd_ros->keyword, &vpd_ros->value, maxsize); in next_vpd_ro_elem()
1255 if (vpd_ros->value == NULL) in next_vpd_ro_elem()
1256 return (-1); in next_vpd_ro_elem()
1257 vpd_ros->len = len; in next_vpd_ro_elem()
1258 if (vpd_ros->keyword[0] == 'R' && vpd_ros->keyword[1] == 'V') { in next_vpd_ro_elem()
1259 vpd_fixup_cksum(vrs, vpd_ros->value, len); in next_vpd_ro_elem()
1260 if (vrs->cksum != 0) { in next_vpd_ro_elem()
1262 "invalid VPD checksum %#hhx\n", vrs->cksum); in next_vpd_ro_elem()
1263 return (-1); in next_vpd_ro_elem()
1266 vpd->vpd_rocnt++; in next_vpd_ro_elem()
1280 cfg = vrs->cfg; in next_vpd_rw_elem()
1281 vpd = &cfg->vpd; in next_vpd_rw_elem()
1284 return (-1); in next_vpd_rw_elem()
1285 vpd->vpd_w = alloc_buffer(vpd->vpd_w, sizeof(*vpd->vpd_w), vpd->vpd_wcnt); in next_vpd_rw_elem()
1286 if (vpd->vpd_w == NULL) { in next_vpd_rw_elem()
1288 return (-1); in next_vpd_rw_elem()
1290 vpd_w = &vpd->vpd_w[vpd->vpd_wcnt]; in next_vpd_rw_elem()
1291 maxsize -= 3; in next_vpd_rw_elem()
1292 vpd_w->start = vrs->off + 3 - vrs->bytesinval; in next_vpd_rw_elem()
1293 len = vpd_read_elem_data(vrs, vpd_w->keyword, &vpd_w->value, maxsize); in next_vpd_rw_elem()
1294 if (vpd_w->value == NULL) in next_vpd_rw_elem()
1295 return (-1); in next_vpd_rw_elem()
1296 vpd_w->len = len; in next_vpd_rw_elem()
1297 vpd->vpd_wcnt++; in next_vpd_rw_elem()
1308 free(vpd->vpd_ident, M_DEVBUF); in vpd_free()
1309 for (i = 0; i < vpd->vpd_rocnt; i++) in vpd_free()
1310 free(vpd->vpd_ros[i].value, M_DEVBUF); in vpd_free()
1311 free(vpd->vpd_ros, M_DEVBUF); in vpd_free()
1312 vpd->vpd_rocnt = 0; in vpd_free()
1313 for (i = 0; i < vpd->vpd_wcnt; i++) in vpd_free()
1314 free(vpd->vpd_w[i].value, M_DEVBUF); in vpd_free()
1315 free(vpd->vpd_w, M_DEVBUF); in vpd_free()
1316 vpd->vpd_wcnt = 0; in vpd_free()
1338 /* read VPD ident element - mandatory */ in pci_parse_vpd()
1344 cfg->vpd.vpd_ident = vpd_read_value(&vrs, size); in pci_parse_vpd()
1345 if (cfg->vpd.vpd_ident == NULL) { in pci_parse_vpd()
1350 /* read VPD RO elements - mandatory */ in pci_parse_vpd()
1353 pci_printf(cfg, "no read-only VPD data found\n"); in pci_parse_vpd()
1359 pci_printf(cfg, "error accessing read-only VPD data\n"); in pci_parse_vpd()
1360 return (-1); in pci_parse_vpd()
1362 size -= elem_size; in pci_parse_vpd()
1366 return (-1); in pci_parse_vpd()
1368 /* read VPD RW elements - optional */ in pci_parse_vpd()
1370 if (size == -2) in pci_parse_vpd()
1371 return (-1); in pci_parse_vpd()
1376 return (-1); in pci_parse_vpd()
1378 size -= elem_size; in pci_parse_vpd()
1381 /* read empty END tag - mandatory */ in pci_parse_vpd()
1396 vpd_free(&cfg->vpd); in pci_read_vpd()
1397 cfg->vpd.vpd_cached = 1; in pci_read_vpd()
1406 pcicfgregs *cfg = &dinfo->cfg; in pci_get_vpd_ident_method()
1408 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_get_vpd_ident_method()
1411 *identptr = cfg->vpd.vpd_ident; in pci_get_vpd_ident_method()
1424 pcicfgregs *cfg = &dinfo->cfg; in pci_get_vpd_readonly_method()
1427 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_get_vpd_readonly_method()
1430 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) in pci_get_vpd_readonly_method()
1431 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, in pci_get_vpd_readonly_method()
1432 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { in pci_get_vpd_readonly_method()
1433 *vptr = cfg->vpd.vpd_ros[i].value; in pci_get_vpd_readonly_method()
1445 pcicfgregs *cfg = &dinfo->cfg; in pci_fetch_vpd_list()
1447 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_fetch_vpd_list()
1449 return (&cfg->vpd); in pci_fetch_vpd_list()
1543 pcicfgregs *cfg = &dinfo->cfg; in pci_find_cap_method()
1558 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_find_cap_method()
1577 for (cnt = 0; ptr != 0 && cnt < (PCIE_REGMAX - 0x40) / 2; cnt++) { in pci_find_cap_method()
1626 pcicfgregs *cfg = &dinfo->cfg; in pci_find_extcap_method()
1630 /* Only supported for PCI-express devices. */ in pci_find_extcap_method()
1631 if (cfg->pcie.pcie_location == 0) in pci_find_extcap_method()
1663 pcicfgregs *cfg = &dinfo->cfg; in pci_find_next_extcap_method()
1667 /* Only supported for PCI-express devices. */ in pci_find_next_extcap_method()
1668 if (cfg->pcie.pcie_location == 0) in pci_find_next_extcap_method()
1689 * Support for MSI-X message interrupts.
1695 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_write_msix_entry()
1698 KASSERT(msix->msix_table_len > index, ("bogus index")); in pci_write_msix_entry()
1699 offset = msix->msix_table_offset + index * 16; in pci_write_msix_entry()
1700 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); in pci_write_msix_entry()
1701 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); in pci_write_msix_entry()
1702 bus_write_4(msix->msix_table_res, offset + 8, data); in pci_write_msix_entry()
1712 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_enable_msix_method()
1723 msix->msix_location + PCIR_MSIX_CTRL, in pci_enable_msix_method()
1724 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); in pci_enable_msix_method()
1729 /* Enable MSI -> HT mapping. */ in pci_enable_msix_method()
1737 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_mask_msix()
1740 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); in pci_mask_msix()
1741 offset = msix->msix_table_offset + index * 16 + 12; in pci_mask_msix()
1742 val = bus_read_4(msix->msix_table_res, offset); in pci_mask_msix()
1749 bus_write_4(msix->msix_table_res, offset, val); in pci_mask_msix()
1756 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_unmask_msix()
1759 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); in pci_unmask_msix()
1760 offset = msix->msix_table_offset + index * 16 + 12; in pci_unmask_msix()
1761 val = bus_read_4(msix->msix_table_res, offset); in pci_unmask_msix()
1768 bus_write_4(msix->msix_table_res, offset, val); in pci_unmask_msix()
1775 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_pending_msix()
1778 KASSERT(msix->msix_table_len > index, ("bogus index")); in pci_pending_msix()
1779 offset = msix->msix_pba_offset + (index / 32) * 4; in pci_pending_msix()
1781 return (bus_read_4(msix->msix_pba_res, offset) & bit); in pci_pending_msix()
1785 * Restore MSI-X registers and table during resume. If MSI-X is
1786 * enabled then walk the virtual table to restore the actual MSI-X
1793 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_resume_msix()
1798 if (msix->msix_alloc > 0) { in pci_resume_msix()
1799 msgnum = PCI_MSIX_MSGNUM(msix->msix_ctrl); in pci_resume_msix()
1806 for (i = 0; i < msix->msix_table_len; i++) { in pci_resume_msix()
1807 mte = &msix->msix_table[i]; in pci_resume_msix()
1808 if (mte->mte_vector == 0 || mte->mte_handlers == 0) in pci_resume_msix()
1810 mv = &msix->msix_vectors[mte->mte_vector - 1]; in pci_resume_msix()
1811 pci_write_msix_entry(dev, i, mv->mv_address, in pci_resume_msix()
1812 mv->mv_data); in pci_resume_msix()
1816 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, in pci_resume_msix()
1817 msix->msix_ctrl, 2); in pci_resume_msix()
1821 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1829 pcicfgregs *cfg = &dinfo->cfg; in pci_alloc_msix_method()
1840 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_alloc_msix_method()
1841 if (rle != NULL && rle->res != NULL) in pci_alloc_msix_method()
1845 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) in pci_alloc_msix_method()
1848 /* If MSI-X is blacklisted for this system, fail. */ in pci_alloc_msix_method()
1852 /* MSI-X capability present? */ in pci_alloc_msix_method()
1853 if (cfg->msix.msix_location == 0 || !pci_do_msix) in pci_alloc_msix_method()
1857 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, in pci_alloc_msix_method()
1858 cfg->msix.msix_table_bar); in pci_alloc_msix_method()
1859 if (rle == NULL || rle->res == NULL || in pci_alloc_msix_method()
1860 !(rman_get_flags(rle->res) & RF_ACTIVE)) in pci_alloc_msix_method()
1862 cfg->msix.msix_table_res = rle->res; in pci_alloc_msix_method()
1863 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { in pci_alloc_msix_method()
1864 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, in pci_alloc_msix_method()
1865 cfg->msix.msix_pba_bar); in pci_alloc_msix_method()
1866 if (rle == NULL || rle->res == NULL || in pci_alloc_msix_method()
1867 !(rman_get_flags(rle->res) & RF_ACTIVE)) in pci_alloc_msix_method()
1870 cfg->msix.msix_pba_res = rle->res; in pci_alloc_msix_method()
1872 ctrl = pci_read_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, in pci_alloc_msix_method()
1877 "attempting to allocate %d MSI-X vectors (%d supported)\n", in pci_alloc_msix_method()
1888 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, in pci_alloc_msix_method()
1894 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); in pci_alloc_msix_method()
1896 device_printf(child, "using IRQ %ju for MSI-X\n", in pci_alloc_msix_method()
1897 rle->start); in pci_alloc_msix_method()
1906 device_printf(child, "using IRQs %ju", rle->start); in pci_alloc_msix_method()
1907 irq = rle->start; in pci_alloc_msix_method()
1910 rle = resource_list_find(&dinfo->resources, in pci_alloc_msix_method()
1914 if (rle->start == irq + 1) { in pci_alloc_msix_method()
1922 printf("-%d", irq); in pci_alloc_msix_method()
1927 printf(",%ju", rle->start); in pci_alloc_msix_method()
1928 irq = rle->start; in pci_alloc_msix_method()
1933 printf("-%d", irq); in pci_alloc_msix_method()
1934 printf(" for MSI-X\n"); in pci_alloc_msix_method()
1942 cfg->msix.msix_ctrl = ctrl; in pci_alloc_msix_method()
1947 cfg->msix.msix_vectors = mallocarray(actual, sizeof(struct msix_vector), in pci_alloc_msix_method()
1949 cfg->msix.msix_table = mallocarray(actual, in pci_alloc_msix_method()
1952 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_alloc_msix_method()
1953 cfg->msix.msix_vectors[i].mv_irq = rle->start; in pci_alloc_msix_method()
1954 cfg->msix.msix_table[i].mte_vector = i + 1; in pci_alloc_msix_method()
1957 /* Update control register to enable MSI-X. */ in pci_alloc_msix_method()
1959 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, in pci_alloc_msix_method()
1961 cfg->msix.msix_ctrl = ctrl; in pci_alloc_msix_method()
1964 cfg->msix.msix_alloc = actual; in pci_alloc_msix_method()
1965 cfg->msix.msix_table_len = actual; in pci_alloc_msix_method()
1972 * resources consecutively to the first N messages in the MSI-X table.
1975 * populate the MSI-X table sparsely. This method allows the driver
1981 * maps directly to the MSI-X table in that index 0 in the array
1982 * specifies the vector for the first message in the MSI-X table, etc.
1989 * On successful return, each message with a non-zero vector will have
1991 * 1. Additionally, if any of the IRQs allocated via the previous
1992 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1995 * For example, suppose a driver has a MSI-X table with 6 messages and
1999 * have an MSI-X table of ABC--- (where - means no vector assigned).
2001 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
2006 * at MSI-X table index X - 1 and will only be valid if a vector is
2014 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_remap_msix_method()
2021 * table can't be bigger than the actual MSI-X table in the in pci_remap_msix_method()
2024 if (count < 1 || count > PCI_MSIX_MSGNUM(msix->msix_ctrl)) in pci_remap_msix_method()
2029 if (vectors[i] > msix->msix_alloc) in pci_remap_msix_method()
2037 used = mallocarray(msix->msix_alloc, sizeof(*used), M_DEVBUF, M_WAITOK | in pci_remap_msix_method()
2041 used[vectors[i] - 1] = true; in pci_remap_msix_method()
2042 for (i = 0; i < msix->msix_alloc - 1; i++) in pci_remap_msix_method()
2053 for (i = 0; i < msix->msix_table_len; i++) { in pci_remap_msix_method()
2054 if (msix->msix_table[i].mte_vector == 0) in pci_remap_msix_method()
2056 if (msix->msix_table[i].mte_handlers > 0) { in pci_remap_msix_method()
2060 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_remap_msix_method()
2062 if (rle->res != NULL) { in pci_remap_msix_method()
2069 for (i = 0; i < msix->msix_table_len; i++) { in pci_remap_msix_method()
2070 if (msix->msix_table[i].mte_vector == 0) in pci_remap_msix_method()
2072 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_remap_msix_method()
2079 free(msix->msix_table, M_DEVBUF); in pci_remap_msix_method()
2080 msix->msix_table = mallocarray(count, sizeof(struct msix_table_entry), in pci_remap_msix_method()
2083 msix->msix_table[i].mte_vector = vectors[i]; in pci_remap_msix_method()
2084 msix->msix_table_len = count; in pci_remap_msix_method()
2086 /* Free any unused IRQs and resize the vectors array if necessary. */ in pci_remap_msix_method()
2087 j = msix->msix_alloc - 1; in pci_remap_msix_method()
2093 msix->msix_vectors[j].mv_irq); in pci_remap_msix_method()
2094 j--; in pci_remap_msix_method()
2098 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * in pci_remap_msix_method()
2100 free(msix->msix_vectors, M_DEVBUF); in pci_remap_msix_method()
2101 msix->msix_vectors = vec; in pci_remap_msix_method()
2102 msix->msix_alloc = j + 1; in pci_remap_msix_method()
2106 /* Map the IRQs onto the rids. */ in pci_remap_msix_method()
2110 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; in pci_remap_msix_method()
2111 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, in pci_remap_msix_method()
2116 device_printf(child, "Remapped MSI-X IRQs as: "); in pci_remap_msix_method()
2121 printf("---"); in pci_remap_msix_method()
2124 msix->msix_vectors[vectors[i] - 1].mv_irq); in pci_remap_msix_method()
2136 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_release_msix()
2141 if (msix->msix_alloc == 0) in pci_release_msix()
2145 for (i = 0; i < msix->msix_table_len; i++) { in pci_release_msix()
2146 if (msix->msix_table[i].mte_vector == 0) in pci_release_msix()
2148 if (msix->msix_table[i].mte_handlers > 0) in pci_release_msix()
2150 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msix()
2152 if (rle->res != NULL) in pci_release_msix()
2156 /* Update control register to disable MSI-X. */ in pci_release_msix()
2157 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; in pci_release_msix()
2158 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, in pci_release_msix()
2159 msix->msix_ctrl, 2); in pci_release_msix()
2162 for (i = 0; i < msix->msix_table_len; i++) { in pci_release_msix()
2163 if (msix->msix_table[i].mte_vector == 0) in pci_release_msix()
2165 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msix()
2167 free(msix->msix_table, M_DEVBUF); in pci_release_msix()
2168 msix->msix_table_len = 0; in pci_release_msix()
2170 /* Release the IRQs. */ in pci_release_msix()
2171 for (i = 0; i < msix->msix_alloc; i++) in pci_release_msix()
2173 msix->msix_vectors[i].mv_irq); in pci_release_msix()
2174 free(msix->msix_vectors, M_DEVBUF); in pci_release_msix()
2175 msix->msix_alloc = 0; in pci_release_msix()
2180 * Return the max supported MSI-X messages this device supports.
2189 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_count_method()
2192 if (pci_do_msix && msix->msix_location != 0) { in pci_msix_count_method()
2193 ctrl = pci_read_config(child, msix->msix_location + in pci_msix_count_method()
2204 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_pba_bar_method()
2206 if (pci_do_msix && msix->msix_location != 0) in pci_msix_pba_bar_method()
2207 return (msix->msix_pba_bar); in pci_msix_pba_bar_method()
2208 return (-1); in pci_msix_pba_bar_method()
2215 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_table_bar_method()
2217 if (pci_do_msix && msix->msix_location != 0) in pci_msix_table_bar_method()
2218 return (msix->msix_table_bar); in pci_msix_table_bar_method()
2219 return (-1); in pci_msix_table_bar_method()
2229 struct pcicfg_ht *ht = &dinfo->cfg.ht; in pci_ht_map_msi()
2231 if (!ht->ht_msimap) in pci_ht_map_msi()
2234 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && in pci_ht_map_msi()
2235 ht->ht_msiaddr >> 20 == addr >> 20) { in pci_ht_map_msi()
2236 /* Enable MSI -> HT mapping. */ in pci_ht_map_msi()
2237 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; in pci_ht_map_msi()
2238 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, in pci_ht_map_msi()
2239 ht->ht_msictrl, 2); in pci_ht_map_msi()
2242 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { in pci_ht_map_msi()
2243 /* Disable MSI -> HT mapping. */ in pci_ht_map_msi()
2244 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; in pci_ht_map_msi()
2245 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, in pci_ht_map_msi()
2246 ht->ht_msictrl, 2); in pci_ht_map_msi()
2257 cap = dinfo->cfg.pcie.pcie_location; in pci_get_relaxed_ordering_enabled()
2272 cap = dinfo->cfg.pcie.pcie_location; in pci_get_max_payload()
2288 cap = dinfo->cfg.pcie.pcie_location; in pci_get_max_read_req()
2304 cap = dinfo->cfg.pcie.pcie_location; in pci_set_max_read_req()
2311 size = (1 << (fls(size) - 1)); in pci_set_max_read_req()
2314 val |= (fls(size) - 8) << 12; in pci_set_max_read_req()
2325 cap = dinfo->cfg.pcie.pcie_location; in pcie_read_config()
2341 cap = dinfo->cfg.pcie.pcie_location; in pcie_write_config()
2348 * Adjusts a PCI-e capability register by clearing the bits in mask
2362 cap = dinfo->cfg.pcie.pcie_location; in pcie_adjust_config()
2384 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_enable_msi_method()
2387 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, in pci_enable_msi_method()
2389 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { in pci_enable_msi_method()
2390 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, in pci_enable_msi_method()
2392 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, in pci_enable_msi_method()
2395 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, in pci_enable_msi_method()
2399 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; in pci_enable_msi_method()
2400 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_enable_msi_method()
2401 msi->msi_ctrl, 2); in pci_enable_msi_method()
2403 /* Enable MSI -> HT mapping. */ in pci_enable_msi_method()
2411 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_disable_msi_method()
2413 /* Disable MSI -> HT mapping. */ in pci_disable_msi_method()
2417 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; in pci_disable_msi_method()
2418 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_disable_msi_method()
2419 msi->msi_ctrl, 2); in pci_disable_msi_method()
2431 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_resume_msi()
2435 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { in pci_resume_msi()
2436 address = msi->msi_addr; in pci_resume_msi()
2437 data = msi->msi_data; in pci_resume_msi()
2438 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, in pci_resume_msi()
2440 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { in pci_resume_msi()
2441 pci_write_config(dev, msi->msi_location + in pci_resume_msi()
2443 pci_write_config(dev, msi->msi_location + in pci_resume_msi()
2446 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, in pci_resume_msi()
2449 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, in pci_resume_msi()
2457 pcicfgregs *cfg = &dinfo->cfg; in pci_remap_intr_method()
2468 * of MSI IRQs. If we find it, we request updated address and in pci_remap_intr_method()
2471 if (cfg->msi.msi_alloc > 0) { in pci_remap_intr_method()
2473 if (cfg->msi.msi_handlers == 0) in pci_remap_intr_method()
2475 for (i = 0; i < cfg->msi.msi_alloc; i++) { in pci_remap_intr_method()
2476 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, in pci_remap_intr_method()
2478 if (rle->start == irq) { in pci_remap_intr_method()
2484 dinfo->cfg.msi.msi_addr = addr; in pci_remap_intr_method()
2485 dinfo->cfg.msi.msi_data = data; in pci_remap_intr_method()
2494 * For MSI-X, we check to see if we have this IRQ. If we do, in pci_remap_intr_method()
2498 if (cfg->msix.msix_alloc > 0) { in pci_remap_intr_method()
2501 for (i = 0; i < cfg->msix.msix_alloc; i++) { in pci_remap_intr_method()
2502 mv = &cfg->msix.msix_vectors[i]; in pci_remap_intr_method()
2503 if (mv->mv_irq == irq) { in pci_remap_intr_method()
2508 mv->mv_address = addr; in pci_remap_intr_method()
2509 mv->mv_data = data; in pci_remap_intr_method()
2510 for (j = 0; j < cfg->msix.msix_table_len; j++) { in pci_remap_intr_method()
2511 mte = &cfg->msix.msix_table[j]; in pci_remap_intr_method()
2512 if (mte->mte_vector != i + 1) in pci_remap_intr_method()
2514 if (mte->mte_handlers == 0) in pci_remap_intr_method()
2546 * host-PCI bridge at device 0:0:0. In the future, it may become
2558 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ in pci_msi_blacklisted()
2580 * Returns true if the specified device is blacklisted because MSI-X
2582 * MSI-X doesn't either.
2598 * Determine if MSI-X is blacklisted globally on this system. If MSI
2599 * is blacklisted, assume that MSI-X is as well. Check for additional
2600 * chipsets where MSI works but MSI-X does not.
2627 pcicfgregs *cfg = &dinfo->cfg; in pci_alloc_msi_method()
2630 int error, irqs[32]; in pci_alloc_msi_method() local
2638 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_alloc_msi_method()
2639 if (rle != NULL && rle->res != NULL) in pci_alloc_msi_method()
2643 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) in pci_alloc_msi_method()
2651 if (cfg->msi.msi_location == 0 || !pci_do_msi) in pci_alloc_msi_method()
2654 ctrl = pci_read_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 2); in pci_alloc_msi_method()
2674 actual, irqs); in pci_alloc_msi_method()
2686 * resources in the irqs[] array, so add new resources in pci_alloc_msi_method()
2690 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, in pci_alloc_msi_method()
2691 irqs[i], irqs[i], 1); in pci_alloc_msi_method()
2695 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); in pci_alloc_msi_method()
2704 device_printf(child, "using IRQs %d", irqs[0]); in pci_alloc_msi_method()
2708 if (irqs[i] == irqs[i - 1] + 1) { in pci_alloc_msi_method()
2715 printf("-%d", irqs[i - 1]); in pci_alloc_msi_method()
2720 printf(",%d", irqs[i]); in pci_alloc_msi_method()
2725 printf("-%d", irqs[actual - 1]); in pci_alloc_msi_method()
2732 ctrl |= (ffs(actual) - 1) << 4; in pci_alloc_msi_method()
2733 cfg->msi.msi_ctrl = ctrl; in pci_alloc_msi_method()
2734 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); in pci_alloc_msi_method()
2737 cfg->msi.msi_alloc = actual; in pci_alloc_msi_method()
2738 cfg->msi.msi_handlers = 0; in pci_alloc_msi_method()
2748 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_release_msi_method()
2750 u_int i, irqs[32]; in pci_release_msi_method() local
2753 /* Try MSI-X first. */ in pci_release_msi_method()
2759 if (msi->msi_alloc == 0) in pci_release_msi_method()
2761 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); in pci_release_msi_method()
2764 if (msi->msi_handlers > 0) in pci_release_msi_method()
2766 for (i = 0; i < msi->msi_alloc; i++) { in pci_release_msi_method()
2767 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msi_method()
2769 if (rle->res != NULL) in pci_release_msi_method()
2771 irqs[i] = rle->start; in pci_release_msi_method()
2775 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), in pci_release_msi_method()
2777 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; in pci_release_msi_method()
2778 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_release_msi_method()
2779 msi->msi_ctrl, 2); in pci_release_msi_method()
2782 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); in pci_release_msi_method()
2783 for (i = 0; i < msi->msi_alloc; i++) in pci_release_msi_method()
2784 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msi_method()
2787 msi->msi_alloc = 0; in pci_release_msi_method()
2788 msi->msi_addr = 0; in pci_release_msi_method()
2789 msi->msi_data = 0; in pci_release_msi_method()
2803 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_msi_count_method()
2806 if (pci_do_msi && msi->msi_location != 0) { in pci_msi_count_method()
2807 ctrl = pci_read_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_msi_count_method()
2824 if (dinfo->cfg.vpd.vpd_reg) in pci_freecfg()
2825 vpd_free(&dinfo->cfg.vpd); in pci_freecfg()
2827 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { in pci_freecfg()
2837 pci_numdevs--; in pci_freecfg()
2848 pcicfgregs *cfg = &dinfo->cfg; in pci_set_powerstate_method()
2852 if (cfg->pp.pp_location == 0) in pci_set_powerstate_method()
2858 * behavior when going from D3 -> D3. in pci_set_powerstate_method()
2883 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + in pci_set_powerstate_method()
2890 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) in pci_set_powerstate_method()
2895 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) in pci_set_powerstate_method()
2911 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_location + PCIR_POWER_STATUS, in pci_set_powerstate_method()
2922 pcicfgregs *cfg = &dinfo->cfg; in pci_get_powerstate_method()
2926 if (cfg->pp.pp_location != 0) { in pci_get_powerstate_method()
2927 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + in pci_get_powerstate_method()
2958 pcicfgregs *cfg = &dinfo->cfg; in pci_clear_pme()
2961 if (cfg->pp.pp_location != 0) { in pci_clear_pme()
2962 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + in pci_clear_pme()
2966 pci_write_config(dev, dinfo->cfg.pp.pp_location + in pci_clear_pme()
2976 pcicfgregs *cfg = &dinfo->cfg; in pci_enable_pme()
2979 if (cfg->pp.pp_location != 0) { in pci_enable_pme()
2980 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + in pci_enable_pme()
2983 pci_write_config(dev, dinfo->cfg.pp.pp_location + in pci_enable_pme()
2992 pcicfgregs *cfg = &dinfo->cfg; in pci_has_pm()
2994 return (cfg->pp.pp_location != 0); in pci_has_pm()
3074 * New style pci driver. Parent device is either a pci-host-bridge or a
3075 * pci-pci-bridge. Both kinds are represented by instances of pcib.
3083 pcicfgregs *cfg = &dinfo->cfg; in pci_print_verbose()
3085 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", in pci_print_verbose()
3086 cfg->vendor, cfg->device, cfg->revid); in pci_print_verbose()
3088 cfg->domain, cfg->bus, cfg->slot, cfg->func); in pci_print_verbose()
3089 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", in pci_print_verbose()
3090 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, in pci_print_verbose()
3091 cfg->mfdev); in pci_print_verbose()
3093 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); in pci_print_verbose()
3095 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, in pci_print_verbose()
3096 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); in pci_print_verbose()
3097 if (cfg->intpin > 0) in pci_print_verbose()
3099 cfg->intpin +'a' -1, cfg->intline); in pci_print_verbose()
3100 if (cfg->pp.pp_location) { in pci_print_verbose()
3103 status = pci_read_config(cfg->dev, cfg->pp.pp_location + in pci_print_verbose()
3106 cfg->pp.pp_cap & PCIM_PCAP_SPEC, in pci_print_verbose()
3107 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", in pci_print_verbose()
3108 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", in pci_print_verbose()
3111 if (cfg->msi.msi_location) { in pci_print_verbose()
3114 ctrl = cfg->msi.msi_ctrl; in pci_print_verbose()
3121 if (cfg->msix.msix_location) { in pci_print_verbose()
3124 msgnum = PCI_MSIX_MSGNUM(cfg->msix.msix_ctrl); in pci_print_verbose()
3125 printf("\tMSI-X supports %d message%s ", in pci_print_verbose()
3127 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) in pci_print_verbose()
3129 cfg->msix.msix_table_bar); in pci_print_verbose()
3132 cfg->msix.msix_table_bar, in pci_print_verbose()
3133 cfg->msix.msix_pba_bar); in pci_print_verbose()
3160 * The device ROM BAR is special. It is always a 32-bit in pci_read_bar()
3165 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { in pci_read_bar()
3198 * and combines the result into a 64-bit value." (section 6.2.5.1) in pci_read_bar()
3213 * the BAR of the low-level console device and when booting verbose, in pci_read_bar()
3233 /* The device ROM BAR is always a 32-bit memory BAR. */ in pci_write_bar()
3235 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) in pci_write_bar()
3238 ln2range = pci_maprange(pm->pm_value); in pci_write_bar()
3239 pci_write_config(dev, pm->pm_reg, base, 4); in pci_write_bar()
3241 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); in pci_write_bar()
3242 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); in pci_write_bar()
3244 pm->pm_value |= (pci_addr_t)pci_read_config(dev, in pci_write_bar()
3245 pm->pm_reg + 4, 4) << 32; in pci_write_bar()
3255 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { in pci_find_bar()
3256 if (pm->pm_reg == reg) in pci_find_bar()
3268 return (STAILQ_FIRST(&dinfo->cfg.maps)); in pci_first_bar()
3284 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && in pci_bar_enabled()
3285 !(pm->pm_value & PCIM_BIOS_ENABLE)) in pci_bar_enabled()
3288 if ((dinfo->cfg.flags & PCICFG_VF) != 0) { in pci_bar_enabled()
3291 iov = dinfo->cfg.iov; in pci_bar_enabled()
3292 cmd = pci_read_config(iov->iov_pf, in pci_bar_enabled()
3293 iov->iov_pos + PCIR_SRIOV_CTL, 2); in pci_bar_enabled()
3298 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) in pci_bar_enabled()
3312 pm->pm_reg = reg; in pci_add_bar()
3313 pm->pm_value = value; in pci_add_bar()
3314 pm->pm_size = size; in pci_add_bar()
3315 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { in pci_add_bar()
3316 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", in pci_add_bar()
3319 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) in pci_add_bar()
3323 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); in pci_add_bar()
3325 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); in pci_add_bar()
3337 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { in pci_restore_bars()
3338 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) in pci_restore_bars()
3341 ln2range = pci_maprange(pm->pm_value); in pci_restore_bars()
3342 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); in pci_restore_bars()
3344 pci_write_config(dev, pm->pm_reg + 4, in pci_restore_bars()
3345 pm->pm_value >> 32, 4); in pci_restore_bars()
3370 maprange = pci_maprange(pm->pm_value); in pci_add_map()
3474 end = base + count - 1; in pci_add_map()
3588 pcicfgregs *cfg = &dinfo->cfg; in pci_assign_interrupt()
3593 if (cfg->intpin == 0) in pci_assign_interrupt()
3600 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); in pci_assign_interrupt()
3612 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) in pci_assign_interrupt()
3615 irq = cfg->intline; in pci_assign_interrupt()
3623 if (irq != cfg->intline) { in pci_assign_interrupt()
3624 cfg->intline = irq; in pci_assign_interrupt()
3629 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); in pci_assign_interrupt()
3769 eec = -1; in xhci_early_takeover()
3820 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_reserve_secbus()
3885 count = end - start + 1; in pci_reserve_secbus()
3927 cfg = &dinfo->cfg; in pci_alloc_secbus()
3928 rl = &dinfo->resources; in pci_alloc_secbus()
3929 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_alloc_secbus()
3976 iov = dinfo->cfg.iov; in pci_ea_bei_to_rid()
3978 iov_pos = iov->iov_pos; in pci_ea_bei_to_rid()
3996 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + in pci_ea_bei_to_rid()
4000 return (-1); in pci_ea_bei_to_rid()
4011 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { in pci_ea_is_enabled()
4012 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) in pci_ea_is_enabled()
4013 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); in pci_ea_is_enabled()
4034 rl = &dinfo->resources; in pci_add_resources_ea()
4038 iov = dinfo->cfg.iov; in pci_add_resources_ea()
4041 if (dinfo->cfg.ea.ea_location == 0) in pci_add_resources_ea()
4044 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { in pci_add_resources_ea()
4046 * TODO: Ignore EA-BAR if is not enabled. in pci_add_resources_ea()
4051 * a legacy-BAR mechanism. in pci_add_resources_ea()
4053 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) in pci_add_resources_ea()
4056 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { in pci_add_resources_ea()
4075 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || in pci_add_resources_ea()
4076 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) in pci_add_resources_ea()
4083 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || in pci_add_resources_ea()
4084 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && in pci_add_resources_ea()
4085 (ea->eae_bei != PCIM_EA_BEI_ROM)) in pci_add_resources_ea()
4089 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); in pci_add_resources_ea()
4098 start = ea->eae_base; in pci_add_resources_ea()
4099 count = ea->eae_max_offset + 1; in pci_add_resources_ea()
4102 count = count * iov->iov_num_vfs; in pci_add_resources_ea()
4104 end = start + count - 1; in pci_add_resources_ea()
4119 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); in pci_add_resources_ea()
4121 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); in pci_add_resources_ea()
4127 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); in pci_add_resources_ea()
4148 cfg = &dinfo->cfg; in pci_add_resources()
4149 rl = &dinfo->resources; in pci_add_resources()
4150 devid = (cfg->device << 16) | cfg->vendor; in pci_add_resources()
4163 for (i = 0; i < cfg->nummaps;) { in pci_add_resources()
4175 for (q = &pci_quirks[0]; q->devid != 0; q++) in pci_add_resources()
4176 if (q->devid == devid && in pci_add_resources()
4177 q->type == PCI_QUIRK_UNMAP_REG && in pci_add_resources()
4178 q->arg1 == PCIR_BAR(i)) in pci_add_resources()
4180 if (q->devid != 0) { in pci_add_resources()
4191 for (q = &pci_quirks[0]; q->devid != 0; q++) in pci_add_resources()
4192 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) in pci_add_resources()
4193 pci_add_map(bus, dev, q->arg1, rl, force, 0); in pci_add_resources()
4195 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline) && in pci_add_resources()
4198 * Try to re-route interrupts. Sometimes the BIOS or in pci_add_resources()
4200 * If the re-route fails, then just stick with what we in pci_add_resources()
4257 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); in pci_add_children()
4396 vf_dinfo->cfg.flags |= PCICFG_VF; in pci_add_iov_child()
4399 return (vf_dinfo->cfg.dev); in pci_add_iov_child()
4421 if (dinfo->cfg.pcie.pcie_location == 0) in pcie_setup_mps()
4457 if (dinfo->cfg.pcie.pcie_location != 0 && in pci_add_child_clear_aer()
4458 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { in pci_add_child_clear_aer()
4459 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4463 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4470 pci_printf(&dinfo->cfg, in pci_add_child_clear_aer()
4471 "clearing AER UC 0x%08x -> 0x%08x\n", in pci_add_child_clear_aer()
4499 pci_printf(&dinfo->cfg, in pci_add_child_clear_aer()
4500 "clearing AER COR 0x%08x -> 0x%08x\n", in pci_add_child_clear_aer()
4516 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4520 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4530 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY); in pci_add_child()
4532 resource_list_init(&dinfo->resources); in pci_add_child()
4540 pci_child_added(dinfo->cfg.dev); in pci_add_child()
4545 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); in pci_add_child()
4575 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, in pci_attach_common()
4577 if (sc->sc_bus == NULL) { in pci_attach_common()
4584 sc->sc_dma_tag = bus_get_dma_tag(dev); in pci_attach_common()
4620 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); in pci_detach()
4703 * as MSI/MSI-X interrupts are never shared. in pci_suspend_child()
4705 rle = resource_list_find(&dinfo->resources, in pci_suspend_child()
4707 if (rle != NULL && rle->res != NULL) in pci_suspend_child()
4708 (void)bus_suspend_intr(child, rle->res); in pci_suspend_child()
4737 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_resume_child()
4738 if (rle != NULL && rle->res != NULL) in pci_resume_child()
4739 (void)bus_resume_intr(child, rle->res); in pci_resume_child()
4825 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); in pci_driver_added()
4862 * Check to see if the interrupt is MSI or MSI-X. in pci_setup_intr()
4869 if (dinfo->cfg.msi.msi_alloc > 0) { in pci_setup_intr()
4870 if (dinfo->cfg.msi.msi_addr == 0) { in pci_setup_intr()
4871 KASSERT(dinfo->cfg.msi.msi_handlers == 0, in pci_setup_intr()
4877 dinfo->cfg.msi.msi_addr = addr; in pci_setup_intr()
4878 dinfo->cfg.msi.msi_data = data; in pci_setup_intr()
4880 if (dinfo->cfg.msi.msi_handlers == 0) in pci_setup_intr()
4881 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, in pci_setup_intr()
4882 dinfo->cfg.msi.msi_data); in pci_setup_intr()
4883 dinfo->cfg.msi.msi_handlers++; in pci_setup_intr()
4885 KASSERT(dinfo->cfg.msix.msix_alloc > 0, in pci_setup_intr()
4886 ("No MSI or MSI-X interrupts allocated")); in pci_setup_intr()
4887 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, in pci_setup_intr()
4888 ("MSI-X index too high")); in pci_setup_intr()
4889 mte = &dinfo->cfg.msix.msix_table[rid - 1]; in pci_setup_intr()
4890 KASSERT(mte->mte_vector != 0, ("no message vector")); in pci_setup_intr()
4891 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; in pci_setup_intr()
4892 KASSERT(mv->mv_irq == rman_get_start(irq), in pci_setup_intr()
4894 if (mv->mv_address == 0) { in pci_setup_intr()
4895 KASSERT(mte->mte_handlers == 0, in pci_setup_intr()
4896 ("MSI-X table entry has handlers, but vector not mapped")); in pci_setup_intr()
4901 mv->mv_address = addr; in pci_setup_intr()
4902 mv->mv_data = data; in pci_setup_intr()
4912 mte->mte_handlers++; in pci_setup_intr()
4913 if (mte->mte_handlers == 1) { in pci_setup_intr()
4914 pci_enable_msix(child, rid - 1, mv->mv_address, in pci_setup_intr()
4915 mv->mv_data); in pci_setup_intr()
4916 pci_unmask_msix(child, rid - 1); in pci_setup_intr()
4921 * Make sure that INTx is disabled if we are using MSI/MSI-X, in pci_setup_intr()
4923 * in which case we "enable" INTx so MSI/MSI-X actually works. in pci_setup_intr()
4963 * Check to see if the interrupt is MSI or MSI-X. If so, in pci_teardown_intr()
4965 * MSI-X message, or disable MSI messages if the count in pci_teardown_intr()
4969 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); in pci_teardown_intr()
4970 if (rle->res != irq) in pci_teardown_intr()
4972 if (dinfo->cfg.msi.msi_alloc > 0) { in pci_teardown_intr()
4973 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, in pci_teardown_intr()
4974 ("MSI-X index too high")); in pci_teardown_intr()
4975 if (dinfo->cfg.msi.msi_handlers == 0) in pci_teardown_intr()
4977 dinfo->cfg.msi.msi_handlers--; in pci_teardown_intr()
4978 if (dinfo->cfg.msi.msi_handlers == 0) in pci_teardown_intr()
4981 KASSERT(dinfo->cfg.msix.msix_alloc > 0, in pci_teardown_intr()
4982 ("No MSI or MSI-X interrupts allocated")); in pci_teardown_intr()
4983 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, in pci_teardown_intr()
4984 ("MSI-X index too high")); in pci_teardown_intr()
4985 mte = &dinfo->cfg.msix.msix_table[rid - 1]; in pci_teardown_intr()
4986 if (mte->mte_handlers == 0) in pci_teardown_intr()
4988 mte->mte_handlers--; in pci_teardown_intr()
4989 if (mte->mte_handlers == 0) in pci_teardown_intr()
4990 pci_mask_msix(child, rid - 1); in pci_teardown_intr()
4996 ("%s: generic teardown failed for MSI/MSI-X", __func__)); in pci_teardown_intr()
5008 rl = &dinfo->resources; in pci_print_child()
5034 {PCIC_OLD, -1, 1, "old"},
5035 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"},
5036 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"},
5037 {PCIC_STORAGE, -1, 1, "mass storage"},
5047 {PCIC_NETWORK, -1, 1, "network"},
5053 {PCIC_DISPLAY, -1, 1, "display"},
5057 {PCIC_MULTIMEDIA, -1, 1, "multimedia"},
5062 {PCIC_MEMORY, -1, 1, "memory"},
5065 {PCIC_BRIDGE, -1, 1, "bridge"},
5066 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"},
5067 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"},
5068 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"},
5069 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"},
5070 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"},
5071 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"},
5072 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"},
5073 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"},
5074 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"},
5075 {PCIC_SIMPLECOMM, -1, 1, "simple comms"},
5080 {PCIC_BASEPERIPH, -1, 0, "base peripheral"},
5085 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"},
5088 {PCIC_INPUTDEV, -1, 1, "input device"},
5094 {PCIC_DOCKING, -1, 1, "docking station"},
5095 {PCIC_PROCESSOR, -1, 1, "processor"},
5096 {PCIC_SERIALBUS, -1, 1, "serial bus"},
5103 {PCIC_WIRELESS, -1, 1, "wireless controller"},
5107 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"},
5109 {PCIC_SATCOM, -1, 1, "satellite communication"},
5114 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"},
5117 {PCIC_DASP, -1, 0, "dasp"},
5122 {PCIC_INSTRUMENT, -1, 0, "non-essential instrumentation"},
5149 if (pci_nomatch_tab[i].subclass == -1) { in pci_probe_nomatch()
5180 rl = &dinfo->resources; in pci_child_detached()
5183 * Have to deallocate IRQs before releasing any MSI messages and in pci_child_detached()
5188 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); in pci_child_detached()
5189 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { in pci_child_detached()
5190 if (dinfo->cfg.msi.msi_alloc != 0) in pci_child_detached()
5191 pci_printf(&dinfo->cfg, "Device leaked %d MSI " in pci_child_detached()
5192 "vectors\n", dinfo->cfg.msi.msi_alloc); in pci_child_detached()
5194 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " in pci_child_detached()
5195 "vectors\n", dinfo->cfg.msix.msix_alloc); in pci_child_detached()
5199 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); in pci_child_detached()
5201 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); in pci_child_detached()
5203 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); in pci_child_detached()
5221 * - devices cannot be listed without a corresponding VENDOR line.
5230 * is set to -1. Returns nonzero at the end of the database.
5242 *device = -1; in pci_describe_parse_line()
5243 *vendor = -1; in pci_describe_parse_line()
5246 left = pci_vendordata_size - (cp - pci_vendordata); in pci_describe_parse_line()
5264 left--; in pci_describe_parse_line()
5268 left--; in pci_describe_parse_line()
5274 left--; in pci_describe_parse_line()
5315 if (vendor != -1) { in pci_describe_device()
5342 cfg = &dinfo->cfg; in pci_read_ivar()
5353 *result = cfg->subvendor; in pci_read_ivar()
5356 *result = cfg->subdevice; in pci_read_ivar()
5359 *result = cfg->vendor; in pci_read_ivar()
5362 *result = cfg->device; in pci_read_ivar()
5365 *result = (cfg->device << 16) | cfg->vendor; in pci_read_ivar()
5368 *result = cfg->baseclass; in pci_read_ivar()
5371 *result = cfg->subclass; in pci_read_ivar()
5374 *result = cfg->progif; in pci_read_ivar()
5377 *result = cfg->revid; in pci_read_ivar()
5380 *result = cfg->intpin; in pci_read_ivar()
5383 *result = cfg->intline; in pci_read_ivar()
5386 *result = cfg->domain; in pci_read_ivar()
5389 *result = cfg->bus; in pci_read_ivar()
5392 *result = cfg->slot; in pci_read_ivar()
5395 *result = cfg->func; in pci_read_ivar()
5398 *result = cfg->cmdreg; in pci_read_ivar()
5401 *result = cfg->cachelnsz; in pci_read_ivar()
5404 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { in pci_read_ivar()
5405 *result = -1; in pci_read_ivar()
5408 *result = cfg->mingnt; in pci_read_ivar()
5411 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { in pci_read_ivar()
5412 *result = -1; in pci_read_ivar()
5415 *result = cfg->maxlat; in pci_read_ivar()
5418 *result = cfg->lattimer; in pci_read_ivar()
5435 dinfo->cfg.intpin = value; in pci_write_ivar()
5489 if (dinfo->cfg.dev) in DB_SHOW_COMMAND_FLAGS()
5490 name = device_get_name(dinfo->cfg.dev); in DB_SHOW_COMMAND_FLAGS()
5492 p = &dinfo->conf; in DB_SHOW_COMMAND_FLAGS()
5496 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : in DB_SHOW_COMMAND_FLAGS()
5498 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, in DB_SHOW_COMMAND_FLAGS()
5499 p->pc_sel.pc_func, (p->pc_class << 16) | in DB_SHOW_COMMAND_FLAGS()
5500 (p->pc_subclass << 8) | p->pc_progif, in DB_SHOW_COMMAND_FLAGS()
5501 (p->pc_subdevice << 16) | p->pc_subvendor, in DB_SHOW_COMMAND_FLAGS()
5502 (p->pc_device << 16) | p->pc_vendor, in DB_SHOW_COMMAND_FLAGS()
5503 p->pc_revid, p->pc_hdr); in DB_SHOW_COMMAND_FLAGS()
5510 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, in pci_reserve_map() argument
5514 struct resource_list *rl = &dinfo->resources; in pci_reserve_map()
5530 mapsize = pm->pm_size; in pci_reserve_map()
5531 map = pm->pm_value; in pci_reserve_map()
5547 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) in pci_reserve_map()
5556 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { in pci_reserve_map()
5583 count = ((pci_addr_t)1 << mapsize) * num; in pci_reserve_map()
5624 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, in pci_alloc_multi_resource() argument
5637 rl = &dinfo->resources; in pci_alloc_multi_resource()
5638 cfg = &dinfo->cfg; in pci_alloc_multi_resource()
5648 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || in pci_alloc_multi_resource()
5649 cfg->msix.msix_alloc > 0)) in pci_alloc_multi_resource()
5657 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && in pci_alloc_multi_resource()
5658 (cfg->intpin != 0)) in pci_alloc_multi_resource()
5664 * PCI-PCI bridge I/O window resources are not BARs. in pci_alloc_multi_resource()
5668 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { in pci_alloc_multi_resource()
5685 count, num, flags); in pci_alloc_multi_resource()
5708 if (dinfo->cfg.flags & PCICFG_VF) { in pci_alloc_resource()
5737 cfg = &dinfo->cfg; in pci_release_resource()
5740 if (cfg->flags & PCICFG_VF) { in pci_release_resource()
5754 * PCI-PCI bridge I/O window resources are not BARs. For in pci_release_resource()
5757 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && in pci_release_resource()
5768 rl = &dinfo->resources; in pci_release_resource()
5783 if (dinfo->cfg.flags & PCICFG_VF) { in pci_activate_resource()
5806 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) in pci_activate_resource()
5831 if (dinfo->cfg.flags & PCICFG_VF) { in pci_deactivate_resource()
5853 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) in pci_deactivate_resource()
5871 if (dinfo->cfg.flags & PCICFG_VF) { in pci_adjust_resource()
5900 if (dinfo->cfg.flags & PCICFG_VF) { in pci_map_resource()
5928 if (dinfo->cfg.flags & PCICFG_VF) { in pci_unmap_resource()
5952 rl = &dinfo->resources; in pci_child_deleted()
5966 if (rle->res) { in pci_child_deleted()
5967 if (rman_get_flags(rle->res) & RF_ACTIVE || in pci_child_deleted()
5968 resource_list_busy(rl, rle->type, rle->rid)) { in pci_child_deleted()
5969 pci_printf(&dinfo->cfg, in pci_child_deleted()
5972 rle->type, rle->rid, in pci_child_deleted()
5973 rman_get_start(rle->res)); in pci_child_deleted()
5974 bus_release_resource(child, rle->type, rle->rid, in pci_child_deleted()
5975 rle->res); in pci_child_deleted()
5977 resource_list_unreserve(rl, dev, child, rle->type, in pci_child_deleted()
5978 rle->rid); in pci_child_deleted()
5997 rl = &dinfo->resources; in pci_delete_resource()
6002 if (rle->res) { in pci_delete_resource()
6003 if (rman_get_flags(rle->res) & RF_ACTIVE || in pci_delete_resource()
6008 type, rid, rman_get_start(rle->res)); in pci_delete_resource()
6021 return (&dinfo->resources); in pci_get_resource_list()
6038 tag = sc->sc_dma_tag; in pci_get_dma_tag()
6048 return (sc->sc_dma_tag); in pci_get_dma_tag()
6056 pcicfgregs *cfg = &dinfo->cfg; in pci_read_config_method()
6060 * SR-IOV VFs don't implement the VID or DID registers, so we have to in pci_read_config_method()
6063 if (cfg->flags & PCICFG_VF) { in pci_read_config_method()
6067 return (cfg->device << 16 | cfg->vendor); in pci_read_config_method()
6069 return (cfg->vendor); in pci_read_config_method()
6071 return (cfg->vendor & 0xff); in pci_read_config_method()
6077 /* Note that an unaligned 4-byte read is an error. */ in pci_read_config_method()
6079 return (cfg->device); in pci_read_config_method()
6081 return (cfg->device & 0xff); in pci_read_config_method()
6090 cfg->bus, cfg->slot, cfg->func, reg, width)); in pci_read_config_method()
6098 pcicfgregs *cfg = &dinfo->cfg; in pci_write_config_method()
6101 cfg->bus, cfg->slot, cfg->func, reg, val, width); in pci_write_config_method()
6121 cfg = &dinfo->cfg; in pci_child_pnpinfo_method()
6123 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, in pci_child_pnpinfo_method()
6124 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, in pci_child_pnpinfo_method()
6125 cfg->progif); in pci_child_pnpinfo_method()
6151 pcicfgregs *cfg = &dinfo->cfg; in pci_assign_interrupt_method()
6154 cfg->intpin)); in pci_assign_interrupt_method()
6168 * Accept pciconf-style selectors of either pciD:B:S:F or in pci_lookup()
6240 cfg = &dinfo->cfg.pcie; in pci_cfg_restore_pcie()
6241 pos = cfg->pcie_location; in pci_cfg_restore_pcie()
6243 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; in pci_cfg_restore_pcie()
6245 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); in pci_cfg_restore_pcie()
6247 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6248 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || in pci_cfg_restore_pcie()
6249 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) in pci_cfg_restore_pcie()
6250 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); in pci_cfg_restore_pcie()
6252 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6253 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && in pci_cfg_restore_pcie()
6254 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) in pci_cfg_restore_pcie()
6255 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); in pci_cfg_restore_pcie()
6257 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6258 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) in pci_cfg_restore_pcie()
6259 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); in pci_cfg_restore_pcie()
6262 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); in pci_cfg_restore_pcie()
6263 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); in pci_cfg_restore_pcie()
6264 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); in pci_cfg_restore_pcie()
6272 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, in pci_cfg_restore_pcix()
6273 dinfo->cfg.pcix.pcix_command, 2); in pci_cfg_restore_pcix()
6290 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); in pci_cfg_restore()
6291 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); in pci_cfg_restore()
6292 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); in pci_cfg_restore()
6293 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); in pci_cfg_restore()
6294 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); in pci_cfg_restore()
6295 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); in pci_cfg_restore()
6296 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { in pci_cfg_restore()
6298 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); in pci_cfg_restore()
6299 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); in pci_cfg_restore()
6303 dinfo->cfg.bridge.br_seclat, 1); in pci_cfg_restore()
6305 dinfo->cfg.bridge.br_subbus, 1); in pci_cfg_restore()
6307 dinfo->cfg.bridge.br_secbus, 1); in pci_cfg_restore()
6309 dinfo->cfg.bridge.br_pribus, 1); in pci_cfg_restore()
6311 dinfo->cfg.bridge.br_control, 2); in pci_cfg_restore()
6315 dinfo->cfg.bridge.br_seclat, 1); in pci_cfg_restore()
6317 dinfo->cfg.bridge.br_subbus, 1); in pci_cfg_restore()
6319 dinfo->cfg.bridge.br_secbus, 1); in pci_cfg_restore()
6321 dinfo->cfg.bridge.br_pribus, 1); in pci_cfg_restore()
6323 dinfo->cfg.bridge.br_control, 2); in pci_cfg_restore()
6328 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) in pci_cfg_restore()
6329 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); in pci_cfg_restore()
6332 * Restore extended capabilities for PCI-Express and PCI-X in pci_cfg_restore()
6334 if (dinfo->cfg.pcie.pcie_location != 0) in pci_cfg_restore()
6336 if (dinfo->cfg.pcix.pcix_location != 0) in pci_cfg_restore()
6339 /* Restore MSI and MSI-X configurations if they are present. */ in pci_cfg_restore()
6340 if (dinfo->cfg.msi.msi_location != 0) in pci_cfg_restore()
6342 if (dinfo->cfg.msix.msix_location != 0) in pci_cfg_restore()
6346 if (dinfo->cfg.iov != NULL) in pci_cfg_restore()
6358 cfg = &dinfo->cfg.pcie; in pci_cfg_save_pcie()
6359 pos = cfg->pcie_location; in pci_cfg_save_pcie()
6361 cfg->pcie_flags = RREG(PCIER_FLAGS); in pci_cfg_save_pcie()
6363 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; in pci_cfg_save_pcie()
6365 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); in pci_cfg_save_pcie()
6367 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6368 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || in pci_cfg_save_pcie()
6369 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) in pci_cfg_save_pcie()
6370 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); in pci_cfg_save_pcie()
6372 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6373 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && in pci_cfg_save_pcie()
6374 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) in pci_cfg_save_pcie()
6375 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); in pci_cfg_save_pcie()
6377 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6378 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) in pci_cfg_save_pcie()
6379 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); in pci_cfg_save_pcie()
6382 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); in pci_cfg_save_pcie()
6383 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); in pci_cfg_save_pcie()
6384 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); in pci_cfg_save_pcie()
6392 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, in pci_cfg_save_pcix()
6393 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); in pci_cfg_save_pcix()
6409 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); in pci_cfg_save()
6410 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); in pci_cfg_save()
6411 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); in pci_cfg_save()
6412 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); in pci_cfg_save()
6413 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); in pci_cfg_save()
6414 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); in pci_cfg_save()
6415 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); in pci_cfg_save()
6416 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); in pci_cfg_save()
6417 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); in pci_cfg_save()
6418 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); in pci_cfg_save()
6419 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); in pci_cfg_save()
6420 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { in pci_cfg_save()
6422 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); in pci_cfg_save()
6423 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); in pci_cfg_save()
6424 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); in pci_cfg_save()
6425 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); in pci_cfg_save()
6428 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, in pci_cfg_save()
6430 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, in pci_cfg_save()
6432 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, in pci_cfg_save()
6434 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, in pci_cfg_save()
6436 dinfo->cfg.bridge.br_control = pci_read_config(dev, in pci_cfg_save()
6440 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, in pci_cfg_save()
6442 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, in pci_cfg_save()
6444 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, in pci_cfg_save()
6446 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, in pci_cfg_save()
6448 dinfo->cfg.bridge.br_control = pci_read_config(dev, in pci_cfg_save()
6450 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); in pci_cfg_save()
6451 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); in pci_cfg_save()
6455 if (dinfo->cfg.pcie.pcie_location != 0) in pci_cfg_save()
6458 if (dinfo->cfg.pcix.pcix_location != 0) in pci_cfg_save()
6462 if (dinfo->cfg.iov != NULL) in pci_cfg_save()
6541 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); in pci_find_pcie_root_port()
6544 * Walk the bridge hierarchy until we find a PCI-e root in pci_find_pcie_root_port()
6545 * port or a non-PCI device. in pci_find_pcie_root_port()
6558 * PCI-PCI bridge. in pci_find_pcie_root_port()
6564 if (dinfo->cfg.pcie.pcie_location != 0 && in pci_find_pcie_root_port()
6565 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) in pci_find_pcie_root_port()
6573 * Wait for pending transactions to complete on a PCI-express function.
6579 * exceeded. If dev is not a PCI-express function, this returns true.
6588 cap = dinfo->cfg.pcie.pcie_location; in pcie_wait_for_pending_transactions()
6600 max_delay -= 100; in pcie_wait_for_pending_transactions()
6615 * For non-PCI-express functions this returns 0.
6623 cap = dinfo->cfg.pcie.pcie_location; in pcie_get_max_completion_timeout()
6632 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || in pcie_get_max_completion_timeout()
6672 s = "Uncorrectable (Non-Fatal)"; in pcie_apei_error()
6708 if (dinfo->cfg.pcie.pcie_location != 0) { in pcie_apei_error()
6709 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pcie_apei_error()
6714 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pcie_apei_error()
6729 * If dev is not a PCI-express function or does not support FLR, this
6734 * PCI-standard registers via pci_save_state() and
6745 cap = dinfo->cfg.pcie.pcie_location; in pcie_flr()
6758 * which will re-enable busmastering. in pcie_flr()
6767 pci_printf(&dinfo->cfg, in pcie_flr()
6772 * Extend the post-FLR delay to cover the maximum in pcie_flr()
6793 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); in pcie_flr()
6798 * Attempt a power-management reset by cycling the device in/out of D3
6898 while (nelt-- > 0) { in pci_match_device()
6900 if (id->match_flag_vendor) in pci_match_device()
6901 match &= vendor == id->vendor; in pci_match_device()
6902 if (id->match_flag_device) in pci_match_device()
6903 match &= device == id->device; in pci_match_device()
6904 if (id->match_flag_subvendor) in pci_match_device()
6905 match &= subvendor == id->subvendor; in pci_match_device()
6906 if (id->match_flag_subdevice) in pci_match_device()
6907 match &= subdevice == id->subdevice; in pci_match_device()
6908 if (id->match_flag_class) in pci_match_device()
6909 match &= class == id->class_id; in pci_match_device()
6910 if (id->match_flag_subclass) in pci_match_device()
6911 match &= subclass == id->subclass; in pci_match_device()
6912 if (id->match_flag_revid) in pci_match_device()
6913 match &= revid == id->revid; in pci_match_device()
6927 dev = dinfo->cfg.dev; in pci_print_faulted_dev_name()
6928 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, in pci_print_faulted_dev_name()
6929 dinfo->cfg.slot, dinfo->cfg.func); in pci_print_faulted_dev_name()
6945 dev = dinfo->cfg.dev; in pci_print_faulted_dev()
6954 if (dinfo->cfg.pcie.pcie_location != 0) { in pci_print_faulted_dev()
6956 dinfo->cfg.pcie.pcie_location + in pci_print_faulted_dev()
6964 dinfo->cfg.pcie.pcie_location + in pci_print_faulted_dev()
7008 dev = dinfo->cfg.dev; in db_clear_pcie_errors()
7009 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in db_clear_pcie_errors()
7011 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in db_clear_pcie_errors()
7031 dev = dinfo->cfg.dev; in DB_COMMAND_FLAGS()
7040 if (dinfo->cfg.pcie.pcie_location != 0) in DB_COMMAND_FLAGS()