Lines Matching +full:irq +full:- +full:status +full:- +full:read +full:- +full:quirk
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
101 static int pci_has_quirk(uint32_t devid, int quirk);
237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
255 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
256 * or the CMIC-SL (AKA ServerWorks GC_LE).
274 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
289 * Note this quirk only affects SB600 revision A13 and earlier.
350 "firmware-assigned ranges fail to allocate during the initial device scan.");
363 "Transition from D3 -> D0 on resume.");
368 "Transition from D0 -> D3 on suspend.");
376 "Enable support for MSI-X interrupts");
381 "Rewrite entire MSI-X table when updating MSI-X entries");
385 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
400 "Ignore firmware-assigned resources for BARs.");
404 "Ignore firmware-assigned bus numbers.");
434 &pci_intx_reroute, 0, "Re-route INTx interrupts when scanning devices");
437 pci_has_quirk(uint32_t devid, int quirk) in pci_has_quirk() argument
441 for (q = &pci_quirks[0]; q->devid; q++) { in pci_has_quirk()
442 if (q->devid == devid && q->type == quirk) in pci_has_quirk()
465 if ((dinfo->cfg.domain == domain) && in pci_find_dbsf()
466 (dinfo->cfg.bus == bus) && in pci_find_dbsf()
467 (dinfo->cfg.slot == slot) && in pci_find_dbsf()
468 (dinfo->cfg.func == func)) { in pci_find_dbsf()
473 return (dinfo != NULL ? dinfo->cfg.dev : NULL); in pci_find_dbsf()
484 if ((dinfo->cfg.vendor == vendor) && in pci_find_device()
485 (dinfo->cfg.device == device)) { in pci_find_device()
486 return (dinfo->cfg.dev); in pci_find_device()
499 if (dinfo->cfg.baseclass == class && in pci_find_class()
500 dinfo->cfg.subclass == subclass) { in pci_find_class()
501 return (dinfo->cfg.dev); in pci_find_class()
516 if (from != dinfo->cfg.dev) in pci_find_class_from()
521 if (dinfo->cfg.baseclass == class && in pci_find_class_from()
522 dinfo->cfg.subclass == subclass) { in pci_find_class_from()
523 return (dinfo->cfg.dev); in pci_find_class_from()
538 if (from != dinfo->cfg.dev) in pci_find_base_class_from()
543 if (dinfo->cfg.baseclass == class) { in pci_find_base_class_from()
544 return (dinfo->cfg.dev); in pci_find_base_class_from()
557 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, in pci_printf()
558 cfg->func); in pci_printf()
666 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) in pci_fixancient()
670 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) in pci_fixancient()
671 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; in pci_fixancient()
680 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_hdrtypedata()
682 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); in pci_hdrtypedata()
683 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); in pci_hdrtypedata()
684 cfg->mingnt = REG(PCIR_MINGNT, 1); in pci_hdrtypedata()
685 cfg->maxlat = REG(PCIR_MAXLAT, 1); in pci_hdrtypedata()
686 cfg->nummaps = PCI_MAXMAPS_0; in pci_hdrtypedata()
689 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); in pci_hdrtypedata()
690 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); in pci_hdrtypedata()
691 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); in pci_hdrtypedata()
692 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); in pci_hdrtypedata()
693 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); in pci_hdrtypedata()
694 cfg->nummaps = PCI_MAXMAPS_1; in pci_hdrtypedata()
697 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); in pci_hdrtypedata()
698 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); in pci_hdrtypedata()
699 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); in pci_hdrtypedata()
700 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); in pci_hdrtypedata()
701 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); in pci_hdrtypedata()
702 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); in pci_hdrtypedata()
703 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); in pci_hdrtypedata()
704 cfg->nummaps = PCI_MAXMAPS_2; in pci_hdrtypedata()
710 /* read configuration header into pcicfgregs structure */
743 cfg = &devlist_entry->cfg; in pci_fill_devinfo()
745 cfg->domain = d; in pci_fill_devinfo()
746 cfg->bus = b; in pci_fill_devinfo()
747 cfg->slot = s; in pci_fill_devinfo()
748 cfg->func = f; in pci_fill_devinfo()
749 cfg->vendor = vid; in pci_fill_devinfo()
750 cfg->device = did; in pci_fill_devinfo()
751 cfg->cmdreg = REG(PCIR_COMMAND, 2); in pci_fill_devinfo()
752 cfg->statreg = REG(PCIR_STATUS, 2); in pci_fill_devinfo()
753 cfg->baseclass = REG(PCIR_CLASS, 1); in pci_fill_devinfo()
754 cfg->subclass = REG(PCIR_SUBCLASS, 1); in pci_fill_devinfo()
755 cfg->progif = REG(PCIR_PROGIF, 1); in pci_fill_devinfo()
756 cfg->revid = REG(PCIR_REVID, 1); in pci_fill_devinfo()
757 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); in pci_fill_devinfo()
758 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); in pci_fill_devinfo()
759 cfg->lattimer = REG(PCIR_LATTIMER, 1); in pci_fill_devinfo()
760 cfg->intpin = REG(PCIR_INTPIN, 1); in pci_fill_devinfo()
761 cfg->intline = REG(PCIR_INTLINE, 1); in pci_fill_devinfo()
763 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; in pci_fill_devinfo()
764 cfg->hdrtype &= ~PCIM_MFDEV; in pci_fill_devinfo()
765 STAILQ_INIT(&cfg->maps); in pci_fill_devinfo()
767 cfg->iov = NULL; in pci_fill_devinfo()
777 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; in pci_fill_devinfo()
778 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; in pci_fill_devinfo()
779 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; in pci_fill_devinfo()
780 devlist_entry->conf.pc_sel.pc_func = cfg->func; in pci_fill_devinfo()
781 devlist_entry->conf.pc_hdr = cfg->hdrtype; in pci_fill_devinfo()
783 devlist_entry->conf.pc_subvendor = cfg->subvendor; in pci_fill_devinfo()
784 devlist_entry->conf.pc_subdevice = cfg->subdevice; in pci_fill_devinfo()
785 devlist_entry->conf.pc_vendor = cfg->vendor; in pci_fill_devinfo()
786 devlist_entry->conf.pc_device = cfg->device; in pci_fill_devinfo()
788 devlist_entry->conf.pc_class = cfg->baseclass; in pci_fill_devinfo()
789 devlist_entry->conf.pc_subclass = cfg->subclass; in pci_fill_devinfo()
790 devlist_entry->conf.pc_progif = cfg->progif; in pci_fill_devinfo()
791 devlist_entry->conf.pc_revid = cfg->revid; in pci_fill_devinfo()
803 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ in pci_ea_fill_info()
804 cfg->ea.ea_location + (n), w) in pci_ea_fill_info()
814 if (cfg->ea.ea_location == 0) in pci_ea_fill_info()
817 STAILQ_INIT(&cfg->ea.ea_entries); in pci_ea_fill_info()
827 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) in pci_ea_fill_info()
832 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; in pci_ea_fill_info()
834 /* Read a number of dwords in the entry */ in pci_ea_fill_info()
844 eae->eae_flags = val; in pci_ea_fill_info()
845 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; in pci_ea_fill_info()
860 eae->eae_base = base; in pci_ea_fill_info()
861 eae->eae_max_offset = max_offset; in pci_ea_fill_info()
863 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); in pci_ea_fill_info()
867 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, in pci_ea_fill_info()
868 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); in pci_ea_fill_info()
877 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) in pci_read_cap()
878 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) in pci_read_cap()
885 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_read_cap()
899 * Read capability entries. in pci_read_cap()
915 cfg->pp.pp_location = ptr; in pci_read_cap()
916 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); in pci_read_cap()
919 /* Determine HT-specific capability type. */ in pci_read_cap()
923 cfg->ht.ht_slave = ptr; in pci_read_cap()
937 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", in pci_read_cap()
938 cfg->domain, cfg->bus, in pci_read_cap()
939 cfg->slot, cfg->func, in pci_read_cap()
944 cfg->ht.ht_msimap = ptr; in pci_read_cap()
945 cfg->ht.ht_msictrl = val; in pci_read_cap()
946 cfg->ht.ht_msiaddr = addr; in pci_read_cap()
952 cfg->msi.msi_location = ptr; in pci_read_cap()
953 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); in pci_read_cap()
955 case PCIY_MSIX: /* PCI MSI-X */ in pci_read_cap()
956 cfg->msix.msix_location = ptr; in pci_read_cap()
957 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); in pci_read_cap()
959 cfg->msix.msix_table_bar = PCIR_BAR(val & in pci_read_cap()
961 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; in pci_read_cap()
963 cfg->msix.msix_pba_bar = PCIR_BAR(val & in pci_read_cap()
965 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; in pci_read_cap()
968 cfg->vpd.vpd_reg = ptr; in pci_read_cap()
972 if ((cfg->hdrtype & PCIM_HDRTYPE) == in pci_read_cap()
975 cfg->subvendor = val & 0xffff; in pci_read_cap()
976 cfg->subdevice = val >> 16; in pci_read_cap()
979 case PCIY_PCIX: /* PCI-X */ in pci_read_cap()
981 * Assume we have a PCI-X chipset if we have in pci_read_cap()
982 * at least one PCI-PCI bridge with a PCI-X in pci_read_cap()
984 * PCI-express or HT chipsets might match on in pci_read_cap()
987 if ((cfg->hdrtype & PCIM_HDRTYPE) == in pci_read_cap()
990 cfg->pcix.pcix_location = ptr; in pci_read_cap()
992 case PCIY_EXPRESS: /* PCI-express */ in pci_read_cap()
994 * Assume we have a PCI-express chipset if we have in pci_read_cap()
995 * at least one PCI-express device. in pci_read_cap()
998 cfg->pcie.pcie_location = ptr; in pci_read_cap()
1000 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; in pci_read_cap()
1003 cfg->ea.ea_location = ptr; in pci_read_cap()
1014 * slaves. PCI-PCI bridges have their windows enabled via in pci_read_cap()
1017 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && in pci_read_cap()
1018 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { in pci_read_cap()
1021 cfg->domain, cfg->bus, cfg->slot, cfg->func); in pci_read_cap()
1022 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; in pci_read_cap()
1023 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, in pci_read_cap()
1043 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); in pci_read_vpd_reg()
1045 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { in pci_read_vpd_reg()
1046 if (--count < 0) in pci_read_vpd_reg()
1050 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); in pci_read_vpd_reg()
1063 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
1064 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
1065 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
1066 if (--count < 0)
1086 /* return 0 and one byte in *data if no read error, -1 else */
1093 if (vrs->bytesinval == 0) { in vpd_nextbyte()
1094 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) in vpd_nextbyte()
1095 return (-1); in vpd_nextbyte()
1096 vrs->val = le32toh(reg); in vpd_nextbyte()
1097 vrs->off += 4; in vpd_nextbyte()
1098 byte = vrs->val & 0xff; in vpd_nextbyte()
1099 vrs->bytesinval = 3; in vpd_nextbyte()
1101 vrs->val = vrs->val >> 8; in vpd_nextbyte()
1102 byte = vrs->val & 0xff; in vpd_nextbyte()
1103 vrs->bytesinval--; in vpd_nextbyte()
1106 vrs->cksum += byte; in vpd_nextbyte()
1111 /* return 0 on match, -1 and "unget" byte on no match */
1118 return (-1); in vpd_expectbyte()
1123 vrs->cksum -= data; in vpd_expectbyte()
1124 vrs->val = (vrs->val << 8) + data; in vpd_expectbyte()
1125 vrs->bytesinval++; in vpd_expectbyte()
1126 return (-1); in vpd_expectbyte()
1129 /* return size if tag matches, -1 on no match, -2 on read error */
1136 return (-1); in vpd_read_tag_size()
1142 return (-2); in vpd_read_tag_size()
1144 return (-2); in vpd_read_tag_size()
1165 /* read VPD keyword and return element size, return -1 on read error */
1172 return (-1); in vpd_read_elem_head()
1174 return (-1); in vpd_read_elem_head()
1176 return (-1); in vpd_read_elem_head()
1181 /* read VPD data element of given size into allocated buffer */
1202 /* read VPD into *keyword and *value, return length of data element */
1210 return (-1); in vpd_read_elem_data()
1226 vrs->cksum -= fixup; in vpd_fixup_cksum()
1229 /* fetch one read-only element and return size of heading + data */
1238 cfg = vrs->cfg; in next_vpd_ro_elem()
1239 vpd = &cfg->vpd; in next_vpd_ro_elem()
1242 return (-1); in next_vpd_ro_elem()
1243 vpd->vpd_ros = alloc_buffer(vpd->vpd_ros, sizeof(*vpd->vpd_ros), vpd->vpd_rocnt); in next_vpd_ro_elem()
1244 vpd_ros = &vpd->vpd_ros[vpd->vpd_rocnt]; in next_vpd_ro_elem()
1245 maxsize -= 3; in next_vpd_ro_elem()
1246 len = vpd_read_elem_data(vrs, vpd_ros->keyword, &vpd_ros->value, maxsize); in next_vpd_ro_elem()
1247 if (vpd_ros->value == NULL) in next_vpd_ro_elem()
1248 return (-1); in next_vpd_ro_elem()
1249 vpd_ros->len = len; in next_vpd_ro_elem()
1250 if (vpd_ros->keyword[0] == 'R' && vpd_ros->keyword[1] == 'V') { in next_vpd_ro_elem()
1251 vpd_fixup_cksum(vrs, vpd_ros->value, len); in next_vpd_ro_elem()
1252 if (vrs->cksum != 0) { in next_vpd_ro_elem()
1254 "invalid VPD checksum %#hhx\n", vrs->cksum); in next_vpd_ro_elem()
1255 return (-1); in next_vpd_ro_elem()
1258 vpd->vpd_rocnt++; in next_vpd_ro_elem()
1272 cfg = vrs->cfg; in next_vpd_rw_elem()
1273 vpd = &cfg->vpd; in next_vpd_rw_elem()
1276 return (-1); in next_vpd_rw_elem()
1277 vpd->vpd_w = alloc_buffer(vpd->vpd_w, sizeof(*vpd->vpd_w), vpd->vpd_wcnt); in next_vpd_rw_elem()
1278 if (vpd->vpd_w == NULL) { in next_vpd_rw_elem()
1280 return (-1); in next_vpd_rw_elem()
1282 vpd_w = &vpd->vpd_w[vpd->vpd_wcnt]; in next_vpd_rw_elem()
1283 maxsize -= 3; in next_vpd_rw_elem()
1284 vpd_w->start = vrs->off + 3 - vrs->bytesinval; in next_vpd_rw_elem()
1285 len = vpd_read_elem_data(vrs, vpd_w->keyword, &vpd_w->value, maxsize); in next_vpd_rw_elem()
1286 if (vpd_w->value == NULL) in next_vpd_rw_elem()
1287 return (-1); in next_vpd_rw_elem()
1288 vpd_w->len = len; in next_vpd_rw_elem()
1289 vpd->vpd_wcnt++; in next_vpd_rw_elem()
1300 free(vpd->vpd_ident, M_DEVBUF); in vpd_free()
1301 for (i = 0; i < vpd->vpd_rocnt; i++) in vpd_free()
1302 free(vpd->vpd_ros[i].value, M_DEVBUF); in vpd_free()
1303 free(vpd->vpd_ros, M_DEVBUF); in vpd_free()
1304 vpd->vpd_rocnt = 0; in vpd_free()
1305 for (i = 0; i < vpd->vpd_wcnt; i++) in vpd_free()
1306 free(vpd->vpd_w[i].value, M_DEVBUF); in vpd_free()
1307 free(vpd->vpd_w, M_DEVBUF); in vpd_free()
1308 vpd->vpd_wcnt = 0; in vpd_free()
1330 /* read VPD ident element - mandatory */ in pci_parse_vpd()
1336 cfg->vpd.vpd_ident = vpd_read_value(&vrs, size); in pci_parse_vpd()
1337 if (cfg->vpd.vpd_ident == NULL) { in pci_parse_vpd()
1342 /* read VPD RO elements - mandatory */ in pci_parse_vpd()
1345 pci_printf(cfg, "no read-only VPD data found\n"); in pci_parse_vpd()
1351 pci_printf(cfg, "error accessing read-only VPD data\n"); in pci_parse_vpd()
1352 return (-1); in pci_parse_vpd()
1354 size -= elem_size; in pci_parse_vpd()
1358 return (-1); in pci_parse_vpd()
1360 /* read VPD RW elements - optional */ in pci_parse_vpd()
1362 if (size == -2) in pci_parse_vpd()
1363 return (-1); in pci_parse_vpd()
1368 return (-1); in pci_parse_vpd()
1370 size -= elem_size; in pci_parse_vpd()
1373 /* read empty END tag - mandatory */ in pci_parse_vpd()
1384 int status; in pci_read_vpd() local
1386 status = pci_parse_vpd(pcib, cfg); in pci_read_vpd()
1387 if (status < 0) in pci_read_vpd()
1388 vpd_free(&cfg->vpd); in pci_read_vpd()
1389 cfg->vpd.vpd_cached = 1; in pci_read_vpd()
1398 pcicfgregs *cfg = &dinfo->cfg; in pci_get_vpd_ident_method()
1400 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_get_vpd_ident_method()
1403 *identptr = cfg->vpd.vpd_ident; in pci_get_vpd_ident_method()
1416 pcicfgregs *cfg = &dinfo->cfg; in pci_get_vpd_readonly_method()
1419 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_get_vpd_readonly_method()
1422 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) in pci_get_vpd_readonly_method()
1423 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, in pci_get_vpd_readonly_method()
1424 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { in pci_get_vpd_readonly_method()
1425 *vptr = cfg->vpd.vpd_ros[i].value; in pci_get_vpd_readonly_method()
1437 pcicfgregs *cfg = &dinfo->cfg; in pci_fetch_vpd_list()
1439 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_fetch_vpd_list()
1441 return (&cfg->vpd); in pci_fetch_vpd_list()
1535 pcicfgregs *cfg = &dinfo->cfg; in pci_find_cap_method()
1536 uint32_t status; in pci_find_cap_method() local
1541 * Check the CAP_LIST bit of the PCI status register first. in pci_find_cap_method()
1543 status = pci_read_config(child, PCIR_STATUS, 2); in pci_find_cap_method()
1544 if (!(status & PCIM_STATUS_CAPPRESENT)) in pci_find_cap_method()
1550 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_find_cap_method()
1569 for (cnt = 0; ptr != 0 && cnt < (PCIE_REGMAX - 0x40) / 2; cnt++) { in pci_find_cap_method()
1618 pcicfgregs *cfg = &dinfo->cfg; in pci_find_extcap_method()
1622 /* Only supported for PCI-express devices. */ in pci_find_extcap_method()
1623 if (cfg->pcie.pcie_location == 0) in pci_find_extcap_method()
1655 pcicfgregs *cfg = &dinfo->cfg; in pci_find_next_extcap_method()
1659 /* Only supported for PCI-express devices. */ in pci_find_next_extcap_method()
1660 if (cfg->pcie.pcie_location == 0) in pci_find_next_extcap_method()
1681 * Support for MSI-X message interrupts.
1687 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_write_msix_entry()
1690 KASSERT(msix->msix_table_len > index, ("bogus index")); in pci_write_msix_entry()
1691 offset = msix->msix_table_offset + index * 16; in pci_write_msix_entry()
1692 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); in pci_write_msix_entry()
1693 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); in pci_write_msix_entry()
1694 bus_write_4(msix->msix_table_res, offset + 8, data); in pci_write_msix_entry()
1704 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_enable_msix_method()
1715 msix->msix_location + PCIR_MSIX_CTRL, in pci_enable_msix_method()
1716 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); in pci_enable_msix_method()
1721 /* Enable MSI -> HT mapping. */ in pci_enable_msix_method()
1729 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_mask_msix()
1732 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); in pci_mask_msix()
1733 offset = msix->msix_table_offset + index * 16 + 12; in pci_mask_msix()
1734 val = bus_read_4(msix->msix_table_res, offset); in pci_mask_msix()
1741 bus_write_4(msix->msix_table_res, offset, val); in pci_mask_msix()
1748 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_unmask_msix()
1751 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); in pci_unmask_msix()
1752 offset = msix->msix_table_offset + index * 16 + 12; in pci_unmask_msix()
1753 val = bus_read_4(msix->msix_table_res, offset); in pci_unmask_msix()
1760 bus_write_4(msix->msix_table_res, offset, val); in pci_unmask_msix()
1767 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_pending_msix()
1770 KASSERT(msix->msix_table_len > index, ("bogus index")); in pci_pending_msix()
1771 offset = msix->msix_pba_offset + (index / 32) * 4; in pci_pending_msix()
1773 return (bus_read_4(msix->msix_pba_res, offset) & bit); in pci_pending_msix()
1777 * Restore MSI-X registers and table during resume. If MSI-X is
1778 * enabled then walk the virtual table to restore the actual MSI-X
1785 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_resume_msix()
1790 if (msix->msix_alloc > 0) { in pci_resume_msix()
1791 msgnum = PCI_MSIX_MSGNUM(msix->msix_ctrl); in pci_resume_msix()
1798 for (i = 0; i < msix->msix_table_len; i++) { in pci_resume_msix()
1799 mte = &msix->msix_table[i]; in pci_resume_msix()
1800 if (mte->mte_vector == 0 || mte->mte_handlers == 0) in pci_resume_msix()
1802 mv = &msix->msix_vectors[mte->mte_vector - 1]; in pci_resume_msix()
1803 pci_write_msix_entry(dev, i, mv->mv_address, in pci_resume_msix()
1804 mv->mv_data); in pci_resume_msix()
1808 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, in pci_resume_msix()
1809 msix->msix_ctrl, 2); in pci_resume_msix()
1813 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1821 pcicfgregs *cfg = &dinfo->cfg; in pci_alloc_msix_method()
1824 int error, irq; in pci_alloc_msix_method() local
1832 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_alloc_msix_method()
1833 if (rle != NULL && rle->res != NULL) in pci_alloc_msix_method()
1837 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) in pci_alloc_msix_method()
1840 /* If MSI-X is blacklisted for this system, fail. */ in pci_alloc_msix_method()
1844 /* MSI-X capability present? */ in pci_alloc_msix_method()
1845 if (cfg->msix.msix_location == 0 || !pci_do_msix) in pci_alloc_msix_method()
1849 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, in pci_alloc_msix_method()
1850 cfg->msix.msix_table_bar); in pci_alloc_msix_method()
1851 if (rle == NULL || rle->res == NULL || in pci_alloc_msix_method()
1852 !(rman_get_flags(rle->res) & RF_ACTIVE)) in pci_alloc_msix_method()
1854 cfg->msix.msix_table_res = rle->res; in pci_alloc_msix_method()
1855 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { in pci_alloc_msix_method()
1856 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, in pci_alloc_msix_method()
1857 cfg->msix.msix_pba_bar); in pci_alloc_msix_method()
1858 if (rle == NULL || rle->res == NULL || in pci_alloc_msix_method()
1859 !(rman_get_flags(rle->res) & RF_ACTIVE)) in pci_alloc_msix_method()
1862 cfg->msix.msix_pba_res = rle->res; in pci_alloc_msix_method()
1864 ctrl = pci_read_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, in pci_alloc_msix_method()
1869 "attempting to allocate %d MSI-X vectors (%d supported)\n", in pci_alloc_msix_method()
1874 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); in pci_alloc_msix_method()
1880 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, in pci_alloc_msix_method()
1881 irq, 1); in pci_alloc_msix_method()
1886 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); in pci_alloc_msix_method()
1888 device_printf(child, "using IRQ %ju for MSI-X\n", in pci_alloc_msix_method()
1889 rle->start); in pci_alloc_msix_method()
1895 * IRQ values as ranges. 'irq' is the previous IRQ. in pci_alloc_msix_method()
1898 device_printf(child, "using IRQs %ju", rle->start); in pci_alloc_msix_method()
1899 irq = rle->start; in pci_alloc_msix_method()
1902 rle = resource_list_find(&dinfo->resources, in pci_alloc_msix_method()
1906 if (rle->start == irq + 1) { in pci_alloc_msix_method()
1908 irq++; in pci_alloc_msix_method()
1914 printf("-%d", irq); in pci_alloc_msix_method()
1919 printf(",%ju", rle->start); in pci_alloc_msix_method()
1920 irq = rle->start; in pci_alloc_msix_method()
1925 printf("-%d", irq); in pci_alloc_msix_method()
1926 printf(" for MSI-X\n"); in pci_alloc_msix_method()
1935 cfg->msix.msix_vectors = mallocarray(actual, sizeof(struct msix_vector), in pci_alloc_msix_method()
1937 cfg->msix.msix_table = mallocarray(actual, in pci_alloc_msix_method()
1940 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_alloc_msix_method()
1941 cfg->msix.msix_vectors[i].mv_irq = rle->start; in pci_alloc_msix_method()
1942 cfg->msix.msix_table[i].mte_vector = i + 1; in pci_alloc_msix_method()
1945 /* Update control register to enable MSI-X. */ in pci_alloc_msix_method()
1947 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, in pci_alloc_msix_method()
1949 cfg->msix.msix_ctrl = ctrl; in pci_alloc_msix_method()
1952 cfg->msix.msix_alloc = actual; in pci_alloc_msix_method()
1953 cfg->msix.msix_table_len = actual; in pci_alloc_msix_method()
1959 * By default, pci_alloc_msix() will assign the allocated IRQ
1960 * resources consecutively to the first N messages in the MSI-X table.
1963 * populate the MSI-X table sparsely. This method allows the driver
1969 * maps directly to the MSI-X table in that index 0 in the array
1970 * specifies the vector for the first message in the MSI-X table, etc.
1975 * vector (IRQ) to be used for the corresponding message.
1977 * On successful return, each message with a non-zero vector will have
1983 * For example, suppose a driver has a MSI-X table with 6 messages and
1987 * have an MSI-X table of ABC--- (where - means no vector assigned).
1989 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1994 * at MSI-X table index X - 1 and will only be valid if a vector is
2002 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_remap_msix_method()
2004 u_int i, irq, j; in pci_remap_msix_method() local
2009 * table can't be bigger than the actual MSI-X table in the in pci_remap_msix_method()
2012 if (count < 1 || count > PCI_MSIX_MSGNUM(msix->msix_ctrl)) in pci_remap_msix_method()
2017 if (vectors[i] > msix->msix_alloc) in pci_remap_msix_method()
2025 used = mallocarray(msix->msix_alloc, sizeof(*used), M_DEVBUF, M_WAITOK | in pci_remap_msix_method()
2029 used[vectors[i] - 1] = true; in pci_remap_msix_method()
2030 for (i = 0; i < msix->msix_alloc - 1; i++) in pci_remap_msix_method()
2041 for (i = 0; i < msix->msix_table_len; i++) { in pci_remap_msix_method()
2042 if (msix->msix_table[i].mte_vector == 0) in pci_remap_msix_method()
2044 if (msix->msix_table[i].mte_handlers > 0) { in pci_remap_msix_method()
2048 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_remap_msix_method()
2050 if (rle->res != NULL) { in pci_remap_msix_method()
2057 for (i = 0; i < msix->msix_table_len; i++) { in pci_remap_msix_method()
2058 if (msix->msix_table[i].mte_vector == 0) in pci_remap_msix_method()
2060 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_remap_msix_method()
2067 free(msix->msix_table, M_DEVBUF); in pci_remap_msix_method()
2068 msix->msix_table = mallocarray(count, sizeof(struct msix_table_entry), in pci_remap_msix_method()
2071 msix->msix_table[i].mte_vector = vectors[i]; in pci_remap_msix_method()
2072 msix->msix_table_len = count; in pci_remap_msix_method()
2075 j = msix->msix_alloc - 1; in pci_remap_msix_method()
2081 msix->msix_vectors[j].mv_irq); in pci_remap_msix_method()
2082 j--; in pci_remap_msix_method()
2086 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * in pci_remap_msix_method()
2088 free(msix->msix_vectors, M_DEVBUF); in pci_remap_msix_method()
2089 msix->msix_vectors = vec; in pci_remap_msix_method()
2090 msix->msix_alloc = j + 1; in pci_remap_msix_method()
2098 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; in pci_remap_msix_method()
2099 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, in pci_remap_msix_method()
2100 irq, 1); in pci_remap_msix_method()
2104 device_printf(child, "Remapped MSI-X IRQs as: "); in pci_remap_msix_method()
2109 printf("---"); in pci_remap_msix_method()
2112 msix->msix_vectors[vectors[i] - 1].mv_irq); in pci_remap_msix_method()
2124 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_release_msix()
2129 if (msix->msix_alloc == 0) in pci_release_msix()
2133 for (i = 0; i < msix->msix_table_len; i++) { in pci_release_msix()
2134 if (msix->msix_table[i].mte_vector == 0) in pci_release_msix()
2136 if (msix->msix_table[i].mte_handlers > 0) in pci_release_msix()
2138 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msix()
2140 if (rle->res != NULL) in pci_release_msix()
2144 /* Update control register to disable MSI-X. */ in pci_release_msix()
2145 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; in pci_release_msix()
2146 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, in pci_release_msix()
2147 msix->msix_ctrl, 2); in pci_release_msix()
2150 for (i = 0; i < msix->msix_table_len; i++) { in pci_release_msix()
2151 if (msix->msix_table[i].mte_vector == 0) in pci_release_msix()
2153 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msix()
2155 free(msix->msix_table, M_DEVBUF); in pci_release_msix()
2156 msix->msix_table_len = 0; in pci_release_msix()
2159 for (i = 0; i < msix->msix_alloc; i++) in pci_release_msix()
2161 msix->msix_vectors[i].mv_irq); in pci_release_msix()
2162 free(msix->msix_vectors, M_DEVBUF); in pci_release_msix()
2163 msix->msix_alloc = 0; in pci_release_msix()
2168 * Return the max supported MSI-X messages this device supports.
2177 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_count_method()
2180 if (pci_do_msix && msix->msix_location != 0) { in pci_msix_count_method()
2181 ctrl = pci_read_config(child, msix->msix_location + in pci_msix_count_method()
2192 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_pba_bar_method()
2194 if (pci_do_msix && msix->msix_location != 0) in pci_msix_pba_bar_method()
2195 return (msix->msix_pba_bar); in pci_msix_pba_bar_method()
2196 return (-1); in pci_msix_pba_bar_method()
2203 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_table_bar_method()
2205 if (pci_do_msix && msix->msix_location != 0) in pci_msix_table_bar_method()
2206 return (msix->msix_table_bar); in pci_msix_table_bar_method()
2207 return (-1); in pci_msix_table_bar_method()
2217 struct pcicfg_ht *ht = &dinfo->cfg.ht; in pci_ht_map_msi()
2219 if (!ht->ht_msimap) in pci_ht_map_msi()
2222 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && in pci_ht_map_msi()
2223 ht->ht_msiaddr >> 20 == addr >> 20) { in pci_ht_map_msi()
2224 /* Enable MSI -> HT mapping. */ in pci_ht_map_msi()
2225 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; in pci_ht_map_msi()
2226 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, in pci_ht_map_msi()
2227 ht->ht_msictrl, 2); in pci_ht_map_msi()
2230 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { in pci_ht_map_msi()
2231 /* Disable MSI -> HT mapping. */ in pci_ht_map_msi()
2232 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; in pci_ht_map_msi()
2233 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, in pci_ht_map_msi()
2234 ht->ht_msictrl, 2); in pci_ht_map_msi()
2245 cap = dinfo->cfg.pcie.pcie_location; in pci_get_relaxed_ordering_enabled()
2260 cap = dinfo->cfg.pcie.pcie_location; in pci_get_max_payload()
2276 cap = dinfo->cfg.pcie.pcie_location; in pci_get_max_read_req()
2292 cap = dinfo->cfg.pcie.pcie_location; in pci_set_max_read_req()
2299 size = (1 << (fls(size) - 1)); in pci_set_max_read_req()
2302 val |= (fls(size) - 8) << 12; in pci_set_max_read_req()
2313 cap = dinfo->cfg.pcie.pcie_location; in pcie_read_config()
2329 cap = dinfo->cfg.pcie.pcie_location; in pcie_write_config()
2336 * Adjusts a PCI-e capability register by clearing the bits in mask
2350 cap = dinfo->cfg.pcie.pcie_location; in pcie_adjust_config()
2372 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_enable_msi_method()
2375 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, in pci_enable_msi_method()
2377 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { in pci_enable_msi_method()
2378 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, in pci_enable_msi_method()
2380 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, in pci_enable_msi_method()
2383 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, in pci_enable_msi_method()
2387 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; in pci_enable_msi_method()
2388 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_enable_msi_method()
2389 msi->msi_ctrl, 2); in pci_enable_msi_method()
2391 /* Enable MSI -> HT mapping. */ in pci_enable_msi_method()
2399 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_disable_msi_method()
2401 /* Disable MSI -> HT mapping. */ in pci_disable_msi_method()
2405 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; in pci_disable_msi_method()
2406 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_disable_msi_method()
2407 msi->msi_ctrl, 2); in pci_disable_msi_method()
2419 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_resume_msi()
2423 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { in pci_resume_msi()
2424 address = msi->msi_addr; in pci_resume_msi()
2425 data = msi->msi_data; in pci_resume_msi()
2426 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, in pci_resume_msi()
2428 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { in pci_resume_msi()
2429 pci_write_config(dev, msi->msi_location + in pci_resume_msi()
2431 pci_write_config(dev, msi->msi_location + in pci_resume_msi()
2434 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, in pci_resume_msi()
2437 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, in pci_resume_msi()
2442 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) in pci_remap_intr_method() argument
2445 pcicfgregs *cfg = &dinfo->cfg; in pci_remap_intr_method()
2455 * Handle MSI first. We try to find this IRQ among our list in pci_remap_intr_method()
2459 if (cfg->msi.msi_alloc > 0) { in pci_remap_intr_method()
2461 if (cfg->msi.msi_handlers == 0) in pci_remap_intr_method()
2463 for (i = 0; i < cfg->msi.msi_alloc; i++) { in pci_remap_intr_method()
2464 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, in pci_remap_intr_method()
2466 if (rle->start == irq) { in pci_remap_intr_method()
2468 dev, irq, &addr, &data); in pci_remap_intr_method()
2472 dinfo->cfg.msi.msi_addr = addr; in pci_remap_intr_method()
2473 dinfo->cfg.msi.msi_data = data; in pci_remap_intr_method()
2482 * For MSI-X, we check to see if we have this IRQ. If we do, in pci_remap_intr_method()
2484 * through all the slots that use this IRQ and update them. in pci_remap_intr_method()
2486 if (cfg->msix.msix_alloc > 0) { in pci_remap_intr_method()
2489 for (i = 0; i < cfg->msix.msix_alloc; i++) { in pci_remap_intr_method()
2490 mv = &cfg->msix.msix_vectors[i]; in pci_remap_intr_method()
2491 if (mv->mv_irq == irq) { in pci_remap_intr_method()
2493 dev, irq, &addr, &data); in pci_remap_intr_method()
2496 mv->mv_address = addr; in pci_remap_intr_method()
2497 mv->mv_data = data; in pci_remap_intr_method()
2498 for (j = 0; j < cfg->msix.msix_table_len; j++) { in pci_remap_intr_method()
2499 mte = &cfg->msix.msix_table[j]; in pci_remap_intr_method()
2500 if (mte->mte_vector != i + 1) in pci_remap_intr_method()
2502 if (mte->mte_handlers == 0) in pci_remap_intr_method()
2534 * host-PCI bridge at device 0:0:0. In the future, it may become
2546 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ in pci_msi_blacklisted()
2568 * Returns true if the specified device is blacklisted because MSI-X
2570 * MSI-X doesn't either.
2586 * Determine if MSI-X is blacklisted globally on this system. If MSI
2587 * is blacklisted, assume that MSI-X is as well. Check for additional
2588 * chipsets where MSI works but MSI-X does not.
2615 pcicfgregs *cfg = &dinfo->cfg; in pci_alloc_msi_method()
2626 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_alloc_msi_method()
2627 if (rle != NULL && rle->res != NULL) in pci_alloc_msi_method()
2631 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) in pci_alloc_msi_method()
2639 if (cfg->msi.msi_location == 0 || !pci_do_msi) in pci_alloc_msi_method()
2642 ctrl = pci_read_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 2); in pci_alloc_msi_method()
2678 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, in pci_alloc_msi_method()
2683 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); in pci_alloc_msi_method()
2689 * of IRQ values as ranges. 'run' is true if in pci_alloc_msi_method()
2696 if (irqs[i] == irqs[i - 1] + 1) { in pci_alloc_msi_method()
2703 printf("-%d", irqs[i - 1]); in pci_alloc_msi_method()
2713 printf("-%d", irqs[actual - 1]); in pci_alloc_msi_method()
2720 ctrl |= (ffs(actual) - 1) << 4; in pci_alloc_msi_method()
2721 cfg->msi.msi_ctrl = ctrl; in pci_alloc_msi_method()
2722 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); in pci_alloc_msi_method()
2725 cfg->msi.msi_alloc = actual; in pci_alloc_msi_method()
2726 cfg->msi.msi_handlers = 0; in pci_alloc_msi_method()
2736 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_release_msi_method()
2741 /* Try MSI-X first. */ in pci_release_msi_method()
2747 if (msi->msi_alloc == 0) in pci_release_msi_method()
2749 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); in pci_release_msi_method()
2752 if (msi->msi_handlers > 0) in pci_release_msi_method()
2754 for (i = 0; i < msi->msi_alloc; i++) { in pci_release_msi_method()
2755 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msi_method()
2757 if (rle->res != NULL) in pci_release_msi_method()
2759 irqs[i] = rle->start; in pci_release_msi_method()
2763 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), in pci_release_msi_method()
2765 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; in pci_release_msi_method()
2766 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_release_msi_method()
2767 msi->msi_ctrl, 2); in pci_release_msi_method()
2770 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); in pci_release_msi_method()
2771 for (i = 0; i < msi->msi_alloc; i++) in pci_release_msi_method()
2772 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msi_method()
2775 msi->msi_alloc = 0; in pci_release_msi_method()
2776 msi->msi_addr = 0; in pci_release_msi_method()
2777 msi->msi_data = 0; in pci_release_msi_method()
2791 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_msi_count_method()
2794 if (pci_do_msi && msi->msi_location != 0) { in pci_msi_count_method()
2795 ctrl = pci_read_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_msi_count_method()
2812 if (dinfo->cfg.vpd.vpd_reg) in pci_freecfg()
2813 vpd_free(&dinfo->cfg.vpd); in pci_freecfg()
2815 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { in pci_freecfg()
2825 pci_numdevs--; in pci_freecfg()
2836 pcicfgregs *cfg = &dinfo->cfg; in pci_set_powerstate_method()
2837 uint16_t status; in pci_set_powerstate_method() local
2840 if (cfg->pp.pp_location == 0) in pci_set_powerstate_method()
2846 * behavior when going from D3 -> D3. in pci_set_powerstate_method()
2871 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + in pci_set_powerstate_method()
2875 status |= PCIM_PSTAT_D0; in pci_set_powerstate_method()
2878 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) in pci_set_powerstate_method()
2880 status |= PCIM_PSTAT_D1; in pci_set_powerstate_method()
2883 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) in pci_set_powerstate_method()
2885 status |= PCIM_PSTAT_D2; in pci_set_powerstate_method()
2888 status |= PCIM_PSTAT_D3; in pci_set_powerstate_method()
2898 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_location + PCIR_POWER_STATUS, in pci_set_powerstate_method()
2899 status, 2); in pci_set_powerstate_method()
2909 pcicfgregs *cfg = &dinfo->cfg; in pci_get_powerstate_method()
2910 uint16_t status; in pci_get_powerstate_method() local
2913 if (cfg->pp.pp_location != 0) { in pci_get_powerstate_method()
2914 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + in pci_get_powerstate_method()
2916 switch (status & PCIM_PSTAT_DMASK) { in pci_get_powerstate_method()
2945 pcicfgregs *cfg = &dinfo->cfg; in pci_clear_pme()
2946 uint16_t status; in pci_clear_pme() local
2948 if (cfg->pp.pp_location != 0) { in pci_clear_pme()
2949 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + in pci_clear_pme()
2951 status &= ~PCIM_PSTAT_PMEENABLE; in pci_clear_pme()
2952 status |= PCIM_PSTAT_PME; in pci_clear_pme()
2953 pci_write_config(dev, dinfo->cfg.pp.pp_location + in pci_clear_pme()
2954 PCIR_POWER_STATUS, status, 2); in pci_clear_pme()
2963 pcicfgregs *cfg = &dinfo->cfg; in pci_enable_pme()
2964 uint16_t status; in pci_enable_pme() local
2966 if (cfg->pp.pp_location != 0) { in pci_enable_pme()
2967 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + in pci_enable_pme()
2969 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; in pci_enable_pme()
2970 pci_write_config(dev, dinfo->cfg.pp.pp_location + in pci_enable_pme()
2971 PCIR_POWER_STATUS, status, 2); in pci_enable_pme()
2979 pcicfgregs *cfg = &dinfo->cfg; in pci_has_pm()
2981 return (cfg->pp.pp_location != 0); in pci_has_pm()
3061 * New style pci driver. Parent device is either a pci-host-bridge or a
3062 * pci-pci-bridge. Both kinds are represented by instances of pcib.
3070 pcicfgregs *cfg = &dinfo->cfg; in pci_print_verbose()
3072 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", in pci_print_verbose()
3073 cfg->vendor, cfg->device, cfg->revid); in pci_print_verbose()
3075 cfg->domain, cfg->bus, cfg->slot, cfg->func); in pci_print_verbose()
3076 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", in pci_print_verbose()
3077 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, in pci_print_verbose()
3078 cfg->mfdev); in pci_print_verbose()
3080 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); in pci_print_verbose()
3082 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, in pci_print_verbose()
3083 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); in pci_print_verbose()
3084 if (cfg->intpin > 0) in pci_print_verbose()
3085 printf("\tintpin=%c, irq=%d\n", in pci_print_verbose()
3086 cfg->intpin +'a' -1, cfg->intline); in pci_print_verbose()
3087 if (cfg->pp.pp_location) { in pci_print_verbose()
3088 uint16_t status; in pci_print_verbose() local
3090 status = pci_read_config(cfg->dev, cfg->pp.pp_location + in pci_print_verbose()
3093 cfg->pp.pp_cap & PCIM_PCAP_SPEC, in pci_print_verbose()
3094 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", in pci_print_verbose()
3095 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", in pci_print_verbose()
3096 status & PCIM_PSTAT_DMASK); in pci_print_verbose()
3098 if (cfg->msi.msi_location) { in pci_print_verbose()
3101 ctrl = cfg->msi.msi_ctrl; in pci_print_verbose()
3108 if (cfg->msix.msix_location) { in pci_print_verbose()
3111 msgnum = PCI_MSIX_MSGNUM(cfg->msix.msix_ctrl); in pci_print_verbose()
3112 printf("\tMSI-X supports %d message%s ", in pci_print_verbose()
3114 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) in pci_print_verbose()
3116 cfg->msix.msix_table_bar); in pci_print_verbose()
3119 cfg->msix.msix_table_bar, in pci_print_verbose()
3120 cfg->msix.msix_pba_bar); in pci_print_verbose()
3147 * The device ROM BAR is special. It is always a 32-bit in pci_read_bar()
3152 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { in pci_read_bar()
3180 * log_2(size) bits of the BAR will stick as 0 when we read in pci_read_bar()
3185 * and combines the result into a 64-bit value." (section 6.2.5.1) in pci_read_bar()
3188 * read back the size value. in pci_read_bar()
3200 * the BAR of the low-level console device and when booting verbose, in pci_read_bar()
3220 /* The device ROM BAR is always a 32-bit memory BAR. */ in pci_write_bar()
3222 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) in pci_write_bar()
3225 ln2range = pci_maprange(pm->pm_value); in pci_write_bar()
3226 pci_write_config(dev, pm->pm_reg, base, 4); in pci_write_bar()
3228 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); in pci_write_bar()
3229 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); in pci_write_bar()
3231 pm->pm_value |= (pci_addr_t)pci_read_config(dev, in pci_write_bar()
3232 pm->pm_reg + 4, 4) << 32; in pci_write_bar()
3242 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { in pci_find_bar()
3243 if (pm->pm_reg == reg) in pci_find_bar()
3255 return (STAILQ_FIRST(&dinfo->cfg.maps)); in pci_first_bar()
3271 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && in pci_bar_enabled()
3272 !(pm->pm_value & PCIM_BIOS_ENABLE)) in pci_bar_enabled()
3275 if ((dinfo->cfg.flags & PCICFG_VF) != 0) { in pci_bar_enabled()
3278 iov = dinfo->cfg.iov; in pci_bar_enabled()
3279 cmd = pci_read_config(iov->iov_pf, in pci_bar_enabled()
3280 iov->iov_pos + PCIR_SRIOV_CTL, 2); in pci_bar_enabled()
3285 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) in pci_bar_enabled()
3299 pm->pm_reg = reg; in pci_add_bar()
3300 pm->pm_value = value; in pci_add_bar()
3301 pm->pm_size = size; in pci_add_bar()
3302 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { in pci_add_bar()
3303 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", in pci_add_bar()
3306 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) in pci_add_bar()
3310 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); in pci_add_bar()
3312 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); in pci_add_bar()
3324 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { in pci_restore_bars()
3325 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) in pci_restore_bars()
3328 ln2range = pci_maprange(pm->pm_value); in pci_restore_bars()
3329 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); in pci_restore_bars()
3331 pci_write_config(dev, pm->pm_reg + 4, in pci_restore_bars()
3332 pm->pm_value >> 32, 4); in pci_restore_bars()
3357 maprange = pci_maprange(pm->pm_value); in pci_add_map()
3413 * read back. These maps have had all f's written to them by the in pci_add_map()
3461 end = base + count - 1; in pci_add_map()
3575 pcicfgregs *cfg = &dinfo->cfg; in pci_assign_interrupt()
3577 int irq; in pci_assign_interrupt() local
3580 if (cfg->intpin == 0) in pci_assign_interrupt()
3583 /* Let the user override the IRQ with a tunable. */ in pci_assign_interrupt()
3584 irq = PCI_INVALID_IRQ; in pci_assign_interrupt()
3586 "hw.pci%d.%d.%d.INT%c.irq", in pci_assign_interrupt()
3587 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); in pci_assign_interrupt()
3588 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) in pci_assign_interrupt()
3589 irq = PCI_INVALID_IRQ; in pci_assign_interrupt()
3592 * If we didn't get an IRQ via the tunable, then we either use the in pci_assign_interrupt()
3593 * IRQ value in the intline register or we ask the bus to route an in pci_assign_interrupt()
3596 * IRQ. in pci_assign_interrupt()
3598 if (!PCI_INTERRUPT_VALID(irq)) { in pci_assign_interrupt()
3599 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) in pci_assign_interrupt()
3600 irq = PCI_ASSIGN_INTERRUPT(bus, dev); in pci_assign_interrupt()
3601 if (!PCI_INTERRUPT_VALID(irq)) in pci_assign_interrupt()
3602 irq = cfg->intline; in pci_assign_interrupt()
3605 /* If after all that we don't have an IRQ, just bail. */ in pci_assign_interrupt()
3606 if (!PCI_INTERRUPT_VALID(irq)) in pci_assign_interrupt()
3610 if (irq != cfg->intline) { in pci_assign_interrupt()
3611 cfg->intline = irq; in pci_assign_interrupt()
3612 pci_write_config(dev, PCIR_INTLINE, irq, 1); in pci_assign_interrupt()
3615 /* Add this IRQ as rid 0 interrupt resource. */ in pci_assign_interrupt()
3616 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); in pci_assign_interrupt()
3756 eec = -1; in xhci_early_takeover()
3807 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_reserve_secbus()
3832 /* Quirk handling. */ in pci_reserve_secbus()
3872 count = end - start + 1; in pci_reserve_secbus()
3914 cfg = &dinfo->cfg; in pci_alloc_secbus()
3915 rl = &dinfo->resources; in pci_alloc_secbus()
3916 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_alloc_secbus()
3963 iov = dinfo->cfg.iov; in pci_ea_bei_to_rid()
3965 iov_pos = iov->iov_pos; in pci_ea_bei_to_rid()
3983 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + in pci_ea_bei_to_rid()
3987 return (-1); in pci_ea_bei_to_rid()
3998 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { in pci_ea_is_enabled()
3999 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) in pci_ea_is_enabled()
4000 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); in pci_ea_is_enabled()
4021 rl = &dinfo->resources; in pci_add_resources_ea()
4025 iov = dinfo->cfg.iov; in pci_add_resources_ea()
4028 if (dinfo->cfg.ea.ea_location == 0) in pci_add_resources_ea()
4031 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { in pci_add_resources_ea()
4033 * TODO: Ignore EA-BAR if is not enabled. in pci_add_resources_ea()
4038 * a legacy-BAR mechanism. in pci_add_resources_ea()
4040 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) in pci_add_resources_ea()
4043 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { in pci_add_resources_ea()
4062 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || in pci_add_resources_ea()
4063 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) in pci_add_resources_ea()
4070 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || in pci_add_resources_ea()
4071 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && in pci_add_resources_ea()
4072 (ea->eae_bei != PCIM_EA_BEI_ROM)) in pci_add_resources_ea()
4076 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); in pci_add_resources_ea()
4085 start = ea->eae_base; in pci_add_resources_ea()
4086 count = ea->eae_max_offset + 1; in pci_add_resources_ea()
4089 count = count * iov->iov_num_vfs; in pci_add_resources_ea()
4091 end = start + count - 1; in pci_add_resources_ea()
4106 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); in pci_add_resources_ea()
4108 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); in pci_add_resources_ea()
4112 * Read flags again to match current status. in pci_add_resources_ea()
4114 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); in pci_add_resources_ea()
4135 cfg = &dinfo->cfg; in pci_add_resources()
4136 rl = &dinfo->resources; in pci_add_resources()
4137 devid = (cfg->device << 16) | cfg->vendor; in pci_add_resources()
4150 for (i = 0; i < cfg->nummaps;) { in pci_add_resources()
4162 for (q = &pci_quirks[0]; q->devid != 0; q++) in pci_add_resources()
4163 if (q->devid == devid && in pci_add_resources()
4164 q->type == PCI_QUIRK_UNMAP_REG && in pci_add_resources()
4165 q->arg1 == PCIR_BAR(i)) in pci_add_resources()
4167 if (q->devid != 0) { in pci_add_resources()
4178 for (q = &pci_quirks[0]; q->devid != 0; q++) in pci_add_resources()
4179 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) in pci_add_resources()
4180 pci_add_map(bus, dev, q->arg1, rl, force, 0); in pci_add_resources()
4182 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline) && in pci_add_resources()
4185 * Try to re-route interrupts. Sometimes the BIOS or in pci_add_resources()
4187 * If the re-route fails, then just stick with what we in pci_add_resources()
4244 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); in pci_add_children()
4383 vf_dinfo->cfg.flags |= PCICFG_VF; in pci_add_iov_child()
4386 return (vf_dinfo->cfg.dev); in pci_add_iov_child()
4408 if (dinfo->cfg.pcie.pcie_location == 0) in pcie_setup_mps()
4444 if (dinfo->cfg.pcie.pcie_location != 0 && in pci_add_child_clear_aer()
4445 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { in pci_add_child_clear_aer()
4446 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4450 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4457 pci_printf(&dinfo->cfg, in pci_add_child_clear_aer()
4458 "clearing AER UC 0x%08x -> 0x%08x\n", in pci_add_child_clear_aer()
4486 pci_printf(&dinfo->cfg, in pci_add_child_clear_aer()
4487 "clearing AER COR 0x%08x -> 0x%08x\n", in pci_add_child_clear_aer()
4503 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4507 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4517 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY); in pci_add_child()
4519 resource_list_init(&dinfo->resources); in pci_add_child()
4527 pci_child_added(dinfo->cfg.dev); in pci_add_child()
4532 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); in pci_add_child()
4562 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, in pci_attach_common()
4564 if (sc->sc_bus == NULL) { in pci_attach_common()
4571 sc->sc_dma_tag = bus_get_dma_tag(dev); in pci_attach_common()
4607 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); in pci_detach()
4690 * as MSI/MSI-X interrupts are never shared. in pci_suspend_child()
4692 rle = resource_list_find(&dinfo->resources, in pci_suspend_child()
4694 if (rle != NULL && rle->res != NULL) in pci_suspend_child()
4695 (void)bus_suspend_intr(child, rle->res); in pci_suspend_child()
4724 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_resume_child()
4725 if (rle != NULL && rle->res != NULL) in pci_resume_child()
4726 (void)bus_resume_intr(child, rle->res); in pci_resume_child()
4812 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); in pci_driver_added()
4821 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, in pci_setup_intr() argument
4832 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, in pci_setup_intr()
4843 rid = rman_get_rid(irq); in pci_setup_intr()
4849 * Check to see if the interrupt is MSI or MSI-X. in pci_setup_intr()
4856 if (dinfo->cfg.msi.msi_alloc > 0) { in pci_setup_intr()
4857 if (dinfo->cfg.msi.msi_addr == 0) { in pci_setup_intr()
4858 KASSERT(dinfo->cfg.msi.msi_handlers == 0, in pci_setup_intr()
4861 child, rman_get_start(irq), &addr, &data); in pci_setup_intr()
4864 dinfo->cfg.msi.msi_addr = addr; in pci_setup_intr()
4865 dinfo->cfg.msi.msi_data = data; in pci_setup_intr()
4867 if (dinfo->cfg.msi.msi_handlers == 0) in pci_setup_intr()
4868 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, in pci_setup_intr()
4869 dinfo->cfg.msi.msi_data); in pci_setup_intr()
4870 dinfo->cfg.msi.msi_handlers++; in pci_setup_intr()
4872 KASSERT(dinfo->cfg.msix.msix_alloc > 0, in pci_setup_intr()
4873 ("No MSI or MSI-X interrupts allocated")); in pci_setup_intr()
4874 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, in pci_setup_intr()
4875 ("MSI-X index too high")); in pci_setup_intr()
4876 mte = &dinfo->cfg.msix.msix_table[rid - 1]; in pci_setup_intr()
4877 KASSERT(mte->mte_vector != 0, ("no message vector")); in pci_setup_intr()
4878 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; in pci_setup_intr()
4879 KASSERT(mv->mv_irq == rman_get_start(irq), in pci_setup_intr()
4880 ("IRQ mismatch")); in pci_setup_intr()
4881 if (mv->mv_address == 0) { in pci_setup_intr()
4882 KASSERT(mte->mte_handlers == 0, in pci_setup_intr()
4883 ("MSI-X table entry has handlers, but vector not mapped")); in pci_setup_intr()
4885 child, rman_get_start(irq), &addr, &data); in pci_setup_intr()
4888 mv->mv_address = addr; in pci_setup_intr()
4889 mv->mv_data = data; in pci_setup_intr()
4897 * table quirk will not work as expected. in pci_setup_intr()
4899 mte->mte_handlers++; in pci_setup_intr()
4900 if (mte->mte_handlers == 1) { in pci_setup_intr()
4901 pci_enable_msix(child, rid - 1, mv->mv_address, in pci_setup_intr()
4902 mv->mv_data); in pci_setup_intr()
4903 pci_unmask_msix(child, rid - 1); in pci_setup_intr()
4908 * Make sure that INTx is disabled if we are using MSI/MSI-X, in pci_setup_intr()
4910 * in which case we "enable" INTx so MSI/MSI-X actually works. in pci_setup_intr()
4919 (void)bus_generic_teardown_intr(dev, child, irq, in pci_setup_intr()
4929 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, in pci_teardown_intr() argument
4937 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) in pci_teardown_intr()
4942 return(bus_generic_teardown_intr(dev, child, irq, cookie)); in pci_teardown_intr()
4944 rid = rman_get_rid(irq); in pci_teardown_intr()
4950 * Check to see if the interrupt is MSI or MSI-X. If so, in pci_teardown_intr()
4952 * MSI-X message, or disable MSI messages if the count in pci_teardown_intr()
4956 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); in pci_teardown_intr()
4957 if (rle->res != irq) in pci_teardown_intr()
4959 if (dinfo->cfg.msi.msi_alloc > 0) { in pci_teardown_intr()
4960 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, in pci_teardown_intr()
4961 ("MSI-X index too high")); in pci_teardown_intr()
4962 if (dinfo->cfg.msi.msi_handlers == 0) in pci_teardown_intr()
4964 dinfo->cfg.msi.msi_handlers--; in pci_teardown_intr()
4965 if (dinfo->cfg.msi.msi_handlers == 0) in pci_teardown_intr()
4968 KASSERT(dinfo->cfg.msix.msix_alloc > 0, in pci_teardown_intr()
4969 ("No MSI or MSI-X interrupts allocated")); in pci_teardown_intr()
4970 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, in pci_teardown_intr()
4971 ("MSI-X index too high")); in pci_teardown_intr()
4972 mte = &dinfo->cfg.msix.msix_table[rid - 1]; in pci_teardown_intr()
4973 if (mte->mte_handlers == 0) in pci_teardown_intr()
4975 mte->mte_handlers--; in pci_teardown_intr()
4976 if (mte->mte_handlers == 0) in pci_teardown_intr()
4977 pci_mask_msix(child, rid - 1); in pci_teardown_intr()
4980 error = bus_generic_teardown_intr(dev, child, irq, cookie); in pci_teardown_intr()
4983 ("%s: generic teardown failed for MSI/MSI-X", __func__)); in pci_teardown_intr()
4995 rl = &dinfo->resources; in pci_print_child()
5001 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); in pci_print_child()
5021 {PCIC_OLD, -1, 1, "old"},
5022 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"},
5023 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"},
5024 {PCIC_STORAGE, -1, 1, "mass storage"},
5034 {PCIC_NETWORK, -1, 1, "network"},
5040 {PCIC_DISPLAY, -1, 1, "display"},
5044 {PCIC_MULTIMEDIA, -1, 1, "multimedia"},
5049 {PCIC_MEMORY, -1, 1, "memory"},
5052 {PCIC_BRIDGE, -1, 1, "bridge"},
5053 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"},
5054 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"},
5055 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"},
5056 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"},
5057 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"},
5058 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"},
5059 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"},
5060 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"},
5061 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"},
5062 {PCIC_SIMPLECOMM, -1, 1, "simple comms"},
5067 {PCIC_BASEPERIPH, -1, 0, "base peripheral"},
5072 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"},
5075 {PCIC_INPUTDEV, -1, 1, "input device"},
5081 {PCIC_DOCKING, -1, 1, "docking station"},
5082 {PCIC_PROCESSOR, -1, 1, "processor"},
5083 {PCIC_SERIALBUS, -1, 1, "serial bus"},
5090 {PCIC_WIRELESS, -1, 1, "wireless controller"},
5094 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"},
5096 {PCIC_SATCOM, -1, 1, "satellite communication"},
5101 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"},
5104 {PCIC_DASP, -1, 0, "dasp"},
5109 {PCIC_INSTRUMENT, -1, 0, "non-essential instrumentation"},
5136 if (pci_nomatch_tab[i].subclass == -1) { in pci_probe_nomatch()
5167 rl = &dinfo->resources; in pci_child_detached()
5175 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); in pci_child_detached()
5176 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { in pci_child_detached()
5177 if (dinfo->cfg.msi.msi_alloc != 0) in pci_child_detached()
5178 pci_printf(&dinfo->cfg, "Device leaked %d MSI " in pci_child_detached()
5179 "vectors\n", dinfo->cfg.msi.msi_alloc); in pci_child_detached()
5181 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " in pci_child_detached()
5182 "vectors\n", dinfo->cfg.msix.msix_alloc); in pci_child_detached()
5186 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); in pci_child_detached()
5188 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); in pci_child_detached()
5190 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); in pci_child_detached()
5208 * - devices cannot be listed without a corresponding VENDOR line.
5217 * is set to -1. Returns nonzero at the end of the database.
5229 *device = -1; in pci_describe_parse_line()
5230 *vendor = -1; in pci_describe_parse_line()
5233 left = pci_vendordata_size - (cp - pci_vendordata); in pci_describe_parse_line()
5251 left--; in pci_describe_parse_line()
5255 left--; in pci_describe_parse_line()
5261 left--; in pci_describe_parse_line()
5302 if (vendor != -1) { in pci_describe_device()
5329 cfg = &dinfo->cfg; in pci_read_ivar()
5340 *result = cfg->subvendor; in pci_read_ivar()
5343 *result = cfg->subdevice; in pci_read_ivar()
5346 *result = cfg->vendor; in pci_read_ivar()
5349 *result = cfg->device; in pci_read_ivar()
5352 *result = (cfg->device << 16) | cfg->vendor; in pci_read_ivar()
5355 *result = cfg->baseclass; in pci_read_ivar()
5358 *result = cfg->subclass; in pci_read_ivar()
5361 *result = cfg->progif; in pci_read_ivar()
5364 *result = cfg->revid; in pci_read_ivar()
5367 *result = cfg->intpin; in pci_read_ivar()
5370 *result = cfg->intline; in pci_read_ivar()
5373 *result = cfg->domain; in pci_read_ivar()
5376 *result = cfg->bus; in pci_read_ivar()
5379 *result = cfg->slot; in pci_read_ivar()
5382 *result = cfg->func; in pci_read_ivar()
5385 *result = cfg->cmdreg; in pci_read_ivar()
5388 *result = cfg->cachelnsz; in pci_read_ivar()
5391 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { in pci_read_ivar()
5392 *result = -1; in pci_read_ivar()
5395 *result = cfg->mingnt; in pci_read_ivar()
5398 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { in pci_read_ivar()
5399 *result = -1; in pci_read_ivar()
5402 *result = cfg->maxlat; in pci_read_ivar()
5405 *result = cfg->lattimer; in pci_read_ivar()
5422 dinfo->cfg.intpin = value; in pci_write_ivar()
5476 if (dinfo->cfg.dev) in DB_SHOW_COMMAND_FLAGS()
5477 name = device_get_name(dinfo->cfg.dev); in DB_SHOW_COMMAND_FLAGS()
5479 p = &dinfo->conf; in DB_SHOW_COMMAND_FLAGS()
5483 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : in DB_SHOW_COMMAND_FLAGS()
5485 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, in DB_SHOW_COMMAND_FLAGS()
5486 p->pc_sel.pc_func, (p->pc_class << 16) | in DB_SHOW_COMMAND_FLAGS()
5487 (p->pc_subclass << 8) | p->pc_progif, in DB_SHOW_COMMAND_FLAGS()
5488 (p->pc_subdevice << 16) | p->pc_subvendor, in DB_SHOW_COMMAND_FLAGS()
5489 (p->pc_device << 16) | p->pc_vendor, in DB_SHOW_COMMAND_FLAGS()
5490 p->pc_revid, p->pc_hdr); in DB_SHOW_COMMAND_FLAGS()
5501 struct resource_list *rl = &dinfo->resources; in pci_reserve_map()
5517 mapsize = pm->pm_size; in pci_reserve_map()
5518 map = pm->pm_value; in pci_reserve_map()
5522 * BAR/map is. BARs that read back 0 here are bogus in pci_reserve_map()
5534 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) in pci_reserve_map()
5543 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { in pci_reserve_map()
5624 rl = &dinfo->resources; in pci_alloc_multi_resource()
5625 cfg = &dinfo->cfg; in pci_alloc_multi_resource()
5635 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || in pci_alloc_multi_resource()
5636 cfg->msix.msix_alloc > 0)) in pci_alloc_multi_resource()
5644 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && in pci_alloc_multi_resource()
5645 (cfg->intpin != 0)) in pci_alloc_multi_resource()
5651 * PCI-PCI bridge I/O window resources are not BARs. in pci_alloc_multi_resource()
5655 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { in pci_alloc_multi_resource()
5695 if (dinfo->cfg.flags & PCICFG_VF) { in pci_alloc_resource()
5724 cfg = &dinfo->cfg; in pci_release_resource()
5727 if (cfg->flags & PCICFG_VF) { in pci_release_resource()
5741 * PCI-PCI bridge I/O window resources are not BARs. For in pci_release_resource()
5744 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && in pci_release_resource()
5755 rl = &dinfo->resources; in pci_release_resource()
5770 if (dinfo->cfg.flags & PCICFG_VF) { in pci_activate_resource()
5793 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) in pci_activate_resource()
5818 if (dinfo->cfg.flags & PCICFG_VF) { in pci_deactivate_resource()
5840 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) in pci_deactivate_resource()
5858 if (dinfo->cfg.flags & PCICFG_VF) { in pci_adjust_resource()
5887 if (dinfo->cfg.flags & PCICFG_VF) { in pci_map_resource()
5915 if (dinfo->cfg.flags & PCICFG_VF) { in pci_unmap_resource()
5939 rl = &dinfo->resources; in pci_child_deleted()
5953 if (rle->res) { in pci_child_deleted()
5954 if (rman_get_flags(rle->res) & RF_ACTIVE || in pci_child_deleted()
5955 resource_list_busy(rl, rle->type, rle->rid)) { in pci_child_deleted()
5956 pci_printf(&dinfo->cfg, in pci_child_deleted()
5959 rle->type, rle->rid, in pci_child_deleted()
5960 rman_get_start(rle->res)); in pci_child_deleted()
5961 bus_release_resource(child, rle->type, rle->rid, in pci_child_deleted()
5962 rle->res); in pci_child_deleted()
5964 resource_list_unreserve(rl, dev, child, rle->type, in pci_child_deleted()
5965 rle->rid); in pci_child_deleted()
5984 rl = &dinfo->resources; in pci_delete_resource()
5989 if (rle->res) { in pci_delete_resource()
5990 if (rman_get_flags(rle->res) & RF_ACTIVE || in pci_delete_resource()
5995 type, rid, rman_get_start(rle->res)); in pci_delete_resource()
6008 return (&dinfo->resources); in pci_get_resource_list()
6025 tag = sc->sc_dma_tag; in pci_get_dma_tag()
6035 return (sc->sc_dma_tag); in pci_get_dma_tag()
6043 pcicfgregs *cfg = &dinfo->cfg; in pci_read_config_method()
6047 * SR-IOV VFs don't implement the VID or DID registers, so we have to in pci_read_config_method()
6050 if (cfg->flags & PCICFG_VF) { in pci_read_config_method()
6054 return (cfg->device << 16 | cfg->vendor); in pci_read_config_method()
6056 return (cfg->vendor); in pci_read_config_method()
6058 return (cfg->vendor & 0xff); in pci_read_config_method()
6064 /* Note that an unaligned 4-byte read is an error. */ in pci_read_config_method()
6066 return (cfg->device); in pci_read_config_method()
6068 return (cfg->device & 0xff); in pci_read_config_method()
6077 cfg->bus, cfg->slot, cfg->func, reg, width)); in pci_read_config_method()
6085 pcicfgregs *cfg = &dinfo->cfg; in pci_write_config_method()
6088 cfg->bus, cfg->slot, cfg->func, reg, val, width); in pci_write_config_method()
6108 cfg = &dinfo->cfg; in pci_child_pnpinfo_method()
6110 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, in pci_child_pnpinfo_method()
6111 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, in pci_child_pnpinfo_method()
6112 cfg->progif); in pci_child_pnpinfo_method()
6138 pcicfgregs *cfg = &dinfo->cfg; in pci_assign_interrupt_method()
6141 cfg->intpin)); in pci_assign_interrupt_method()
6155 * Accept pciconf-style selectors of either pciD:B:S:F or in pci_lookup()
6227 cfg = &dinfo->cfg.pcie; in pci_cfg_restore_pcie()
6228 pos = cfg->pcie_location; in pci_cfg_restore_pcie()
6230 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; in pci_cfg_restore_pcie()
6232 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); in pci_cfg_restore_pcie()
6234 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6235 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || in pci_cfg_restore_pcie()
6236 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) in pci_cfg_restore_pcie()
6237 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); in pci_cfg_restore_pcie()
6239 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6240 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && in pci_cfg_restore_pcie()
6241 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) in pci_cfg_restore_pcie()
6242 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); in pci_cfg_restore_pcie()
6244 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6245 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) in pci_cfg_restore_pcie()
6246 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); in pci_cfg_restore_pcie()
6249 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); in pci_cfg_restore_pcie()
6250 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); in pci_cfg_restore_pcie()
6251 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); in pci_cfg_restore_pcie()
6259 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, in pci_cfg_restore_pcix()
6260 dinfo->cfg.pcix.pcix_command, 2); in pci_cfg_restore_pcix()
6277 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); in pci_cfg_restore()
6278 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); in pci_cfg_restore()
6279 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); in pci_cfg_restore()
6280 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); in pci_cfg_restore()
6281 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); in pci_cfg_restore()
6282 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); in pci_cfg_restore()
6283 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { in pci_cfg_restore()
6285 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); in pci_cfg_restore()
6286 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); in pci_cfg_restore()
6290 dinfo->cfg.bridge.br_seclat, 1); in pci_cfg_restore()
6292 dinfo->cfg.bridge.br_subbus, 1); in pci_cfg_restore()
6294 dinfo->cfg.bridge.br_secbus, 1); in pci_cfg_restore()
6296 dinfo->cfg.bridge.br_pribus, 1); in pci_cfg_restore()
6298 dinfo->cfg.bridge.br_control, 2); in pci_cfg_restore()
6302 dinfo->cfg.bridge.br_seclat, 1); in pci_cfg_restore()
6304 dinfo->cfg.bridge.br_subbus, 1); in pci_cfg_restore()
6306 dinfo->cfg.bridge.br_secbus, 1); in pci_cfg_restore()
6308 dinfo->cfg.bridge.br_pribus, 1); in pci_cfg_restore()
6310 dinfo->cfg.bridge.br_control, 2); in pci_cfg_restore()
6315 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) in pci_cfg_restore()
6316 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); in pci_cfg_restore()
6319 * Restore extended capabilities for PCI-Express and PCI-X in pci_cfg_restore()
6321 if (dinfo->cfg.pcie.pcie_location != 0) in pci_cfg_restore()
6323 if (dinfo->cfg.pcix.pcix_location != 0) in pci_cfg_restore()
6326 /* Restore MSI and MSI-X configurations if they are present. */ in pci_cfg_restore()
6327 if (dinfo->cfg.msi.msi_location != 0) in pci_cfg_restore()
6329 if (dinfo->cfg.msix.msix_location != 0) in pci_cfg_restore()
6333 if (dinfo->cfg.iov != NULL) in pci_cfg_restore()
6345 cfg = &dinfo->cfg.pcie; in pci_cfg_save_pcie()
6346 pos = cfg->pcie_location; in pci_cfg_save_pcie()
6348 cfg->pcie_flags = RREG(PCIER_FLAGS); in pci_cfg_save_pcie()
6350 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; in pci_cfg_save_pcie()
6352 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); in pci_cfg_save_pcie()
6354 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6355 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || in pci_cfg_save_pcie()
6356 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) in pci_cfg_save_pcie()
6357 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); in pci_cfg_save_pcie()
6359 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6360 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && in pci_cfg_save_pcie()
6361 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) in pci_cfg_save_pcie()
6362 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); in pci_cfg_save_pcie()
6364 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6365 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) in pci_cfg_save_pcie()
6366 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); in pci_cfg_save_pcie()
6369 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); in pci_cfg_save_pcie()
6370 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); in pci_cfg_save_pcie()
6371 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); in pci_cfg_save_pcie()
6379 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, in pci_cfg_save_pcix()
6380 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); in pci_cfg_save_pcix()
6396 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); in pci_cfg_save()
6397 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); in pci_cfg_save()
6398 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); in pci_cfg_save()
6399 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); in pci_cfg_save()
6400 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); in pci_cfg_save()
6401 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); in pci_cfg_save()
6402 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); in pci_cfg_save()
6403 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); in pci_cfg_save()
6404 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); in pci_cfg_save()
6405 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); in pci_cfg_save()
6406 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); in pci_cfg_save()
6407 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { in pci_cfg_save()
6409 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); in pci_cfg_save()
6410 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); in pci_cfg_save()
6411 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); in pci_cfg_save()
6412 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); in pci_cfg_save()
6415 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, in pci_cfg_save()
6417 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, in pci_cfg_save()
6419 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, in pci_cfg_save()
6421 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, in pci_cfg_save()
6423 dinfo->cfg.bridge.br_control = pci_read_config(dev, in pci_cfg_save()
6427 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, in pci_cfg_save()
6429 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, in pci_cfg_save()
6431 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, in pci_cfg_save()
6433 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, in pci_cfg_save()
6435 dinfo->cfg.bridge.br_control = pci_read_config(dev, in pci_cfg_save()
6437 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); in pci_cfg_save()
6438 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); in pci_cfg_save()
6442 if (dinfo->cfg.pcie.pcie_location != 0) in pci_cfg_save()
6445 if (dinfo->cfg.pcix.pcix_location != 0) in pci_cfg_save()
6449 if (dinfo->cfg.iov != NULL) in pci_cfg_save()
6528 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); in pci_find_pcie_root_port()
6531 * Walk the bridge hierarchy until we find a PCI-e root in pci_find_pcie_root_port()
6532 * port or a non-PCI device. in pci_find_pcie_root_port()
6545 * PCI-PCI bridge. in pci_find_pcie_root_port()
6551 if (dinfo->cfg.pcie.pcie_location != 0 && in pci_find_pcie_root_port()
6552 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) in pci_find_pcie_root_port()
6560 * Wait for pending transactions to complete on a PCI-express function.
6566 * exceeded. If dev is not a PCI-express function, this returns true.
6575 cap = dinfo->cfg.pcie.pcie_location; in pcie_wait_for_pending_transactions()
6587 max_delay -= 100; in pcie_wait_for_pending_transactions()
6602 * For non-PCI-express functions this returns 0.
6610 cap = dinfo->cfg.pcie.pcie_location; in pcie_get_max_completion_timeout()
6619 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || in pcie_get_max_completion_timeout()
6659 s = "Uncorrectable (Non-Fatal)"; in pcie_apei_error()
6671 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1); in pcie_apei_error()
6695 if (dinfo->cfg.pcie.pcie_location != 0) { in pcie_apei_error()
6696 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pcie_apei_error()
6701 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pcie_apei_error()
6716 * If dev is not a PCI-express function or does not support FLR, this
6721 * PCI-standard registers via pci_save_state() and
6732 cap = dinfo->cfg.pcie.pcie_location; in pcie_flr()
6743 * which will re-enable busmastering. in pcie_flr()
6752 pci_printf(&dinfo->cfg, in pcie_flr()
6757 * Extend the post-FLR delay to cover the maximum in pcie_flr()
6778 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); in pcie_flr()
6783 * Attempt a power-management reset by cycling the device in/out of D3
6883 while (nelt-- > 0) { in pci_match_device()
6885 if (id->match_flag_vendor) in pci_match_device()
6886 match &= vendor == id->vendor; in pci_match_device()
6887 if (id->match_flag_device) in pci_match_device()
6888 match &= device == id->device; in pci_match_device()
6889 if (id->match_flag_subvendor) in pci_match_device()
6890 match &= subvendor == id->subvendor; in pci_match_device()
6891 if (id->match_flag_subdevice) in pci_match_device()
6892 match &= subdevice == id->subdevice; in pci_match_device()
6893 if (id->match_flag_class) in pci_match_device()
6894 match &= class == id->class_id; in pci_match_device()
6895 if (id->match_flag_subclass) in pci_match_device()
6896 match &= subclass == id->subclass; in pci_match_device()
6897 if (id->match_flag_revid) in pci_match_device()
6898 match &= revid == id->revid; in pci_match_device()
6912 dev = dinfo->cfg.dev; in pci_print_faulted_dev_name()
6913 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, in pci_print_faulted_dev_name()
6914 dinfo->cfg.slot, dinfo->cfg.func); in pci_print_faulted_dev_name()
6927 uint16_t status; in pci_print_faulted_dev() local
6930 dev = dinfo->cfg.dev; in pci_print_faulted_dev()
6931 status = pci_read_config(dev, PCIR_STATUS, 2); in pci_print_faulted_dev()
6932 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | in pci_print_faulted_dev()
6935 if (status != 0) { in pci_print_faulted_dev()
6937 printf(" error 0x%04x\n", status); in pci_print_faulted_dev()
6939 if (dinfo->cfg.pcie.pcie_location != 0) { in pci_print_faulted_dev()
6940 status = pci_read_config(dev, in pci_print_faulted_dev()
6941 dinfo->cfg.pcie.pcie_location + in pci_print_faulted_dev()
6943 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | in pci_print_faulted_dev()
6949 dinfo->cfg.pcie.pcie_location + in pci_print_faulted_dev()
6951 status); in pci_print_faulted_dev()
6993 dev = dinfo->cfg.dev; in db_clear_pcie_errors()
6994 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in db_clear_pcie_errors()
6996 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in db_clear_pcie_errors()
7013 uint16_t status, status1; in DB_COMMAND_FLAGS() local
7016 dev = dinfo->cfg.dev; in DB_COMMAND_FLAGS()
7017 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); in DB_COMMAND_FLAGS()
7022 status &= ~status1; in DB_COMMAND_FLAGS()
7023 pci_write_config(dev, PCIR_STATUS, status, 2); in DB_COMMAND_FLAGS()
7025 if (dinfo->cfg.pcie.pcie_location != 0) in DB_COMMAND_FLAGS()