Lines Matching +full:irda +full:- +full:mode +full:- +full:ports

1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
255 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
256 * or the CMIC-SL (AKA ServerWorks GC_LE).
274 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
350 "firmware-assigned ranges fail to allocate during the initial device scan.");
363 "Transition from D3 -> D0 on resume.");
368 "Transition from D0 -> D3 on suspend.");
376 "Enable support for MSI-X interrupts");
381 "Rewrite entire MSI-X table when updating MSI-X entries");
385 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
400 "Ignore firmware-assigned resources for BARs.");
404 "Ignore firmware-assigned bus numbers.");
437 for (q = &pci_quirks[0]; q->devid; q++) { in pci_has_quirk()
438 if (q->devid == devid && q->type == quirk) in pci_has_quirk()
461 if ((dinfo->cfg.domain == domain) && in pci_find_dbsf()
462 (dinfo->cfg.bus == bus) && in pci_find_dbsf()
463 (dinfo->cfg.slot == slot) && in pci_find_dbsf()
464 (dinfo->cfg.func == func)) { in pci_find_dbsf()
469 return (dinfo != NULL ? dinfo->cfg.dev : NULL); in pci_find_dbsf()
480 if ((dinfo->cfg.vendor == vendor) && in pci_find_device()
481 (dinfo->cfg.device == device)) { in pci_find_device()
482 return (dinfo->cfg.dev); in pci_find_device()
495 if (dinfo->cfg.baseclass == class && in pci_find_class()
496 dinfo->cfg.subclass == subclass) { in pci_find_class()
497 return (dinfo->cfg.dev); in pci_find_class()
512 if (from != dinfo->cfg.dev) in pci_find_class_from()
517 if (dinfo->cfg.baseclass == class && in pci_find_class_from()
518 dinfo->cfg.subclass == subclass) { in pci_find_class_from()
519 return (dinfo->cfg.dev); in pci_find_class_from()
534 if (from != dinfo->cfg.dev) in pci_find_base_class_from()
539 if (dinfo->cfg.baseclass == class) { in pci_find_base_class_from()
540 return (dinfo->cfg.dev); in pci_find_base_class_from()
553 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, in pci_printf()
554 cfg->func); in pci_printf()
662 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) in pci_fixancient()
666 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) in pci_fixancient()
667 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; in pci_fixancient()
676 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_hdrtypedata()
678 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); in pci_hdrtypedata()
679 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); in pci_hdrtypedata()
680 cfg->mingnt = REG(PCIR_MINGNT, 1); in pci_hdrtypedata()
681 cfg->maxlat = REG(PCIR_MAXLAT, 1); in pci_hdrtypedata()
682 cfg->nummaps = PCI_MAXMAPS_0; in pci_hdrtypedata()
685 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); in pci_hdrtypedata()
686 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); in pci_hdrtypedata()
687 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); in pci_hdrtypedata()
688 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); in pci_hdrtypedata()
689 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); in pci_hdrtypedata()
690 cfg->nummaps = PCI_MAXMAPS_1; in pci_hdrtypedata()
693 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); in pci_hdrtypedata()
694 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); in pci_hdrtypedata()
695 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); in pci_hdrtypedata()
696 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); in pci_hdrtypedata()
697 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); in pci_hdrtypedata()
698 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); in pci_hdrtypedata()
699 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); in pci_hdrtypedata()
700 cfg->nummaps = PCI_MAXMAPS_2; in pci_hdrtypedata()
739 cfg = &devlist_entry->cfg; in pci_fill_devinfo()
741 cfg->domain = d; in pci_fill_devinfo()
742 cfg->bus = b; in pci_fill_devinfo()
743 cfg->slot = s; in pci_fill_devinfo()
744 cfg->func = f; in pci_fill_devinfo()
745 cfg->vendor = vid; in pci_fill_devinfo()
746 cfg->device = did; in pci_fill_devinfo()
747 cfg->cmdreg = REG(PCIR_COMMAND, 2); in pci_fill_devinfo()
748 cfg->statreg = REG(PCIR_STATUS, 2); in pci_fill_devinfo()
749 cfg->baseclass = REG(PCIR_CLASS, 1); in pci_fill_devinfo()
750 cfg->subclass = REG(PCIR_SUBCLASS, 1); in pci_fill_devinfo()
751 cfg->progif = REG(PCIR_PROGIF, 1); in pci_fill_devinfo()
752 cfg->revid = REG(PCIR_REVID, 1); in pci_fill_devinfo()
753 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); in pci_fill_devinfo()
754 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); in pci_fill_devinfo()
755 cfg->lattimer = REG(PCIR_LATTIMER, 1); in pci_fill_devinfo()
756 cfg->intpin = REG(PCIR_INTPIN, 1); in pci_fill_devinfo()
757 cfg->intline = REG(PCIR_INTLINE, 1); in pci_fill_devinfo()
759 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; in pci_fill_devinfo()
760 cfg->hdrtype &= ~PCIM_MFDEV; in pci_fill_devinfo()
761 STAILQ_INIT(&cfg->maps); in pci_fill_devinfo()
763 cfg->iov = NULL; in pci_fill_devinfo()
773 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; in pci_fill_devinfo()
774 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; in pci_fill_devinfo()
775 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; in pci_fill_devinfo()
776 devlist_entry->conf.pc_sel.pc_func = cfg->func; in pci_fill_devinfo()
777 devlist_entry->conf.pc_hdr = cfg->hdrtype; in pci_fill_devinfo()
779 devlist_entry->conf.pc_subvendor = cfg->subvendor; in pci_fill_devinfo()
780 devlist_entry->conf.pc_subdevice = cfg->subdevice; in pci_fill_devinfo()
781 devlist_entry->conf.pc_vendor = cfg->vendor; in pci_fill_devinfo()
782 devlist_entry->conf.pc_device = cfg->device; in pci_fill_devinfo()
784 devlist_entry->conf.pc_class = cfg->baseclass; in pci_fill_devinfo()
785 devlist_entry->conf.pc_subclass = cfg->subclass; in pci_fill_devinfo()
786 devlist_entry->conf.pc_progif = cfg->progif; in pci_fill_devinfo()
787 devlist_entry->conf.pc_revid = cfg->revid; in pci_fill_devinfo()
799 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ in pci_ea_fill_info()
800 cfg->ea.ea_location + (n), w) in pci_ea_fill_info()
810 if (cfg->ea.ea_location == 0) in pci_ea_fill_info()
813 STAILQ_INIT(&cfg->ea.ea_entries); in pci_ea_fill_info()
823 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) in pci_ea_fill_info()
828 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; in pci_ea_fill_info()
840 eae->eae_flags = val; in pci_ea_fill_info()
841 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; in pci_ea_fill_info()
856 eae->eae_base = base; in pci_ea_fill_info()
857 eae->eae_max_offset = max_offset; in pci_ea_fill_info()
859 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); in pci_ea_fill_info()
863 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, in pci_ea_fill_info()
864 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); in pci_ea_fill_info()
873 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) in pci_read_cap()
874 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) in pci_read_cap()
881 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_read_cap()
911 if (cfg->pp.pp_cap == 0) { in pci_read_cap()
912 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); in pci_read_cap()
913 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; in pci_read_cap()
914 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; in pci_read_cap()
915 if ((nextptr - ptr) > PCIR_POWER_DATA) in pci_read_cap()
916 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; in pci_read_cap()
920 /* Determine HT-specific capability type. */ in pci_read_cap()
924 cfg->ht.ht_slave = ptr; in pci_read_cap()
938 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", in pci_read_cap()
939 cfg->domain, cfg->bus, in pci_read_cap()
940 cfg->slot, cfg->func, in pci_read_cap()
945 cfg->ht.ht_msimap = ptr; in pci_read_cap()
946 cfg->ht.ht_msictrl = val; in pci_read_cap()
947 cfg->ht.ht_msiaddr = addr; in pci_read_cap()
953 cfg->msi.msi_location = ptr; in pci_read_cap()
954 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); in pci_read_cap()
956 case PCIY_MSIX: /* PCI MSI-X */ in pci_read_cap()
957 cfg->msix.msix_location = ptr; in pci_read_cap()
958 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); in pci_read_cap()
960 cfg->msix.msix_table_bar = PCIR_BAR(val & in pci_read_cap()
962 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; in pci_read_cap()
964 cfg->msix.msix_pba_bar = PCIR_BAR(val & in pci_read_cap()
966 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; in pci_read_cap()
969 cfg->vpd.vpd_reg = ptr; in pci_read_cap()
973 if ((cfg->hdrtype & PCIM_HDRTYPE) == in pci_read_cap()
976 cfg->subvendor = val & 0xffff; in pci_read_cap()
977 cfg->subdevice = val >> 16; in pci_read_cap()
980 case PCIY_PCIX: /* PCI-X */ in pci_read_cap()
982 * Assume we have a PCI-X chipset if we have in pci_read_cap()
983 * at least one PCI-PCI bridge with a PCI-X in pci_read_cap()
985 * PCI-express or HT chipsets might match on in pci_read_cap()
988 if ((cfg->hdrtype & PCIM_HDRTYPE) == in pci_read_cap()
991 cfg->pcix.pcix_location = ptr; in pci_read_cap()
993 case PCIY_EXPRESS: /* PCI-express */ in pci_read_cap()
995 * Assume we have a PCI-express chipset if we have in pci_read_cap()
996 * at least one PCI-express device. in pci_read_cap()
999 cfg->pcie.pcie_location = ptr; in pci_read_cap()
1001 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; in pci_read_cap()
1004 cfg->ea.ea_location = ptr; in pci_read_cap()
1015 * slaves. PCI-PCI bridges have their windows enabled via in pci_read_cap()
1018 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && in pci_read_cap()
1019 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { in pci_read_cap()
1022 cfg->domain, cfg->bus, cfg->slot, cfg->func); in pci_read_cap()
1023 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; in pci_read_cap()
1024 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, in pci_read_cap()
1044 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); in pci_read_vpd_reg()
1046 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { in pci_read_vpd_reg()
1047 if (--count < 0) in pci_read_vpd_reg()
1051 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); in pci_read_vpd_reg()
1064 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
1065 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
1066 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
1067 if (--count < 0)
1087 /* return 0 and one byte in *data if no read error, -1 else */
1094 if (vrs->bytesinval == 0) { in vpd_nextbyte()
1095 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, &reg)) in vpd_nextbyte()
1096 return (-1); in vpd_nextbyte()
1097 vrs->val = le32toh(reg); in vpd_nextbyte()
1098 vrs->off += 4; in vpd_nextbyte()
1099 byte = vrs->val & 0xff; in vpd_nextbyte()
1100 vrs->bytesinval = 3; in vpd_nextbyte()
1102 vrs->val = vrs->val >> 8; in vpd_nextbyte()
1103 byte = vrs->val & 0xff; in vpd_nextbyte()
1104 vrs->bytesinval--; in vpd_nextbyte()
1107 vrs->cksum += byte; in vpd_nextbyte()
1112 /* return 0 on match, -1 and "unget" byte on no match */
1119 return (-1); in vpd_expectbyte()
1124 vrs->cksum -= data; in vpd_expectbyte()
1125 vrs->val = (vrs->val << 8) + data; in vpd_expectbyte()
1126 vrs->bytesinval++; in vpd_expectbyte()
1127 return (-1); in vpd_expectbyte()
1130 /* return size if tag matches, -1 on no match, -2 on read error */
1137 return (-1); in vpd_read_tag_size()
1143 return (-2); in vpd_read_tag_size()
1145 return (-2); in vpd_read_tag_size()
1166 /* read VPD keyword and return element size, return -1 on read error */
1173 return (-1); in vpd_read_elem_head()
1175 return (-1); in vpd_read_elem_head()
1177 return (-1); in vpd_read_elem_head()
1211 return (-1); in vpd_read_elem_data()
1227 vrs->cksum -= fixup; in vpd_fixup_cksum()
1230 /* fetch one read-only element and return size of heading + data */
1239 cfg = vrs->cfg; in next_vpd_ro_elem()
1240 vpd = &cfg->vpd; in next_vpd_ro_elem()
1243 return (-1); in next_vpd_ro_elem()
1244 vpd->vpd_ros = alloc_buffer(vpd->vpd_ros, sizeof(*vpd->vpd_ros), vpd->vpd_rocnt); in next_vpd_ro_elem()
1245 vpd_ros = &vpd->vpd_ros[vpd->vpd_rocnt]; in next_vpd_ro_elem()
1246 maxsize -= 3; in next_vpd_ro_elem()
1247 len = vpd_read_elem_data(vrs, vpd_ros->keyword, &vpd_ros->value, maxsize); in next_vpd_ro_elem()
1248 if (vpd_ros->value == NULL) in next_vpd_ro_elem()
1249 return (-1); in next_vpd_ro_elem()
1250 vpd_ros->len = len; in next_vpd_ro_elem()
1251 if (vpd_ros->keyword[0] == 'R' && vpd_ros->keyword[1] == 'V') { in next_vpd_ro_elem()
1252 vpd_fixup_cksum(vrs, vpd_ros->value, len); in next_vpd_ro_elem()
1253 if (vrs->cksum != 0) { in next_vpd_ro_elem()
1255 "invalid VPD checksum %#hhx\n", vrs->cksum); in next_vpd_ro_elem()
1256 return (-1); in next_vpd_ro_elem()
1259 vpd->vpd_rocnt++; in next_vpd_ro_elem()
1273 cfg = vrs->cfg; in next_vpd_rw_elem()
1274 vpd = &cfg->vpd; in next_vpd_rw_elem()
1277 return (-1); in next_vpd_rw_elem()
1278 vpd->vpd_w = alloc_buffer(vpd->vpd_w, sizeof(*vpd->vpd_w), vpd->vpd_wcnt); in next_vpd_rw_elem()
1279 if (vpd->vpd_w == NULL) { in next_vpd_rw_elem()
1281 return (-1); in next_vpd_rw_elem()
1283 vpd_w = &vpd->vpd_w[vpd->vpd_wcnt]; in next_vpd_rw_elem()
1284 maxsize -= 3; in next_vpd_rw_elem()
1285 vpd_w->start = vrs->off + 3 - vrs->bytesinval; in next_vpd_rw_elem()
1286 len = vpd_read_elem_data(vrs, vpd_w->keyword, &vpd_w->value, maxsize); in next_vpd_rw_elem()
1287 if (vpd_w->value == NULL) in next_vpd_rw_elem()
1288 return (-1); in next_vpd_rw_elem()
1289 vpd_w->len = len; in next_vpd_rw_elem()
1290 vpd->vpd_wcnt++; in next_vpd_rw_elem()
1301 free(vpd->vpd_ident, M_DEVBUF); in vpd_free()
1302 for (i = 0; i < vpd->vpd_rocnt; i++) in vpd_free()
1303 free(vpd->vpd_ros[i].value, M_DEVBUF); in vpd_free()
1304 free(vpd->vpd_ros, M_DEVBUF); in vpd_free()
1305 vpd->vpd_rocnt = 0; in vpd_free()
1306 for (i = 0; i < vpd->vpd_wcnt; i++) in vpd_free()
1307 free(vpd->vpd_w[i].value, M_DEVBUF); in vpd_free()
1308 free(vpd->vpd_w, M_DEVBUF); in vpd_free()
1309 vpd->vpd_wcnt = 0; in vpd_free()
1331 /* read VPD ident element - mandatory */ in pci_parse_vpd()
1337 cfg->vpd.vpd_ident = vpd_read_value(&vrs, size); in pci_parse_vpd()
1338 if (cfg->vpd.vpd_ident == NULL) { in pci_parse_vpd()
1343 /* read VPD RO elements - mandatory */ in pci_parse_vpd()
1346 pci_printf(cfg, "no read-only VPD data found\n"); in pci_parse_vpd()
1352 pci_printf(cfg, "error accessing read-only VPD data\n"); in pci_parse_vpd()
1353 return (-1); in pci_parse_vpd()
1355 size -= elem_size; in pci_parse_vpd()
1359 return (-1); in pci_parse_vpd()
1361 /* read VPD RW elements - optional */ in pci_parse_vpd()
1363 if (size == -2) in pci_parse_vpd()
1364 return (-1); in pci_parse_vpd()
1369 return (-1); in pci_parse_vpd()
1371 size -= elem_size; in pci_parse_vpd()
1374 /* read empty END tag - mandatory */ in pci_parse_vpd()
1389 vpd_free(&cfg->vpd); in pci_read_vpd()
1390 cfg->vpd.vpd_cached = 1; in pci_read_vpd()
1399 pcicfgregs *cfg = &dinfo->cfg; in pci_get_vpd_ident_method()
1401 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_get_vpd_ident_method()
1404 *identptr = cfg->vpd.vpd_ident; in pci_get_vpd_ident_method()
1417 pcicfgregs *cfg = &dinfo->cfg; in pci_get_vpd_readonly_method()
1420 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_get_vpd_readonly_method()
1423 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) in pci_get_vpd_readonly_method()
1424 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, in pci_get_vpd_readonly_method()
1425 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { in pci_get_vpd_readonly_method()
1426 *vptr = cfg->vpd.vpd_ros[i].value; in pci_get_vpd_readonly_method()
1438 pcicfgregs *cfg = &dinfo->cfg; in pci_fetch_vpd_list()
1440 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_fetch_vpd_list()
1442 return (&cfg->vpd); in pci_fetch_vpd_list()
1536 pcicfgregs *cfg = &dinfo->cfg; in pci_find_cap_method()
1551 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_find_cap_method()
1570 for (cnt = 0; ptr != 0 && cnt < (PCIE_REGMAX - 0x40) / 2; cnt++) { in pci_find_cap_method()
1619 pcicfgregs *cfg = &dinfo->cfg; in pci_find_extcap_method()
1623 /* Only supported for PCI-express devices. */ in pci_find_extcap_method()
1624 if (cfg->pcie.pcie_location == 0) in pci_find_extcap_method()
1656 pcicfgregs *cfg = &dinfo->cfg; in pci_find_next_extcap_method()
1660 /* Only supported for PCI-express devices. */ in pci_find_next_extcap_method()
1661 if (cfg->pcie.pcie_location == 0) in pci_find_next_extcap_method()
1682 * Support for MSI-X message interrupts.
1688 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_write_msix_entry()
1691 KASSERT(msix->msix_table_len > index, ("bogus index")); in pci_write_msix_entry()
1692 offset = msix->msix_table_offset + index * 16; in pci_write_msix_entry()
1693 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); in pci_write_msix_entry()
1694 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); in pci_write_msix_entry()
1695 bus_write_4(msix->msix_table_res, offset + 8, data); in pci_write_msix_entry()
1705 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_enable_msix_method()
1716 msix->msix_location + PCIR_MSIX_CTRL, in pci_enable_msix_method()
1717 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); in pci_enable_msix_method()
1722 /* Enable MSI -> HT mapping. */ in pci_enable_msix_method()
1730 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_mask_msix()
1733 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); in pci_mask_msix()
1734 offset = msix->msix_table_offset + index * 16 + 12; in pci_mask_msix()
1735 val = bus_read_4(msix->msix_table_res, offset); in pci_mask_msix()
1742 bus_write_4(msix->msix_table_res, offset, val); in pci_mask_msix()
1749 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_unmask_msix()
1752 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); in pci_unmask_msix()
1753 offset = msix->msix_table_offset + index * 16 + 12; in pci_unmask_msix()
1754 val = bus_read_4(msix->msix_table_res, offset); in pci_unmask_msix()
1761 bus_write_4(msix->msix_table_res, offset, val); in pci_unmask_msix()
1768 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_pending_msix()
1771 KASSERT(msix->msix_table_len > index, ("bogus index")); in pci_pending_msix()
1772 offset = msix->msix_pba_offset + (index / 32) * 4; in pci_pending_msix()
1774 return (bus_read_4(msix->msix_pba_res, offset) & bit); in pci_pending_msix()
1778 * Restore MSI-X registers and table during resume. If MSI-X is
1779 * enabled then walk the virtual table to restore the actual MSI-X
1786 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_resume_msix()
1791 if (msix->msix_alloc > 0) { in pci_resume_msix()
1792 msgnum = PCI_MSIX_MSGNUM(msix->msix_ctrl); in pci_resume_msix()
1799 for (i = 0; i < msix->msix_table_len; i++) { in pci_resume_msix()
1800 mte = &msix->msix_table[i]; in pci_resume_msix()
1801 if (mte->mte_vector == 0 || mte->mte_handlers == 0) in pci_resume_msix()
1803 mv = &msix->msix_vectors[mte->mte_vector - 1]; in pci_resume_msix()
1804 pci_write_msix_entry(dev, i, mv->mv_address, in pci_resume_msix()
1805 mv->mv_data); in pci_resume_msix()
1809 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, in pci_resume_msix()
1810 msix->msix_ctrl, 2); in pci_resume_msix()
1814 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1822 pcicfgregs *cfg = &dinfo->cfg; in pci_alloc_msix_method()
1833 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_alloc_msix_method()
1834 if (rle != NULL && rle->res != NULL) in pci_alloc_msix_method()
1838 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) in pci_alloc_msix_method()
1841 /* If MSI-X is blacklisted for this system, fail. */ in pci_alloc_msix_method()
1845 /* MSI-X capability present? */ in pci_alloc_msix_method()
1846 if (cfg->msix.msix_location == 0 || !pci_do_msix) in pci_alloc_msix_method()
1850 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, in pci_alloc_msix_method()
1851 cfg->msix.msix_table_bar); in pci_alloc_msix_method()
1852 if (rle == NULL || rle->res == NULL || in pci_alloc_msix_method()
1853 !(rman_get_flags(rle->res) & RF_ACTIVE)) in pci_alloc_msix_method()
1855 cfg->msix.msix_table_res = rle->res; in pci_alloc_msix_method()
1856 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { in pci_alloc_msix_method()
1857 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, in pci_alloc_msix_method()
1858 cfg->msix.msix_pba_bar); in pci_alloc_msix_method()
1859 if (rle == NULL || rle->res == NULL || in pci_alloc_msix_method()
1860 !(rman_get_flags(rle->res) & RF_ACTIVE)) in pci_alloc_msix_method()
1863 cfg->msix.msix_pba_res = rle->res; in pci_alloc_msix_method()
1865 ctrl = pci_read_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, in pci_alloc_msix_method()
1870 "attempting to allocate %d MSI-X vectors (%d supported)\n", in pci_alloc_msix_method()
1881 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, in pci_alloc_msix_method()
1887 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); in pci_alloc_msix_method()
1889 device_printf(child, "using IRQ %ju for MSI-X\n", in pci_alloc_msix_method()
1890 rle->start); in pci_alloc_msix_method()
1899 device_printf(child, "using IRQs %ju", rle->start); in pci_alloc_msix_method()
1900 irq = rle->start; in pci_alloc_msix_method()
1903 rle = resource_list_find(&dinfo->resources, in pci_alloc_msix_method()
1907 if (rle->start == irq + 1) { in pci_alloc_msix_method()
1915 printf("-%d", irq); in pci_alloc_msix_method()
1920 printf(",%ju", rle->start); in pci_alloc_msix_method()
1921 irq = rle->start; in pci_alloc_msix_method()
1926 printf("-%d", irq); in pci_alloc_msix_method()
1927 printf(" for MSI-X\n"); in pci_alloc_msix_method()
1936 cfg->msix.msix_vectors = mallocarray(actual, sizeof(struct msix_vector), in pci_alloc_msix_method()
1938 cfg->msix.msix_table = mallocarray(actual, in pci_alloc_msix_method()
1941 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_alloc_msix_method()
1942 cfg->msix.msix_vectors[i].mv_irq = rle->start; in pci_alloc_msix_method()
1943 cfg->msix.msix_table[i].mte_vector = i + 1; in pci_alloc_msix_method()
1946 /* Update control register to enable MSI-X. */ in pci_alloc_msix_method()
1948 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, in pci_alloc_msix_method()
1950 cfg->msix.msix_ctrl = ctrl; in pci_alloc_msix_method()
1953 cfg->msix.msix_alloc = actual; in pci_alloc_msix_method()
1954 cfg->msix.msix_table_len = actual; in pci_alloc_msix_method()
1961 * resources consecutively to the first N messages in the MSI-X table.
1964 * populate the MSI-X table sparsely. This method allows the driver
1970 * maps directly to the MSI-X table in that index 0 in the array
1971 * specifies the vector for the first message in the MSI-X table, etc.
1978 * On successful return, each message with a non-zero vector will have
1984 * For example, suppose a driver has a MSI-X table with 6 messages and
1988 * have an MSI-X table of ABC--- (where - means no vector assigned).
1990 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1995 * at MSI-X table index X - 1 and will only be valid if a vector is
2003 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_remap_msix_method()
2010 * table can't be bigger than the actual MSI-X table in the in pci_remap_msix_method()
2013 if (count < 1 || count > PCI_MSIX_MSGNUM(msix->msix_ctrl)) in pci_remap_msix_method()
2018 if (vectors[i] > msix->msix_alloc) in pci_remap_msix_method()
2026 used = mallocarray(msix->msix_alloc, sizeof(*used), M_DEVBUF, M_WAITOK | in pci_remap_msix_method()
2030 used[vectors[i] - 1] = true; in pci_remap_msix_method()
2031 for (i = 0; i < msix->msix_alloc - 1; i++) in pci_remap_msix_method()
2042 for (i = 0; i < msix->msix_table_len; i++) { in pci_remap_msix_method()
2043 if (msix->msix_table[i].mte_vector == 0) in pci_remap_msix_method()
2045 if (msix->msix_table[i].mte_handlers > 0) { in pci_remap_msix_method()
2049 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_remap_msix_method()
2051 if (rle->res != NULL) { in pci_remap_msix_method()
2058 for (i = 0; i < msix->msix_table_len; i++) { in pci_remap_msix_method()
2059 if (msix->msix_table[i].mte_vector == 0) in pci_remap_msix_method()
2061 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_remap_msix_method()
2068 free(msix->msix_table, M_DEVBUF); in pci_remap_msix_method()
2069 msix->msix_table = mallocarray(count, sizeof(struct msix_table_entry), in pci_remap_msix_method()
2072 msix->msix_table[i].mte_vector = vectors[i]; in pci_remap_msix_method()
2073 msix->msix_table_len = count; in pci_remap_msix_method()
2076 j = msix->msix_alloc - 1; in pci_remap_msix_method()
2082 msix->msix_vectors[j].mv_irq); in pci_remap_msix_method()
2083 j--; in pci_remap_msix_method()
2087 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * in pci_remap_msix_method()
2089 free(msix->msix_vectors, M_DEVBUF); in pci_remap_msix_method()
2090 msix->msix_vectors = vec; in pci_remap_msix_method()
2091 msix->msix_alloc = j + 1; in pci_remap_msix_method()
2099 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; in pci_remap_msix_method()
2100 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, in pci_remap_msix_method()
2105 device_printf(child, "Remapped MSI-X IRQs as: "); in pci_remap_msix_method()
2110 printf("---"); in pci_remap_msix_method()
2113 msix->msix_vectors[vectors[i] - 1].mv_irq); in pci_remap_msix_method()
2125 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_release_msix()
2130 if (msix->msix_alloc == 0) in pci_release_msix()
2134 for (i = 0; i < msix->msix_table_len; i++) { in pci_release_msix()
2135 if (msix->msix_table[i].mte_vector == 0) in pci_release_msix()
2137 if (msix->msix_table[i].mte_handlers > 0) in pci_release_msix()
2139 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msix()
2141 if (rle->res != NULL) in pci_release_msix()
2145 /* Update control register to disable MSI-X. */ in pci_release_msix()
2146 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; in pci_release_msix()
2147 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, in pci_release_msix()
2148 msix->msix_ctrl, 2); in pci_release_msix()
2151 for (i = 0; i < msix->msix_table_len; i++) { in pci_release_msix()
2152 if (msix->msix_table[i].mte_vector == 0) in pci_release_msix()
2154 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msix()
2156 free(msix->msix_table, M_DEVBUF); in pci_release_msix()
2157 msix->msix_table_len = 0; in pci_release_msix()
2160 for (i = 0; i < msix->msix_alloc; i++) in pci_release_msix()
2162 msix->msix_vectors[i].mv_irq); in pci_release_msix()
2163 free(msix->msix_vectors, M_DEVBUF); in pci_release_msix()
2164 msix->msix_alloc = 0; in pci_release_msix()
2169 * Return the max supported MSI-X messages this device supports.
2178 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_count_method()
2181 if (pci_do_msix && msix->msix_location != 0) { in pci_msix_count_method()
2182 ctrl = pci_read_config(child, msix->msix_location + in pci_msix_count_method()
2193 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_pba_bar_method()
2195 if (pci_do_msix && msix->msix_location != 0) in pci_msix_pba_bar_method()
2196 return (msix->msix_pba_bar); in pci_msix_pba_bar_method()
2197 return (-1); in pci_msix_pba_bar_method()
2204 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_table_bar_method()
2206 if (pci_do_msix && msix->msix_location != 0) in pci_msix_table_bar_method()
2207 return (msix->msix_table_bar); in pci_msix_table_bar_method()
2208 return (-1); in pci_msix_table_bar_method()
2218 struct pcicfg_ht *ht = &dinfo->cfg.ht; in pci_ht_map_msi()
2220 if (!ht->ht_msimap) in pci_ht_map_msi()
2223 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && in pci_ht_map_msi()
2224 ht->ht_msiaddr >> 20 == addr >> 20) { in pci_ht_map_msi()
2225 /* Enable MSI -> HT mapping. */ in pci_ht_map_msi()
2226 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; in pci_ht_map_msi()
2227 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, in pci_ht_map_msi()
2228 ht->ht_msictrl, 2); in pci_ht_map_msi()
2231 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { in pci_ht_map_msi()
2232 /* Disable MSI -> HT mapping. */ in pci_ht_map_msi()
2233 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; in pci_ht_map_msi()
2234 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, in pci_ht_map_msi()
2235 ht->ht_msictrl, 2); in pci_ht_map_msi()
2246 cap = dinfo->cfg.pcie.pcie_location; in pci_get_relaxed_ordering_enabled()
2261 cap = dinfo->cfg.pcie.pcie_location; in pci_get_max_payload()
2277 cap = dinfo->cfg.pcie.pcie_location; in pci_get_max_read_req()
2293 cap = dinfo->cfg.pcie.pcie_location; in pci_set_max_read_req()
2300 size = (1 << (fls(size) - 1)); in pci_set_max_read_req()
2303 val |= (fls(size) - 8) << 12; in pci_set_max_read_req()
2314 cap = dinfo->cfg.pcie.pcie_location; in pcie_read_config()
2330 cap = dinfo->cfg.pcie.pcie_location; in pcie_write_config()
2337 * Adjusts a PCI-e capability register by clearing the bits in mask
2351 cap = dinfo->cfg.pcie.pcie_location; in pcie_adjust_config()
2373 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_enable_msi_method()
2376 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, in pci_enable_msi_method()
2378 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { in pci_enable_msi_method()
2379 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, in pci_enable_msi_method()
2381 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, in pci_enable_msi_method()
2384 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, in pci_enable_msi_method()
2388 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; in pci_enable_msi_method()
2389 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_enable_msi_method()
2390 msi->msi_ctrl, 2); in pci_enable_msi_method()
2392 /* Enable MSI -> HT mapping. */ in pci_enable_msi_method()
2400 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_disable_msi_method()
2402 /* Disable MSI -> HT mapping. */ in pci_disable_msi_method()
2406 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; in pci_disable_msi_method()
2407 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_disable_msi_method()
2408 msi->msi_ctrl, 2); in pci_disable_msi_method()
2420 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_resume_msi()
2424 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { in pci_resume_msi()
2425 address = msi->msi_addr; in pci_resume_msi()
2426 data = msi->msi_data; in pci_resume_msi()
2427 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, in pci_resume_msi()
2429 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { in pci_resume_msi()
2430 pci_write_config(dev, msi->msi_location + in pci_resume_msi()
2432 pci_write_config(dev, msi->msi_location + in pci_resume_msi()
2435 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, in pci_resume_msi()
2438 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, in pci_resume_msi()
2446 pcicfgregs *cfg = &dinfo->cfg; in pci_remap_intr_method()
2460 if (cfg->msi.msi_alloc > 0) { in pci_remap_intr_method()
2462 if (cfg->msi.msi_handlers == 0) in pci_remap_intr_method()
2464 for (i = 0; i < cfg->msi.msi_alloc; i++) { in pci_remap_intr_method()
2465 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, in pci_remap_intr_method()
2467 if (rle->start == irq) { in pci_remap_intr_method()
2473 dinfo->cfg.msi.msi_addr = addr; in pci_remap_intr_method()
2474 dinfo->cfg.msi.msi_data = data; in pci_remap_intr_method()
2483 * For MSI-X, we check to see if we have this IRQ. If we do, in pci_remap_intr_method()
2487 if (cfg->msix.msix_alloc > 0) { in pci_remap_intr_method()
2490 for (i = 0; i < cfg->msix.msix_alloc; i++) { in pci_remap_intr_method()
2491 mv = &cfg->msix.msix_vectors[i]; in pci_remap_intr_method()
2492 if (mv->mv_irq == irq) { in pci_remap_intr_method()
2497 mv->mv_address = addr; in pci_remap_intr_method()
2498 mv->mv_data = data; in pci_remap_intr_method()
2499 for (j = 0; j < cfg->msix.msix_table_len; j++) { in pci_remap_intr_method()
2500 mte = &cfg->msix.msix_table[j]; in pci_remap_intr_method()
2501 if (mte->mte_vector != i + 1) in pci_remap_intr_method()
2503 if (mte->mte_handlers == 0) in pci_remap_intr_method()
2535 * host-PCI bridge at device 0:0:0. In the future, it may become
2547 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ in pci_msi_blacklisted()
2569 * Returns true if the specified device is blacklisted because MSI-X
2571 * MSI-X doesn't either.
2587 * Determine if MSI-X is blacklisted globally on this system. If MSI
2588 * is blacklisted, assume that MSI-X is as well. Check for additional
2589 * chipsets where MSI works but MSI-X does not.
2616 pcicfgregs *cfg = &dinfo->cfg; in pci_alloc_msi_method()
2627 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_alloc_msi_method()
2628 if (rle != NULL && rle->res != NULL) in pci_alloc_msi_method()
2632 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) in pci_alloc_msi_method()
2640 if (cfg->msi.msi_location == 0 || !pci_do_msi) in pci_alloc_msi_method()
2643 ctrl = pci_read_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 2); in pci_alloc_msi_method()
2679 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, in pci_alloc_msi_method()
2697 if (irqs[i] == irqs[i - 1] + 1) { in pci_alloc_msi_method()
2704 printf("-%d", irqs[i - 1]); in pci_alloc_msi_method()
2714 printf("-%d", irqs[actual - 1]); in pci_alloc_msi_method()
2721 ctrl |= (ffs(actual) - 1) << 4; in pci_alloc_msi_method()
2722 cfg->msi.msi_ctrl = ctrl; in pci_alloc_msi_method()
2723 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); in pci_alloc_msi_method()
2726 cfg->msi.msi_alloc = actual; in pci_alloc_msi_method()
2727 cfg->msi.msi_handlers = 0; in pci_alloc_msi_method()
2737 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_release_msi_method()
2742 /* Try MSI-X first. */ in pci_release_msi_method()
2748 if (msi->msi_alloc == 0) in pci_release_msi_method()
2750 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); in pci_release_msi_method()
2753 if (msi->msi_handlers > 0) in pci_release_msi_method()
2755 for (i = 0; i < msi->msi_alloc; i++) { in pci_release_msi_method()
2756 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msi_method()
2758 if (rle->res != NULL) in pci_release_msi_method()
2760 irqs[i] = rle->start; in pci_release_msi_method()
2764 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), in pci_release_msi_method()
2766 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; in pci_release_msi_method()
2767 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_release_msi_method()
2768 msi->msi_ctrl, 2); in pci_release_msi_method()
2771 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); in pci_release_msi_method()
2772 for (i = 0; i < msi->msi_alloc; i++) in pci_release_msi_method()
2773 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msi_method()
2776 msi->msi_alloc = 0; in pci_release_msi_method()
2777 msi->msi_addr = 0; in pci_release_msi_method()
2778 msi->msi_data = 0; in pci_release_msi_method()
2792 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_msi_count_method()
2795 if (pci_do_msi && msi->msi_location != 0) { in pci_msi_count_method()
2796 ctrl = pci_read_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_msi_count_method()
2813 if (dinfo->cfg.vpd.vpd_reg) in pci_freecfg()
2814 vpd_free(&dinfo->cfg.vpd); in pci_freecfg()
2816 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { in pci_freecfg()
2826 pci_numdevs--; in pci_freecfg()
2837 pcicfgregs *cfg = &dinfo->cfg; in pci_set_powerstate_method()
2841 if (cfg->pp.pp_cap == 0) in pci_set_powerstate_method()
2847 * behavior when going from D3 -> D3. in pci_set_powerstate_method()
2872 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) in pci_set_powerstate_method()
2879 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) in pci_set_powerstate_method()
2884 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) in pci_set_powerstate_method()
2899 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); in pci_set_powerstate_method()
2909 pcicfgregs *cfg = &dinfo->cfg; in pci_get_powerstate_method()
2913 if (cfg->pp.pp_cap != 0) { in pci_get_powerstate_method()
2914 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); in pci_get_powerstate_method()
3016 * New style pci driver. Parent device is either a pci-host-bridge or a
3017 * pci-pci-bridge. Both kinds are represented by instances of pcib.
3025 pcicfgregs *cfg = &dinfo->cfg; in pci_print_verbose()
3027 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", in pci_print_verbose()
3028 cfg->vendor, cfg->device, cfg->revid); in pci_print_verbose()
3030 cfg->domain, cfg->bus, cfg->slot, cfg->func); in pci_print_verbose()
3031 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", in pci_print_verbose()
3032 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, in pci_print_verbose()
3033 cfg->mfdev); in pci_print_verbose()
3035 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); in pci_print_verbose()
3037 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, in pci_print_verbose()
3038 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); in pci_print_verbose()
3039 if (cfg->intpin > 0) in pci_print_verbose()
3041 cfg->intpin +'a' -1, cfg->intline); in pci_print_verbose()
3042 if (cfg->pp.pp_cap) { in pci_print_verbose()
3045 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); in pci_print_verbose()
3047 cfg->pp.pp_cap & PCIM_PCAP_SPEC, in pci_print_verbose()
3048 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", in pci_print_verbose()
3049 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", in pci_print_verbose()
3052 if (cfg->msi.msi_location) { in pci_print_verbose()
3055 ctrl = cfg->msi.msi_ctrl; in pci_print_verbose()
3062 if (cfg->msix.msix_location) { in pci_print_verbose()
3065 msgnum = PCI_MSIX_MSGNUM(cfg->msix.msix_ctrl); in pci_print_verbose()
3066 printf("\tMSI-X supports %d message%s ", in pci_print_verbose()
3068 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) in pci_print_verbose()
3070 cfg->msix.msix_table_bar); in pci_print_verbose()
3073 cfg->msix.msix_table_bar, in pci_print_verbose()
3074 cfg->msix.msix_pba_bar); in pci_print_verbose()
3101 * The device ROM BAR is special. It is always a 32-bit in pci_read_bar()
3106 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { in pci_read_bar()
3139 * and combines the result into a 64-bit value." (section 6.2.5.1) in pci_read_bar()
3154 * the BAR of the low-level console device and when booting verbose, in pci_read_bar()
3174 /* The device ROM BAR is always a 32-bit memory BAR. */ in pci_write_bar()
3176 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) in pci_write_bar()
3179 ln2range = pci_maprange(pm->pm_value); in pci_write_bar()
3180 pci_write_config(dev, pm->pm_reg, base, 4); in pci_write_bar()
3182 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); in pci_write_bar()
3183 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); in pci_write_bar()
3185 pm->pm_value |= (pci_addr_t)pci_read_config(dev, in pci_write_bar()
3186 pm->pm_reg + 4, 4) << 32; in pci_write_bar()
3196 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { in pci_find_bar()
3197 if (pm->pm_reg == reg) in pci_find_bar()
3209 return (STAILQ_FIRST(&dinfo->cfg.maps)); in pci_first_bar()
3225 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && in pci_bar_enabled()
3226 !(pm->pm_value & PCIM_BIOS_ENABLE)) in pci_bar_enabled()
3229 if ((dinfo->cfg.flags & PCICFG_VF) != 0) { in pci_bar_enabled()
3232 iov = dinfo->cfg.iov; in pci_bar_enabled()
3233 cmd = pci_read_config(iov->iov_pf, in pci_bar_enabled()
3234 iov->iov_pos + PCIR_SRIOV_CTL, 2); in pci_bar_enabled()
3239 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) in pci_bar_enabled()
3253 pm->pm_reg = reg; in pci_add_bar()
3254 pm->pm_value = value; in pci_add_bar()
3255 pm->pm_size = size; in pci_add_bar()
3256 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { in pci_add_bar()
3257 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", in pci_add_bar()
3260 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) in pci_add_bar()
3264 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); in pci_add_bar()
3266 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); in pci_add_bar()
3278 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { in pci_restore_bars()
3279 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) in pci_restore_bars()
3282 ln2range = pci_maprange(pm->pm_value); in pci_restore_bars()
3283 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); in pci_restore_bars()
3285 pci_write_config(dev, pm->pm_reg + 4, in pci_restore_bars()
3286 pm->pm_value >> 32, 4); in pci_restore_bars()
3311 maprange = pci_maprange(pm->pm_value); in pci_add_map()
3415 end = base + count - 1; in pci_add_map()
3465 * For ATA devices we need to decide early what addressing mode to use.
3466 * Legacy demands that the primary and secondary ATA ports sits on the
3469 * addressing mode.
3482 printf("Trying ATA native PCI addressing mode\n"); in pci_ata_maps()
3529 pcicfgregs *cfg = &dinfo->cfg; in pci_assign_interrupt()
3534 if (cfg->intpin == 0) in pci_assign_interrupt()
3541 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); in pci_assign_interrupt()
3553 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) in pci_assign_interrupt()
3556 irq = cfg->intline; in pci_assign_interrupt()
3564 if (irq != cfg->intline) { in pci_assign_interrupt()
3565 cfg->intline = irq; in pci_assign_interrupt()
3570 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); in pci_assign_interrupt()
3621 * to the ports of the root hub? in uhci_early_takeover()
3710 eec = -1; in xhci_early_takeover()
3761 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_reserve_secbus()
3826 count = end - start + 1; in pci_reserve_secbus()
3868 cfg = &dinfo->cfg; in pci_alloc_secbus()
3869 rl = &dinfo->resources; in pci_alloc_secbus()
3870 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_alloc_secbus()
3917 iov = dinfo->cfg.iov; in pci_ea_bei_to_rid()
3919 iov_pos = iov->iov_pos; in pci_ea_bei_to_rid()
3937 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + in pci_ea_bei_to_rid()
3941 return (-1); in pci_ea_bei_to_rid()
3952 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { in pci_ea_is_enabled()
3953 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) in pci_ea_is_enabled()
3954 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); in pci_ea_is_enabled()
3975 rl = &dinfo->resources; in pci_add_resources_ea()
3979 iov = dinfo->cfg.iov; in pci_add_resources_ea()
3982 if (dinfo->cfg.ea.ea_location == 0) in pci_add_resources_ea()
3985 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { in pci_add_resources_ea()
3987 * TODO: Ignore EA-BAR if is not enabled. in pci_add_resources_ea()
3992 * a legacy-BAR mechanism. in pci_add_resources_ea()
3994 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) in pci_add_resources_ea()
3997 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { in pci_add_resources_ea()
4016 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || in pci_add_resources_ea()
4017 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) in pci_add_resources_ea()
4024 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || in pci_add_resources_ea()
4025 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && in pci_add_resources_ea()
4026 (ea->eae_bei != PCIM_EA_BEI_ROM)) in pci_add_resources_ea()
4030 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); in pci_add_resources_ea()
4039 start = ea->eae_base; in pci_add_resources_ea()
4040 count = ea->eae_max_offset + 1; in pci_add_resources_ea()
4043 count = count * iov->iov_num_vfs; in pci_add_resources_ea()
4045 end = start + count - 1; in pci_add_resources_ea()
4060 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); in pci_add_resources_ea()
4062 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); in pci_add_resources_ea()
4068 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); in pci_add_resources_ea()
4089 cfg = &dinfo->cfg; in pci_add_resources()
4090 rl = &dinfo->resources; in pci_add_resources()
4091 devid = (cfg->device << 16) | cfg->vendor; in pci_add_resources()
4104 for (i = 0; i < cfg->nummaps;) { in pci_add_resources()
4116 for (q = &pci_quirks[0]; q->devid != 0; q++) in pci_add_resources()
4117 if (q->devid == devid && in pci_add_resources()
4118 q->type == PCI_QUIRK_UNMAP_REG && in pci_add_resources()
4119 q->arg1 == PCIR_BAR(i)) in pci_add_resources()
4121 if (q->devid != 0) { in pci_add_resources()
4132 for (q = &pci_quirks[0]; q->devid != 0; q++) in pci_add_resources()
4133 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) in pci_add_resources()
4134 pci_add_map(bus, dev, q->arg1, rl, force, 0); in pci_add_resources()
4136 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { in pci_add_resources()
4138 * Try to re-route interrupts. Sometimes the BIOS or in pci_add_resources()
4140 * If the re-route fails, then just stick with what we in pci_add_resources()
4197 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); in pci_add_children()
4336 vf_dinfo->cfg.flags |= PCICFG_VF; in pci_add_iov_child()
4339 return (vf_dinfo->cfg.dev); in pci_add_iov_child()
4361 if (dinfo->cfg.pcie.pcie_location == 0) in pcie_setup_mps()
4397 if (dinfo->cfg.pcie.pcie_location != 0 && in pci_add_child_clear_aer()
4398 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { in pci_add_child_clear_aer()
4399 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4403 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4410 pci_printf(&dinfo->cfg, in pci_add_child_clear_aer()
4411 "clearing AER UC 0x%08x -> 0x%08x\n", in pci_add_child_clear_aer()
4439 pci_printf(&dinfo->cfg, in pci_add_child_clear_aer()
4440 "clearing AER COR 0x%08x -> 0x%08x\n", in pci_add_child_clear_aer()
4456 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4460 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4470 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY); in pci_add_child()
4472 resource_list_init(&dinfo->resources); in pci_add_child()
4479 pci_child_added(dinfo->cfg.dev); in pci_add_child()
4484 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); in pci_add_child()
4514 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, in pci_attach_common()
4516 if (sc->sc_bus == NULL) { in pci_attach_common()
4523 sc->sc_dma_tag = bus_get_dma_tag(dev); in pci_attach_common()
4559 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); in pci_detach()
4642 * as MSI/MSI-X interrupts are never shared. in pci_suspend_child()
4644 rle = resource_list_find(&dinfo->resources, in pci_suspend_child()
4646 if (rle != NULL && rle->res != NULL) in pci_suspend_child()
4647 (void)bus_suspend_intr(child, rle->res); in pci_suspend_child()
4675 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_resume_child()
4676 if (rle != NULL && rle->res != NULL) in pci_resume_child()
4677 (void)bus_resume_intr(child, rle->res); in pci_resume_child()
4763 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); in pci_driver_added()
4800 * Check to see if the interrupt is MSI or MSI-X. in pci_setup_intr()
4807 if (dinfo->cfg.msi.msi_alloc > 0) { in pci_setup_intr()
4808 if (dinfo->cfg.msi.msi_addr == 0) { in pci_setup_intr()
4809 KASSERT(dinfo->cfg.msi.msi_handlers == 0, in pci_setup_intr()
4815 dinfo->cfg.msi.msi_addr = addr; in pci_setup_intr()
4816 dinfo->cfg.msi.msi_data = data; in pci_setup_intr()
4818 if (dinfo->cfg.msi.msi_handlers == 0) in pci_setup_intr()
4819 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, in pci_setup_intr()
4820 dinfo->cfg.msi.msi_data); in pci_setup_intr()
4821 dinfo->cfg.msi.msi_handlers++; in pci_setup_intr()
4823 KASSERT(dinfo->cfg.msix.msix_alloc > 0, in pci_setup_intr()
4824 ("No MSI or MSI-X interrupts allocated")); in pci_setup_intr()
4825 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, in pci_setup_intr()
4826 ("MSI-X index too high")); in pci_setup_intr()
4827 mte = &dinfo->cfg.msix.msix_table[rid - 1]; in pci_setup_intr()
4828 KASSERT(mte->mte_vector != 0, ("no message vector")); in pci_setup_intr()
4829 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; in pci_setup_intr()
4830 KASSERT(mv->mv_irq == rman_get_start(irq), in pci_setup_intr()
4832 if (mv->mv_address == 0) { in pci_setup_intr()
4833 KASSERT(mte->mte_handlers == 0, in pci_setup_intr()
4834 ("MSI-X table entry has handlers, but vector not mapped")); in pci_setup_intr()
4839 mv->mv_address = addr; in pci_setup_intr()
4840 mv->mv_data = data; in pci_setup_intr()
4850 mte->mte_handlers++; in pci_setup_intr()
4851 if (mte->mte_handlers == 1) { in pci_setup_intr()
4852 pci_enable_msix(child, rid - 1, mv->mv_address, in pci_setup_intr()
4853 mv->mv_data); in pci_setup_intr()
4854 pci_unmask_msix(child, rid - 1); in pci_setup_intr()
4859 * Make sure that INTx is disabled if we are using MSI/MSI-X, in pci_setup_intr()
4861 * in which case we "enable" INTx so MSI/MSI-X actually works. in pci_setup_intr()
4901 * Check to see if the interrupt is MSI or MSI-X. If so, in pci_teardown_intr()
4903 * MSI-X message, or disable MSI messages if the count in pci_teardown_intr()
4907 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); in pci_teardown_intr()
4908 if (rle->res != irq) in pci_teardown_intr()
4910 if (dinfo->cfg.msi.msi_alloc > 0) { in pci_teardown_intr()
4911 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, in pci_teardown_intr()
4912 ("MSI-X index too high")); in pci_teardown_intr()
4913 if (dinfo->cfg.msi.msi_handlers == 0) in pci_teardown_intr()
4915 dinfo->cfg.msi.msi_handlers--; in pci_teardown_intr()
4916 if (dinfo->cfg.msi.msi_handlers == 0) in pci_teardown_intr()
4919 KASSERT(dinfo->cfg.msix.msix_alloc > 0, in pci_teardown_intr()
4920 ("No MSI or MSI-X interrupts allocated")); in pci_teardown_intr()
4921 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, in pci_teardown_intr()
4922 ("MSI-X index too high")); in pci_teardown_intr()
4923 mte = &dinfo->cfg.msix.msix_table[rid - 1]; in pci_teardown_intr()
4924 if (mte->mte_handlers == 0) in pci_teardown_intr()
4926 mte->mte_handlers--; in pci_teardown_intr()
4927 if (mte->mte_handlers == 0) in pci_teardown_intr()
4928 pci_mask_msix(child, rid - 1); in pci_teardown_intr()
4934 ("%s: generic teardown failed for MSI/MSI-X", __func__)); in pci_teardown_intr()
4946 rl = &dinfo->resources; in pci_print_child()
4972 {PCIC_OLD, -1, 1, "old"},
4973 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"},
4974 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"},
4975 {PCIC_STORAGE, -1, 1, "mass storage"},
4985 {PCIC_NETWORK, -1, 1, "network"},
4991 {PCIC_DISPLAY, -1, 1, "display"},
4995 {PCIC_MULTIMEDIA, -1, 1, "multimedia"},
5000 {PCIC_MEMORY, -1, 1, "memory"},
5003 {PCIC_BRIDGE, -1, 1, "bridge"},
5004 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"},
5005 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"},
5006 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"},
5007 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"},
5008 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"},
5009 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"},
5010 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"},
5011 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"},
5012 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"},
5013 {PCIC_SIMPLECOMM, -1, 1, "simple comms"},
5018 {PCIC_BASEPERIPH, -1, 0, "base peripheral"},
5023 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"},
5026 {PCIC_INPUTDEV, -1, 1, "input device"},
5032 {PCIC_DOCKING, -1, 1, "docking station"},
5033 {PCIC_PROCESSOR, -1, 1, "processor"},
5034 {PCIC_SERIALBUS, -1, 1, "serial bus"},
5041 {PCIC_WIRELESS, -1, 1, "wireless controller"},
5042 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"},
5045 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"},
5047 {PCIC_SATCOM, -1, 1, "satellite communication"},
5052 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"},
5055 {PCIC_DASP, -1, 0, "dasp"},
5060 {PCIC_INSTRUMENT, -1, 0, "non-essential instrumentation"},
5087 if (pci_nomatch_tab[i].subclass == -1) { in pci_probe_nomatch()
5118 rl = &dinfo->resources; in pci_child_detached()
5126 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); in pci_child_detached()
5127 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { in pci_child_detached()
5128 if (dinfo->cfg.msi.msi_alloc != 0) in pci_child_detached()
5129 pci_printf(&dinfo->cfg, "Device leaked %d MSI " in pci_child_detached()
5130 "vectors\n", dinfo->cfg.msi.msi_alloc); in pci_child_detached()
5132 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " in pci_child_detached()
5133 "vectors\n", dinfo->cfg.msix.msix_alloc); in pci_child_detached()
5137 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); in pci_child_detached()
5139 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); in pci_child_detached()
5141 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); in pci_child_detached()
5159 * - devices cannot be listed without a corresponding VENDOR line.
5168 * is set to -1. Returns nonzero at the end of the database.
5180 *device = -1; in pci_describe_parse_line()
5181 *vendor = -1; in pci_describe_parse_line()
5184 left = pci_vendordata_size - (cp - pci_vendordata); in pci_describe_parse_line()
5202 left--; in pci_describe_parse_line()
5206 left--; in pci_describe_parse_line()
5212 left--; in pci_describe_parse_line()
5253 if (vendor != -1) { in pci_describe_device()
5280 cfg = &dinfo->cfg; in pci_read_ivar()
5291 *result = cfg->subvendor; in pci_read_ivar()
5294 *result = cfg->subdevice; in pci_read_ivar()
5297 *result = cfg->vendor; in pci_read_ivar()
5300 *result = cfg->device; in pci_read_ivar()
5303 *result = (cfg->device << 16) | cfg->vendor; in pci_read_ivar()
5306 *result = cfg->baseclass; in pci_read_ivar()
5309 *result = cfg->subclass; in pci_read_ivar()
5312 *result = cfg->progif; in pci_read_ivar()
5315 *result = cfg->revid; in pci_read_ivar()
5318 *result = cfg->intpin; in pci_read_ivar()
5321 *result = cfg->intline; in pci_read_ivar()
5324 *result = cfg->domain; in pci_read_ivar()
5327 *result = cfg->bus; in pci_read_ivar()
5330 *result = cfg->slot; in pci_read_ivar()
5333 *result = cfg->func; in pci_read_ivar()
5336 *result = cfg->cmdreg; in pci_read_ivar()
5339 *result = cfg->cachelnsz; in pci_read_ivar()
5342 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { in pci_read_ivar()
5343 *result = -1; in pci_read_ivar()
5346 *result = cfg->mingnt; in pci_read_ivar()
5349 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { in pci_read_ivar()
5350 *result = -1; in pci_read_ivar()
5353 *result = cfg->maxlat; in pci_read_ivar()
5356 *result = cfg->lattimer; in pci_read_ivar()
5373 dinfo->cfg.intpin = value; in pci_write_ivar()
5427 if (dinfo->cfg.dev) in DB_SHOW_COMMAND_FLAGS()
5428 name = device_get_name(dinfo->cfg.dev); in DB_SHOW_COMMAND_FLAGS()
5430 p = &dinfo->conf; in DB_SHOW_COMMAND_FLAGS()
5434 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : in DB_SHOW_COMMAND_FLAGS()
5436 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, in DB_SHOW_COMMAND_FLAGS()
5437 p->pc_sel.pc_func, (p->pc_class << 16) | in DB_SHOW_COMMAND_FLAGS()
5438 (p->pc_subclass << 8) | p->pc_progif, in DB_SHOW_COMMAND_FLAGS()
5439 (p->pc_subdevice << 16) | p->pc_subvendor, in DB_SHOW_COMMAND_FLAGS()
5440 (p->pc_device << 16) | p->pc_vendor, in DB_SHOW_COMMAND_FLAGS()
5441 p->pc_revid, p->pc_hdr); in DB_SHOW_COMMAND_FLAGS()
5452 struct resource_list *rl = &dinfo->resources; in pci_reserve_map()
5468 mapsize = pm->pm_size; in pci_reserve_map()
5469 map = pm->pm_value; in pci_reserve_map()
5474 * and unimplemented. Note: atapci in legacy mode are in pci_reserve_map()
5476 * have a atapci device in legacy mode and it fails in pci_reserve_map()
5485 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) in pci_reserve_map()
5494 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { in pci_reserve_map()
5575 rl = &dinfo->resources; in pci_alloc_multi_resource()
5576 cfg = &dinfo->cfg; in pci_alloc_multi_resource()
5586 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || in pci_alloc_multi_resource()
5587 cfg->msix.msix_alloc > 0)) in pci_alloc_multi_resource()
5595 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && in pci_alloc_multi_resource()
5596 (cfg->intpin != 0)) in pci_alloc_multi_resource()
5602 * PCI-PCI bridge I/O window resources are not BARs. in pci_alloc_multi_resource()
5606 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { in pci_alloc_multi_resource()
5646 if (dinfo->cfg.flags & PCICFG_VF) { in pci_alloc_resource()
5675 cfg = &dinfo->cfg; in pci_release_resource()
5678 if (cfg->flags & PCICFG_VF) { in pci_release_resource()
5692 * PCI-PCI bridge I/O window resources are not BARs. For in pci_release_resource()
5695 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && in pci_release_resource()
5706 rl = &dinfo->resources; in pci_release_resource()
5721 if (dinfo->cfg.flags & PCICFG_VF) { in pci_activate_resource()
5744 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) in pci_activate_resource()
5769 if (dinfo->cfg.flags & PCICFG_VF) { in pci_deactivate_resource()
5791 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) in pci_deactivate_resource()
5809 if (dinfo->cfg.flags & PCICFG_VF) { in pci_adjust_resource()
5838 if (dinfo->cfg.flags & PCICFG_VF) { in pci_map_resource()
5866 if (dinfo->cfg.flags & PCICFG_VF) { in pci_unmap_resource()
5890 rl = &dinfo->resources; in pci_child_deleted()
5904 if (rle->res) { in pci_child_deleted()
5905 if (rman_get_flags(rle->res) & RF_ACTIVE || in pci_child_deleted()
5906 resource_list_busy(rl, rle->type, rle->rid)) { in pci_child_deleted()
5907 pci_printf(&dinfo->cfg, in pci_child_deleted()
5910 rle->type, rle->rid, in pci_child_deleted()
5911 rman_get_start(rle->res)); in pci_child_deleted()
5912 bus_release_resource(child, rle->type, rle->rid, in pci_child_deleted()
5913 rle->res); in pci_child_deleted()
5915 resource_list_unreserve(rl, dev, child, rle->type, in pci_child_deleted()
5916 rle->rid); in pci_child_deleted()
5935 rl = &dinfo->resources; in pci_delete_resource()
5940 if (rle->res) { in pci_delete_resource()
5941 if (rman_get_flags(rle->res) & RF_ACTIVE || in pci_delete_resource()
5946 type, rid, rman_get_start(rle->res)); in pci_delete_resource()
5959 return (&dinfo->resources); in pci_get_resource_list()
5976 tag = sc->sc_dma_tag; in pci_get_dma_tag()
5986 return (sc->sc_dma_tag); in pci_get_dma_tag()
5994 pcicfgregs *cfg = &dinfo->cfg; in pci_read_config_method()
5998 * SR-IOV VFs don't implement the VID or DID registers, so we have to in pci_read_config_method()
6001 if (cfg->flags & PCICFG_VF) { in pci_read_config_method()
6005 return (cfg->device << 16 | cfg->vendor); in pci_read_config_method()
6007 return (cfg->vendor); in pci_read_config_method()
6009 return (cfg->vendor & 0xff); in pci_read_config_method()
6015 /* Note that an unaligned 4-byte read is an error. */ in pci_read_config_method()
6017 return (cfg->device); in pci_read_config_method()
6019 return (cfg->device & 0xff); in pci_read_config_method()
6028 cfg->bus, cfg->slot, cfg->func, reg, width)); in pci_read_config_method()
6036 pcicfgregs *cfg = &dinfo->cfg; in pci_write_config_method()
6039 cfg->bus, cfg->slot, cfg->func, reg, val, width); in pci_write_config_method()
6059 cfg = &dinfo->cfg; in pci_child_pnpinfo_method()
6061 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, in pci_child_pnpinfo_method()
6062 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, in pci_child_pnpinfo_method()
6063 cfg->progif); in pci_child_pnpinfo_method()
6089 pcicfgregs *cfg = &dinfo->cfg; in pci_assign_interrupt_method()
6092 cfg->intpin)); in pci_assign_interrupt_method()
6106 * Accept pciconf-style selectors of either pciD:B:S:F or in pci_lookup()
6178 cfg = &dinfo->cfg.pcie; in pci_cfg_restore_pcie()
6179 pos = cfg->pcie_location; in pci_cfg_restore_pcie()
6181 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; in pci_cfg_restore_pcie()
6183 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); in pci_cfg_restore_pcie()
6185 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6186 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || in pci_cfg_restore_pcie()
6187 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) in pci_cfg_restore_pcie()
6188 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); in pci_cfg_restore_pcie()
6190 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6191 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && in pci_cfg_restore_pcie()
6192 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) in pci_cfg_restore_pcie()
6193 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); in pci_cfg_restore_pcie()
6195 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6196 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) in pci_cfg_restore_pcie()
6197 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); in pci_cfg_restore_pcie()
6200 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); in pci_cfg_restore_pcie()
6201 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); in pci_cfg_restore_pcie()
6202 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); in pci_cfg_restore_pcie()
6210 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, in pci_cfg_restore_pcix()
6211 dinfo->cfg.pcix.pcix_command, 2); in pci_cfg_restore_pcix()
6219 * Restore the device to full power mode. We must do this in pci_cfg_restore()
6228 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); in pci_cfg_restore()
6229 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); in pci_cfg_restore()
6230 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); in pci_cfg_restore()
6231 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); in pci_cfg_restore()
6232 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); in pci_cfg_restore()
6233 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); in pci_cfg_restore()
6234 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { in pci_cfg_restore()
6236 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); in pci_cfg_restore()
6237 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); in pci_cfg_restore()
6241 dinfo->cfg.bridge.br_seclat, 1); in pci_cfg_restore()
6243 dinfo->cfg.bridge.br_subbus, 1); in pci_cfg_restore()
6245 dinfo->cfg.bridge.br_secbus, 1); in pci_cfg_restore()
6247 dinfo->cfg.bridge.br_pribus, 1); in pci_cfg_restore()
6249 dinfo->cfg.bridge.br_control, 2); in pci_cfg_restore()
6253 dinfo->cfg.bridge.br_seclat, 1); in pci_cfg_restore()
6255 dinfo->cfg.bridge.br_subbus, 1); in pci_cfg_restore()
6257 dinfo->cfg.bridge.br_secbus, 1); in pci_cfg_restore()
6259 dinfo->cfg.bridge.br_pribus, 1); in pci_cfg_restore()
6261 dinfo->cfg.bridge.br_control, 2); in pci_cfg_restore()
6266 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) in pci_cfg_restore()
6267 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); in pci_cfg_restore()
6270 * Restore extended capabilities for PCI-Express and PCI-X in pci_cfg_restore()
6272 if (dinfo->cfg.pcie.pcie_location != 0) in pci_cfg_restore()
6274 if (dinfo->cfg.pcix.pcix_location != 0) in pci_cfg_restore()
6277 /* Restore MSI and MSI-X configurations if they are present. */ in pci_cfg_restore()
6278 if (dinfo->cfg.msi.msi_location != 0) in pci_cfg_restore()
6280 if (dinfo->cfg.msix.msix_location != 0) in pci_cfg_restore()
6284 if (dinfo->cfg.iov != NULL) in pci_cfg_restore()
6296 cfg = &dinfo->cfg.pcie; in pci_cfg_save_pcie()
6297 pos = cfg->pcie_location; in pci_cfg_save_pcie()
6299 cfg->pcie_flags = RREG(PCIER_FLAGS); in pci_cfg_save_pcie()
6301 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; in pci_cfg_save_pcie()
6303 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); in pci_cfg_save_pcie()
6305 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6306 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || in pci_cfg_save_pcie()
6307 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) in pci_cfg_save_pcie()
6308 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); in pci_cfg_save_pcie()
6310 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6311 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && in pci_cfg_save_pcie()
6312 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) in pci_cfg_save_pcie()
6313 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); in pci_cfg_save_pcie()
6315 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6316 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) in pci_cfg_save_pcie()
6317 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); in pci_cfg_save_pcie()
6320 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); in pci_cfg_save_pcie()
6321 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); in pci_cfg_save_pcie()
6322 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); in pci_cfg_save_pcie()
6330 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, in pci_cfg_save_pcix()
6331 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); in pci_cfg_save_pcix()
6347 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); in pci_cfg_save()
6348 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); in pci_cfg_save()
6349 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); in pci_cfg_save()
6350 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); in pci_cfg_save()
6351 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); in pci_cfg_save()
6352 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); in pci_cfg_save()
6353 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); in pci_cfg_save()
6354 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); in pci_cfg_save()
6355 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); in pci_cfg_save()
6356 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); in pci_cfg_save()
6357 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); in pci_cfg_save()
6358 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { in pci_cfg_save()
6360 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); in pci_cfg_save()
6361 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); in pci_cfg_save()
6362 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); in pci_cfg_save()
6363 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); in pci_cfg_save()
6366 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, in pci_cfg_save()
6368 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, in pci_cfg_save()
6370 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, in pci_cfg_save()
6372 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, in pci_cfg_save()
6374 dinfo->cfg.bridge.br_control = pci_read_config(dev, in pci_cfg_save()
6378 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, in pci_cfg_save()
6380 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, in pci_cfg_save()
6382 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, in pci_cfg_save()
6384 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, in pci_cfg_save()
6386 dinfo->cfg.bridge.br_control = pci_read_config(dev, in pci_cfg_save()
6388 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); in pci_cfg_save()
6389 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); in pci_cfg_save()
6393 if (dinfo->cfg.pcie.pcie_location != 0) in pci_cfg_save()
6396 if (dinfo->cfg.pcix.pcix_location != 0) in pci_cfg_save()
6400 if (dinfo->cfg.iov != NULL) in pci_cfg_save()
6479 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); in pci_find_pcie_root_port()
6482 * Walk the bridge hierarchy until we find a PCI-e root in pci_find_pcie_root_port()
6483 * port or a non-PCI device. in pci_find_pcie_root_port()
6496 * PCI-PCI bridge. in pci_find_pcie_root_port()
6502 if (dinfo->cfg.pcie.pcie_location != 0 && in pci_find_pcie_root_port()
6503 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) in pci_find_pcie_root_port()
6511 * Wait for pending transactions to complete on a PCI-express function.
6517 * exceeded. If dev is not a PCI-express function, this returns true.
6526 cap = dinfo->cfg.pcie.pcie_location; in pcie_wait_for_pending_transactions()
6538 max_delay -= 100; in pcie_wait_for_pending_transactions()
6553 * For non-PCI-express functions this returns 0.
6561 cap = dinfo->cfg.pcie.pcie_location; in pcie_get_max_completion_timeout()
6570 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || in pcie_get_max_completion_timeout()
6610 s = "Uncorrectable (Non-Fatal)"; in pcie_apei_error()
6646 if (dinfo->cfg.pcie.pcie_location != 0) { in pcie_apei_error()
6647 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pcie_apei_error()
6652 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pcie_apei_error()
6667 * If dev is not a PCI-express function or does not support FLR, this
6672 * PCI-standard registers via pci_save_state() and
6683 cap = dinfo->cfg.pcie.pcie_location; in pcie_flr()
6694 * which will re-enable busmastering. in pcie_flr()
6703 pci_printf(&dinfo->cfg, in pcie_flr()
6708 * Extend the post-FLR delay to cover the maximum in pcie_flr()
6729 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); in pcie_flr()
6734 * Attempt a power-management reset by cycling the device in/out of D3
6834 while (nelt-- > 0) { in pci_match_device()
6836 if (id->match_flag_vendor) in pci_match_device()
6837 match &= vendor == id->vendor; in pci_match_device()
6838 if (id->match_flag_device) in pci_match_device()
6839 match &= device == id->device; in pci_match_device()
6840 if (id->match_flag_subvendor) in pci_match_device()
6841 match &= subvendor == id->subvendor; in pci_match_device()
6842 if (id->match_flag_subdevice) in pci_match_device()
6843 match &= subdevice == id->subdevice; in pci_match_device()
6844 if (id->match_flag_class) in pci_match_device()
6845 match &= class == id->class_id; in pci_match_device()
6846 if (id->match_flag_subclass) in pci_match_device()
6847 match &= subclass == id->subclass; in pci_match_device()
6848 if (id->match_flag_revid) in pci_match_device()
6849 match &= revid == id->revid; in pci_match_device()
6863 dev = dinfo->cfg.dev; in pci_print_faulted_dev_name()
6864 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, in pci_print_faulted_dev_name()
6865 dinfo->cfg.slot, dinfo->cfg.func); in pci_print_faulted_dev_name()
6881 dev = dinfo->cfg.dev; in pci_print_faulted_dev()
6890 if (dinfo->cfg.pcie.pcie_location != 0) { in pci_print_faulted_dev()
6892 dinfo->cfg.pcie.pcie_location + in pci_print_faulted_dev()
6900 dinfo->cfg.pcie.pcie_location + in pci_print_faulted_dev()
6944 dev = dinfo->cfg.dev; in db_clear_pcie_errors()
6945 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in db_clear_pcie_errors()
6947 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in db_clear_pcie_errors()
6967 dev = dinfo->cfg.dev; in DB_COMMAND_FLAGS()
6976 if (dinfo->cfg.pcie.pcie_location != 0) in DB_COMMAND_FLAGS()