Lines Matching +full:func +full:- +full:uart +full:- +full:b
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
121 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
138 int b, int s, int f, uint16_t vid, uint16_t did);
237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
243 #define PCI_QUIRK_DISABLE_FLR 8 /* Function-Level Reset (FLR) not working. */
256 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
257 * or the CMIC-SL (AKA ServerWorks GC_LE).
275 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
358 "firmware-assigned ranges fail to allocate during the initial device scan.");
371 "Transition from D3 -> D0 on resume.");
376 "Transition from D0 -> D3 on suspend.");
384 "Enable support for MSI-X interrupts");
389 "Rewrite entire MSI-X table when updating MSI-X entries");
393 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
408 "Ignore firmware-assigned resources for BARs.");
412 "Ignore firmware-assigned bus numbers.");
442 &pci_intx_reroute, 0, "Re-route INTx interrupts when scanning devices");
449 for (q = &pci_quirks[0]; q->devid; q++) {
450 if (q->devid == devid && q->type == quirk)
459 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
462 return (pci_find_dbsf(0, bus, slot, func));
468 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
473 if ((dinfo->cfg.domain == domain) &&
474 (dinfo->cfg.bus == bus) &&
475 (dinfo->cfg.slot == slot) &&
476 (dinfo->cfg.func == func)) {
481 return (dinfo != NULL ? dinfo->cfg.dev : NULL);
492 if ((dinfo->cfg.vendor == vendor) &&
493 (dinfo->cfg.device == device)) {
494 return (dinfo->cfg.dev);
507 if (dinfo->cfg.baseclass == class &&
508 dinfo->cfg.subclass == subclass) {
509 return (dinfo->cfg.dev);
524 if (from != dinfo->cfg.dev)
529 if (dinfo->cfg.baseclass == class &&
530 dinfo->cfg.subclass == subclass) {
531 return (dinfo->cfg.dev);
546 if (from != dinfo->cfg.dev)
551 if (dinfo->cfg.baseclass == class) {
552 return (dinfo->cfg.dev);
565 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
566 cfg->func);
674 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
678 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
679 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
685 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
687 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
688 switch (cfg->hdrtype & PCIM_HDRTYPE) {
690 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
691 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
692 cfg->mingnt = REG(PCIR_MINGNT, 1);
693 cfg->maxlat = REG(PCIR_MAXLAT, 1);
694 cfg->nummaps = PCI_MAXMAPS_0;
697 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1);
698 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1);
699 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1);
700 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1);
701 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2);
702 cfg->nummaps = PCI_MAXMAPS_1;
705 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1);
706 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1);
707 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1);
708 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1);
709 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2);
710 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
711 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
712 cfg->nummaps = PCI_MAXMAPS_2;
720 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f)
722 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
731 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did));
743 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f,
751 cfg = &devlist_entry->cfg;
753 cfg->domain = d;
754 cfg->bus = b;
755 cfg->slot = s;
756 cfg->func = f;
757 cfg->vendor = vid;
758 cfg->device = did;
759 cfg->cmdreg = REG(PCIR_COMMAND, 2);
760 cfg->statreg = REG(PCIR_STATUS, 2);
761 cfg->baseclass = REG(PCIR_CLASS, 1);
762 cfg->subclass = REG(PCIR_SUBCLASS, 1);
763 cfg->progif = REG(PCIR_PROGIF, 1);
764 cfg->revid = REG(PCIR_REVID, 1);
765 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
766 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
767 cfg->lattimer = REG(PCIR_LATTIMER, 1);
768 cfg->intpin = REG(PCIR_INTPIN, 1);
769 cfg->intline = REG(PCIR_INTLINE, 1);
771 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
772 cfg->hdrtype &= ~PCIM_MFDEV;
773 STAILQ_INIT(&cfg->maps);
775 cfg->iov = NULL;
778 pci_hdrtypedata(pcib, b, s, f, cfg);
785 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
786 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
787 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
788 devlist_entry->conf.pc_sel.pc_func = cfg->func;
789 devlist_entry->conf.pc_hdr = cfg->hdrtype;
791 devlist_entry->conf.pc_subvendor = cfg->subvendor;
792 devlist_entry->conf.pc_subdevice = cfg->subdevice;
793 devlist_entry->conf.pc_vendor = cfg->vendor;
794 devlist_entry->conf.pc_device = cfg->device;
796 devlist_entry->conf.pc_class = cfg->baseclass;
797 devlist_entry->conf.pc_subclass = cfg->subclass;
798 devlist_entry->conf.pc_progif = cfg->progif;
799 devlist_entry->conf.pc_revid = cfg->revid;
811 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \
812 cfg->ea.ea_location + (n), w)
815 int a, b;
822 if (cfg->ea.ea_location == 0)
825 STAILQ_INIT(&cfg->ea.ea_entries);
835 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE)
840 eae->eae_cfg_offset = cfg->ea.ea_location + ptr;
847 for (b = 0; b < ent_size; b++) {
848 dw[b] = REG(ptr, 4);
852 eae->eae_flags = val;
853 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET;
857 b = 2;
858 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) {
859 base |= (uint64_t)dw[b] << 32UL;
860 b++;
863 && (b < ent_size)) {
864 max_offset |= (uint64_t)dw[b] << 32UL;
865 b++;
868 eae->eae_base = base;
869 eae->eae_max_offset = max_offset;
871 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link);
875 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags,
876 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset);
885 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
886 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
893 switch (cfg->hdrtype & PCIM_HDRTYPE) {
923 cfg->pp.pp_location = ptr;
924 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
927 /* Determine HT-specific capability type. */
931 cfg->ht.ht_slave = ptr;
945 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
946 cfg->domain, cfg->bus,
947 cfg->slot, cfg->func,
952 cfg->ht.ht_msimap = ptr;
953 cfg->ht.ht_msictrl = val;
954 cfg->ht.ht_msiaddr = addr;
960 cfg->msi.msi_location = ptr;
961 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
963 case PCIY_MSIX: /* PCI MSI-X */
964 cfg->msix.msix_location = ptr;
965 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
967 cfg->msix.msix_table_bar = PCIR_BAR(val &
969 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
971 cfg->msix.msix_pba_bar = PCIR_BAR(val &
973 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
976 cfg->vpd.vpd_reg = ptr;
980 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
983 cfg->subvendor = val & 0xffff;
984 cfg->subdevice = val >> 16;
987 case PCIY_PCIX: /* PCI-X */
989 * Assume we have a PCI-X chipset if we have
990 * at least one PCI-PCI bridge with a PCI-X
992 * PCI-express or HT chipsets might match on
995 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
998 cfg->pcix.pcix_location = ptr;
1000 case PCIY_EXPRESS: /* PCI-express */
1002 * Assume we have a PCI-express chipset if we have
1003 * at least one PCI-express device.
1006 cfg->pcie.pcie_location = ptr;
1008 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE;
1011 cfg->ea.ea_location = ptr;
1022 * slaves. PCI-PCI bridges have their windows enabled via
1025 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
1026 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
1029 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1030 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1031 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
1051 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
1053 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
1054 if (--count < 0)
1058 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
1071 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
1072 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
1073 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
1074 if (--count < 0)
1094 /* return 0 and one byte in *data if no read error, -1 else */
1101 if (vrs->bytesinval == 0) {
1102 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
1103 return (-1);
1104 vrs->val = le32toh(reg);
1105 vrs->off += 4;
1106 byte = vrs->val & 0xff;
1107 vrs->bytesinval = 3;
1109 vrs->val = vrs->val >> 8;
1110 byte = vrs->val & 0xff;
1111 vrs->bytesinval--;
1114 vrs->cksum += byte;
1119 /* return 0 on match, -1 and "unget" byte on no match */
1126 return (-1);
1131 vrs->cksum -= data;
1132 vrs->val = (vrs->val << 8) + data;
1133 vrs->bytesinval++;
1134 return (-1);
1137 /* return size if tag matches, -1 on no match, -2 on read error */
1144 return (-1);
1150 return (-2);
1152 return (-2);
1173 /* read VPD keyword and return element size, return -1 on read error */
1180 return (-1);
1182 return (-1);
1184 return (-1);
1218 return (-1);
1234 vrs->cksum -= fixup;
1237 /* fetch one read-only element and return size of heading + data */
1246 cfg = vrs->cfg;
1247 vpd = &cfg->vpd;
1250 return (-1);
1251 vpd->vpd_ros = alloc_buffer(vpd->vpd_ros, sizeof(*vpd->vpd_ros), vpd->vpd_rocnt);
1252 vpd_ros = &vpd->vpd_ros[vpd->vpd_rocnt];
1253 maxsize -= 3;
1254 len = vpd_read_elem_data(vrs, vpd_ros->keyword, &vpd_ros->value, maxsize);
1255 if (vpd_ros->value == NULL)
1256 return (-1);
1257 vpd_ros->len = len;
1258 if (vpd_ros->keyword[0] == 'R' && vpd_ros->keyword[1] == 'V') {
1259 vpd_fixup_cksum(vrs, vpd_ros->value, len);
1260 if (vrs->cksum != 0) {
1262 "invalid VPD checksum %#hhx\n", vrs->cksum);
1263 return (-1);
1266 vpd->vpd_rocnt++;
1280 cfg = vrs->cfg;
1281 vpd = &cfg->vpd;
1284 return (-1);
1285 vpd->vpd_w = alloc_buffer(vpd->vpd_w, sizeof(*vpd->vpd_w), vpd->vpd_wcnt);
1286 if (vpd->vpd_w == NULL) {
1288 return (-1);
1290 vpd_w = &vpd->vpd_w[vpd->vpd_wcnt];
1291 maxsize -= 3;
1292 vpd_w->start = vrs->off + 3 - vrs->bytesinval;
1293 len = vpd_read_elem_data(vrs, vpd_w->keyword, &vpd_w->value, maxsize);
1294 if (vpd_w->value == NULL)
1295 return (-1);
1296 vpd_w->len = len;
1297 vpd->vpd_wcnt++;
1308 free(vpd->vpd_ident, M_DEVBUF);
1309 for (i = 0; i < vpd->vpd_rocnt; i++)
1310 free(vpd->vpd_ros[i].value, M_DEVBUF);
1311 free(vpd->vpd_ros, M_DEVBUF);
1312 vpd->vpd_rocnt = 0;
1313 for (i = 0; i < vpd->vpd_wcnt; i++)
1314 free(vpd->vpd_w[i].value, M_DEVBUF);
1315 free(vpd->vpd_w, M_DEVBUF);
1316 vpd->vpd_wcnt = 0;
1338 /* read VPD ident element - mandatory */
1344 cfg->vpd.vpd_ident = vpd_read_value(&vrs, size);
1345 if (cfg->vpd.vpd_ident == NULL) {
1350 /* read VPD RO elements - mandatory */
1353 pci_printf(cfg, "no read-only VPD data found\n");
1359 pci_printf(cfg, "error accessing read-only VPD data\n");
1360 return (-1);
1362 size -= elem_size;
1366 return (-1);
1368 /* read VPD RW elements - optional */
1370 if (size == -2)
1371 return (-1);
1376 return (-1);
1378 size -= elem_size;
1381 /* read empty END tag - mandatory */
1396 vpd_free(&cfg->vpd);
1397 cfg->vpd.vpd_cached = 1;
1406 pcicfgregs *cfg = &dinfo->cfg;
1408 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1411 *identptr = cfg->vpd.vpd_ident;
1424 pcicfgregs *cfg = &dinfo->cfg;
1427 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1430 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1431 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1432 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1433 *vptr = cfg->vpd.vpd_ros[i].value;
1445 pcicfgregs *cfg = &dinfo->cfg;
1447 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1449 return (&cfg->vpd);
1543 pcicfgregs *cfg = &dinfo->cfg;
1558 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1577 for (cnt = 0; ptr != 0 && cnt < (PCIE_REGMAX - 0x40) / 2; cnt++) {
1626 pcicfgregs *cfg = &dinfo->cfg;
1630 /* Only supported for PCI-express devices. */
1631 if (cfg->pcie.pcie_location == 0)
1663 pcicfgregs *cfg = &dinfo->cfg;
1667 /* Only supported for PCI-express devices. */
1668 if (cfg->pcie.pcie_location == 0)
1689 * Support for MSI-X message interrupts.
1695 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1698 KASSERT(msix->msix_table_len > index, ("bogus index"));
1699 offset = msix->msix_table_offset + index * 16;
1700 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1701 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1702 bus_write_4(msix->msix_table_res, offset + 8, data);
1712 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1723 msix->msix_location + PCIR_MSIX_CTRL,
1724 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2);
1729 /* Enable MSI -> HT mapping. */
1737 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1740 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index"));
1741 offset = msix->msix_table_offset + index * 16 + 12;
1742 val = bus_read_4(msix->msix_table_res, offset);
1749 bus_write_4(msix->msix_table_res, offset, val);
1756 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1759 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index"));
1760 offset = msix->msix_table_offset + index * 16 + 12;
1761 val = bus_read_4(msix->msix_table_res, offset);
1768 bus_write_4(msix->msix_table_res, offset, val);
1775 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1778 KASSERT(msix->msix_table_len > index, ("bogus index"));
1779 offset = msix->msix_pba_offset + (index / 32) * 4;
1781 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1785 * Restore MSI-X registers and table during resume. If MSI-X is
1786 * enabled then walk the virtual table to restore the actual MSI-X
1793 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1798 if (msix->msix_alloc > 0) {
1799 msgnum = PCI_MSIX_MSGNUM(msix->msix_ctrl);
1806 for (i = 0; i < msix->msix_table_len; i++) {
1807 mte = &msix->msix_table[i];
1808 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1810 mv = &msix->msix_vectors[mte->mte_vector - 1];
1811 pci_write_msix_entry(dev, i, mv->mv_address,
1812 mv->mv_data);
1816 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1817 msix->msix_ctrl, 2);
1821 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1829 pcicfgregs *cfg = &dinfo->cfg;
1840 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1841 if (rle != NULL && rle->res != NULL)
1845 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1848 /* If MSI-X is blacklisted for this system, fail. */
1852 /* MSI-X capability present? */
1853 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1857 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1858 cfg->msix.msix_table_bar);
1859 if (rle == NULL || rle->res == NULL ||
1860 !(rman_get_flags(rle->res) & RF_ACTIVE))
1862 cfg->msix.msix_table_res = rle->res;
1863 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1864 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1865 cfg->msix.msix_pba_bar);
1866 if (rle == NULL || rle->res == NULL ||
1867 !(rman_get_flags(rle->res) & RF_ACTIVE))
1870 cfg->msix.msix_pba_res = rle->res;
1872 ctrl = pci_read_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1877 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1888 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1894 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1896 device_printf(child, "using IRQ %ju for MSI-X\n",
1897 rle->start);
1906 device_printf(child, "using IRQs %ju", rle->start);
1907 irq = rle->start;
1910 rle = resource_list_find(&dinfo->resources,
1914 if (rle->start == irq + 1) {
1922 printf("-%d", irq);
1927 printf(",%ju", rle->start);
1928 irq = rle->start;
1933 printf("-%d", irq);
1934 printf(" for MSI-X\n");
1942 cfg->msix.msix_ctrl = ctrl;
1947 cfg->msix.msix_vectors = mallocarray(actual, sizeof(struct msix_vector),
1949 cfg->msix.msix_table = mallocarray(actual,
1952 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1953 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1954 cfg->msix.msix_table[i].mte_vector = i + 1;
1957 /* Update control register to enable MSI-X. */
1959 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1961 cfg->msix.msix_ctrl = ctrl;
1964 cfg->msix.msix_alloc = actual;
1965 cfg->msix.msix_table_len = actual;
1972 * resources consecutively to the first N messages in the MSI-X table.
1975 * populate the MSI-X table sparsely. This method allows the driver
1981 * maps directly to the MSI-X table in that index 0 in the array
1982 * specifies the vector for the first message in the MSI-X table, etc.
1989 * On successful return, each message with a non-zero vector will have
1995 * For example, suppose a driver has a MSI-X table with 6 messages and
1997 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1999 * have an MSI-X table of ABC--- (where - means no vector assigned).
2001 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
2006 * at MSI-X table index X - 1 and will only be valid if a vector is
2014 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2021 * table can't be bigger than the actual MSI-X table in the
2024 if (count < 1 || count > PCI_MSIX_MSGNUM(msix->msix_ctrl))
2029 if (vectors[i] > msix->msix_alloc)
2037 used = mallocarray(msix->msix_alloc, sizeof(*used), M_DEVBUF, M_WAITOK |
2041 used[vectors[i] - 1] = true;
2042 for (i = 0; i < msix->msix_alloc - 1; i++)
2053 for (i = 0; i < msix->msix_table_len; i++) {
2054 if (msix->msix_table[i].mte_vector == 0)
2056 if (msix->msix_table[i].mte_handlers > 0) {
2060 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2062 if (rle->res != NULL) {
2069 for (i = 0; i < msix->msix_table_len; i++) {
2070 if (msix->msix_table[i].mte_vector == 0)
2072 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2079 free(msix->msix_table, M_DEVBUF);
2080 msix->msix_table = mallocarray(count, sizeof(struct msix_table_entry),
2083 msix->msix_table[i].mte_vector = vectors[i];
2084 msix->msix_table_len = count;
2087 j = msix->msix_alloc - 1;
2093 msix->msix_vectors[j].mv_irq);
2094 j--;
2098 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
2100 free(msix->msix_vectors, M_DEVBUF);
2101 msix->msix_vectors = vec;
2102 msix->msix_alloc = j + 1;
2110 irq = msix->msix_vectors[vectors[i] - 1].mv_irq;
2111 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
2116 device_printf(child, "Remapped MSI-X IRQs as: ");
2121 printf("---");
2124 msix->msix_vectors[vectors[i] - 1].mv_irq);
2136 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2141 if (msix->msix_alloc == 0)
2145 for (i = 0; i < msix->msix_table_len; i++) {
2146 if (msix->msix_table[i].mte_vector == 0)
2148 if (msix->msix_table[i].mte_handlers > 0)
2150 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2152 if (rle->res != NULL)
2156 /* Update control register to disable MSI-X. */
2157 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
2158 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
2159 msix->msix_ctrl, 2);
2162 for (i = 0; i < msix->msix_table_len; i++) {
2163 if (msix->msix_table[i].mte_vector == 0)
2165 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2167 free(msix->msix_table, M_DEVBUF);
2168 msix->msix_table_len = 0;
2171 for (i = 0; i < msix->msix_alloc; i++)
2173 msix->msix_vectors[i].mv_irq);
2174 free(msix->msix_vectors, M_DEVBUF);
2175 msix->msix_alloc = 0;
2180 * Return the max supported MSI-X messages this device supports.
2189 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2192 if (pci_do_msix && msix->msix_location != 0) {
2193 ctrl = pci_read_config(child, msix->msix_location +
2204 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2206 if (pci_do_msix && msix->msix_location != 0)
2207 return (msix->msix_pba_bar);
2208 return (-1);
2215 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2217 if (pci_do_msix && msix->msix_location != 0)
2218 return (msix->msix_table_bar);
2219 return (-1);
2229 struct pcicfg_ht *ht = &dinfo->cfg.ht;
2231 if (!ht->ht_msimap)
2234 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
2235 ht->ht_msiaddr >> 20 == addr >> 20) {
2236 /* Enable MSI -> HT mapping. */
2237 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
2238 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
2239 ht->ht_msictrl, 2);
2242 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
2243 /* Disable MSI -> HT mapping. */
2244 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
2245 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
2246 ht->ht_msictrl, 2);
2257 cap = dinfo->cfg.pcie.pcie_location;
2272 cap = dinfo->cfg.pcie.pcie_location;
2288 cap = dinfo->cfg.pcie.pcie_location;
2304 cap = dinfo->cfg.pcie.pcie_location;
2311 size = (1 << (fls(size) - 1));
2314 val |= (fls(size) - 8) << 12;
2325 cap = dinfo->cfg.pcie.pcie_location;
2341 cap = dinfo->cfg.pcie.pcie_location;
2348 * Adjusts a PCI-e capability register by clearing the bits in mask
2362 cap = dinfo->cfg.pcie.pcie_location;
2384 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2387 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR,
2389 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
2390 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH,
2392 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT,
2395 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data,
2399 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
2400 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2401 msi->msi_ctrl, 2);
2403 /* Enable MSI -> HT mapping. */
2411 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2413 /* Disable MSI -> HT mapping. */
2417 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
2418 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2419 msi->msi_ctrl, 2);
2431 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2435 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
2436 address = msi->msi_addr;
2437 data = msi->msi_data;
2438 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
2440 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
2441 pci_write_config(dev, msi->msi_location +
2443 pci_write_config(dev, msi->msi_location +
2446 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
2449 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
2457 pcicfgregs *cfg = &dinfo->cfg;
2471 if (cfg->msi.msi_alloc > 0) {
2473 if (cfg->msi.msi_handlers == 0)
2475 for (i = 0; i < cfg->msi.msi_alloc; i++) {
2476 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
2478 if (rle->start == irq) {
2484 dinfo->cfg.msi.msi_addr = addr;
2485 dinfo->cfg.msi.msi_data = data;
2494 * For MSI-X, we check to see if we have this IRQ. If we do,
2498 if (cfg->msix.msix_alloc > 0) {
2501 for (i = 0; i < cfg->msix.msix_alloc; i++) {
2502 mv = &cfg->msix.msix_vectors[i];
2503 if (mv->mv_irq == irq) {
2508 mv->mv_address = addr;
2509 mv->mv_data = data;
2510 for (j = 0; j < cfg->msix.msix_table_len; j++) {
2511 mte = &cfg->msix.msix_table[j];
2512 if (mte->mte_vector != i + 1)
2514 if (mte->mte_handlers == 0)
2546 * host-PCI bridge at device 0:0:0. In the future, it may become
2558 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2580 * Returns true if the specified device is blacklisted because MSI-X
2582 * MSI-X doesn't either.
2598 * Determine if MSI-X is blacklisted globally on this system. If MSI
2599 * is blacklisted, assume that MSI-X is as well. Check for additional
2600 * chipsets where MSI works but MSI-X does not.
2627 pcicfgregs *cfg = &dinfo->cfg;
2638 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2639 if (rle != NULL && rle->res != NULL)
2643 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2651 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2654 ctrl = pci_read_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 2);
2690 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2708 if (irqs[i] == irqs[i - 1] + 1) {
2715 printf("-%d", irqs[i - 1]);
2725 printf("-%d", irqs[actual - 1]);
2732 ctrl |= (ffs(actual) - 1) << 4;
2733 cfg->msi.msi_ctrl = ctrl;
2734 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2737 cfg->msi.msi_alloc = actual;
2738 cfg->msi.msi_handlers = 0;
2748 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2753 /* Try MSI-X first. */
2759 if (msi->msi_alloc == 0)
2761 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2764 if (msi->msi_handlers > 0)
2766 for (i = 0; i < msi->msi_alloc; i++) {
2767 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2769 if (rle->res != NULL)
2771 irqs[i] = rle->start;
2775 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2777 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2778 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2779 msi->msi_ctrl, 2);
2782 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2783 for (i = 0; i < msi->msi_alloc; i++)
2784 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2787 msi->msi_alloc = 0;
2788 msi->msi_addr = 0;
2789 msi->msi_data = 0;
2803 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2806 if (pci_do_msi && msi->msi_location != 0) {
2807 ctrl = pci_read_config(child, msi->msi_location + PCIR_MSI_CTRL,
2824 if (dinfo->cfg.vpd.vpd_reg)
2825 vpd_free(&dinfo->cfg.vpd);
2827 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) {
2837 pci_numdevs--;
2848 pcicfgregs *cfg = &dinfo->cfg;
2852 if (cfg->pp.pp_location == 0)
2858 * behavior when going from D3 -> D3.
2883 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location +
2890 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2895 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2911 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_location + PCIR_POWER_STATUS,
2922 pcicfgregs *cfg = &dinfo->cfg;
2926 if (cfg->pp.pp_location != 0) {
2927 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location +
2958 pcicfgregs *cfg = &dinfo->cfg;
2961 if (cfg->pp.pp_location != 0) {
2962 status = pci_read_config(dev, dinfo->cfg.pp.pp_location +
2966 pci_write_config(dev, dinfo->cfg.pp.pp_location +
2976 pcicfgregs *cfg = &dinfo->cfg;
2979 if (cfg->pp.pp_location != 0) {
2980 status = pci_read_config(dev, dinfo->cfg.pp.pp_location +
2983 pci_write_config(dev, dinfo->cfg.pp.pp_location +
2992 pcicfgregs *cfg = &dinfo->cfg;
2994 return (cfg->pp.pp_location != 0);
3074 * New style pci driver. Parent device is either a pci-host-bridge or a
3075 * pci-pci-bridge. Both kinds are represented by instances of pcib.
3083 pcicfgregs *cfg = &dinfo->cfg;
3085 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
3086 cfg->vendor, cfg->device, cfg->revid);
3087 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
3088 cfg->domain, cfg->bus, cfg->slot, cfg->func);
3089 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
3090 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
3091 cfg->mfdev);
3093 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
3095 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
3096 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
3097 if (cfg->intpin > 0)
3099 cfg->intpin +'a' -1, cfg->intline);
3100 if (cfg->pp.pp_location) {
3103 status = pci_read_config(cfg->dev, cfg->pp.pp_location +
3106 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
3107 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
3108 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
3111 if (cfg->msi.msi_location) {
3114 ctrl = cfg->msi.msi_ctrl;
3121 if (cfg->msix.msix_location) {
3124 msgnum = PCI_MSIX_MSGNUM(cfg->msix.msix_ctrl);
3125 printf("\tMSI-X supports %d message%s ",
3127 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
3129 cfg->msix.msix_table_bar);
3132 cfg->msix.msix_table_bar,
3133 cfg->msix.msix_pba_bar);
3160 * The device ROM BAR is special. It is always a 32-bit
3165 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) {
3198 * and combines the result into a 64-bit value." (section 6.2.5.1)
3213 * the BAR of the low-level console device and when booting verbose,
3233 /* The device ROM BAR is always a 32-bit memory BAR. */
3235 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
3238 ln2range = pci_maprange(pm->pm_value);
3239 pci_write_config(dev, pm->pm_reg, base, 4);
3241 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4);
3242 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4);
3244 pm->pm_value |= (pci_addr_t)pci_read_config(dev,
3245 pm->pm_reg + 4, 4) << 32;
3255 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
3256 if (pm->pm_reg == reg)
3268 return (STAILQ_FIRST(&dinfo->cfg.maps));
3284 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) &&
3285 !(pm->pm_value & PCIM_BIOS_ENABLE))
3288 if ((dinfo->cfg.flags & PCICFG_VF) != 0) {
3291 iov = dinfo->cfg.iov;
3292 cmd = pci_read_config(iov->iov_pf,
3293 iov->iov_pos + PCIR_SRIOV_CTL, 2);
3298 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value))
3312 pm->pm_reg = reg;
3313 pm->pm_value = value;
3314 pm->pm_size = size;
3315 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) {
3316 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x",
3319 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg)
3323 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link);
3325 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link);
3337 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
3338 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
3341 ln2range = pci_maprange(pm->pm_value);
3342 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4);
3344 pci_write_config(dev, pm->pm_reg + 4,
3345 pm->pm_value >> 32, 4);
3370 maprange = pci_maprange(pm->pm_value);
3474 end = base + count - 1;
3588 pcicfgregs *cfg = &dinfo->cfg;
3593 if (cfg->intpin == 0)
3600 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
3612 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
3615 irq = cfg->intline;
3623 if (irq != cfg->intline) {
3624 cfg->intline = irq;
3629 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
3769 eec = -1;
3820 switch (cfg->hdrtype & PCIM_HDRTYPE) {
3885 count = end - start + 1;
3927 cfg = &dinfo->cfg;
3928 rl = &dinfo->resources;
3929 switch (cfg->hdrtype & PCIM_HDRTYPE) {
3976 iov = dinfo->cfg.iov;
3978 iov_pos = iov->iov_pos;
3996 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) +
4000 return (-1);
4011 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) {
4012 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid)
4013 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0);
4034 rl = &dinfo->resources;
4038 iov = dinfo->cfg.iov;
4041 if (dinfo->cfg.ea.ea_location == 0)
4044 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) {
4046 * TODO: Ignore EA-BAR if is not enabled.
4051 * a legacy-BAR mechanism.
4053 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0)
4056 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) {
4075 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) ||
4076 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5))
4083 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) ||
4084 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) &&
4085 (ea->eae_bei != PCIM_EA_BEI_ROM))
4089 rid = pci_ea_bei_to_rid(dev, ea->eae_bei);
4098 start = ea->eae_base;
4099 count = ea->eae_max_offset + 1;
4102 count = count * iov->iov_num_vfs;
4104 end = start + count - 1;
4119 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4);
4121 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4);
4127 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4);
4148 cfg = &dinfo->cfg;
4149 rl = &dinfo->resources;
4150 devid = (cfg->device << 16) | cfg->vendor;
4163 for (i = 0; i < cfg->nummaps;) {
4175 for (q = &pci_quirks[0]; q->devid != 0; q++)
4176 if (q->devid == devid &&
4177 q->type == PCI_QUIRK_UNMAP_REG &&
4178 q->arg1 == PCIR_BAR(i))
4180 if (q->devid != 0) {
4191 for (q = &pci_quirks[0]; q->devid != 0; q++)
4192 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)
4193 pci_add_map(bus, dev, q->arg1, rl, force, 0);
4195 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline) &&
4198 * Try to re-route interrupts. Sometimes the BIOS or
4200 * If the re-route fails, then just stick with what we
4227 int slot, int func)
4231 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func);
4257 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev);
4387 int busno, slot, func;
4391 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func);
4394 slot, func, vid, did);
4396 vf_dinfo->cfg.flags |= PCICFG_VF;
4399 return (vf_dinfo->cfg.dev);
4421 if (dinfo->cfg.pcie.pcie_location == 0)
4457 if (dinfo->cfg.pcie.pcie_location != 0 &&
4458 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) {
4459 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
4463 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
4470 pci_printf(&dinfo->cfg,
4471 "clearing AER UC 0x%08x -> 0x%08x\n",
4499 pci_printf(&dinfo->cfg,
4500 "clearing AER COR 0x%08x -> 0x%08x\n",
4516 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
4520 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
4530 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY);
4532 resource_list_init(&dinfo->resources);
4540 pci_child_added(dinfo->cfg.dev);
4545 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev);
4575 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno,
4577 if (sc->sc_bus == NULL) {
4584 sc->sc_dma_tag = bus_get_dma_tag(dev);
4620 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus);
4630 uint8_t b, s, f;
4635 b = pci_get_bus(child);
4638 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f);
4639 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f);
4703 * as MSI/MSI-X interrupts are never shared.
4705 rle = resource_list_find(&dinfo->resources,
4707 if (rle != NULL && rle->res != NULL)
4708 (void)bus_suspend_intr(child, rle->res);
4737 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
4738 if (rle != NULL && rle->res != NULL)
4739 (void)bus_resume_intr(child, rle->res);
4825 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
4862 * Check to see if the interrupt is MSI or MSI-X.
4869 if (dinfo->cfg.msi.msi_alloc > 0) {
4870 if (dinfo->cfg.msi.msi_addr == 0) {
4871 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
4877 dinfo->cfg.msi.msi_addr = addr;
4878 dinfo->cfg.msi.msi_data = data;
4880 if (dinfo->cfg.msi.msi_handlers == 0)
4881 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
4882 dinfo->cfg.msi.msi_data);
4883 dinfo->cfg.msi.msi_handlers++;
4885 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
4886 ("No MSI or MSI-X interrupts allocated"));
4887 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
4888 ("MSI-X index too high"));
4889 mte = &dinfo->cfg.msix.msix_table[rid - 1];
4890 KASSERT(mte->mte_vector != 0, ("no message vector"));
4891 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
4892 KASSERT(mv->mv_irq == rman_get_start(irq),
4894 if (mv->mv_address == 0) {
4895 KASSERT(mte->mte_handlers == 0,
4896 ("MSI-X table entry has handlers, but vector not mapped"));
4901 mv->mv_address = addr;
4902 mv->mv_data = data;
4912 mte->mte_handlers++;
4913 if (mte->mte_handlers == 1) {
4914 pci_enable_msix(child, rid - 1, mv->mv_address,
4915 mv->mv_data);
4916 pci_unmask_msix(child, rid - 1);
4921 * Make sure that INTx is disabled if we are using MSI/MSI-X,
4923 * in which case we "enable" INTx so MSI/MSI-X actually works.
4963 * Check to see if the interrupt is MSI or MSI-X. If so,
4965 * MSI-X message, or disable MSI messages if the count
4969 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
4970 if (rle->res != irq)
4972 if (dinfo->cfg.msi.msi_alloc > 0) {
4973 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
4974 ("MSI-X index too high"));
4975 if (dinfo->cfg.msi.msi_handlers == 0)
4977 dinfo->cfg.msi.msi_handlers--;
4978 if (dinfo->cfg.msi.msi_handlers == 0)
4981 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
4982 ("No MSI or MSI-X interrupts allocated"));
4983 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
4984 ("MSI-X index too high"));
4985 mte = &dinfo->cfg.msix.msix_table[rid - 1];
4986 if (mte->mte_handlers == 0)
4988 mte->mte_handlers--;
4989 if (mte->mte_handlers == 0)
4990 pci_mask_msix(child, rid - 1);
4996 ("%s: generic teardown failed for MSI/MSI-X", __func__));
5008 rl = &dinfo->resources;
5034 {PCIC_OLD, -1, 1, "old"},
5035 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"},
5036 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"},
5037 {PCIC_STORAGE, -1, 1, "mass storage"},
5047 {PCIC_NETWORK, -1, 1, "network"},
5053 {PCIC_DISPLAY, -1, 1, "display"},
5057 {PCIC_MULTIMEDIA, -1, 1, "multimedia"},
5062 {PCIC_MEMORY, -1, 1, "memory"},
5065 {PCIC_BRIDGE, -1, 1, "bridge"},
5066 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"},
5067 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"},
5068 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"},
5069 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"},
5070 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"},
5071 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"},
5072 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"},
5073 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"},
5074 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"},
5075 {PCIC_SIMPLECOMM, -1, 1, "simple comms"},
5076 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */
5080 {PCIC_BASEPERIPH, -1, 0, "base peripheral"},
5085 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"},
5088 {PCIC_INPUTDEV, -1, 1, "input device"},
5094 {PCIC_DOCKING, -1, 1, "docking station"},
5095 {PCIC_PROCESSOR, -1, 1, "processor"},
5096 {PCIC_SERIALBUS, -1, 1, "serial bus"},
5103 {PCIC_WIRELESS, -1, 1, "wireless controller"},
5107 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"},
5109 {PCIC_SATCOM, -1, 1, "satellite communication"},
5114 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"},
5117 {PCIC_DASP, -1, 0, "dasp"},
5122 {PCIC_INSTRUMENT, -1, 0, "non-essential instrumentation"},
5149 if (pci_nomatch_tab[i].subclass == -1) {
5180 rl = &dinfo->resources;
5188 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n");
5189 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
5190 if (dinfo->cfg.msi.msi_alloc != 0)
5191 pci_printf(&dinfo->cfg, "Device leaked %d MSI "
5192 "vectors\n", dinfo->cfg.msi.msi_alloc);
5194 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X "
5195 "vectors\n", dinfo->cfg.msix.msix_alloc);
5199 pci_printf(&dinfo->cfg, "Device leaked memory resources\n");
5201 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n");
5203 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n");
5221 * - devices cannot be listed without a corresponding VENDOR line.
5230 * is set to -1. Returns nonzero at the end of the database.
5242 *device = -1;
5243 *vendor = -1;
5246 left = pci_vendordata_size - (cp - pci_vendordata);
5264 left--;
5268 left--;
5274 left--;
5315 if (vendor != -1) {
5342 cfg = &dinfo->cfg;
5353 *result = cfg->subvendor;
5356 *result = cfg->subdevice;
5359 *result = cfg->vendor;
5362 *result = cfg->device;
5365 *result = (cfg->device << 16) | cfg->vendor;
5368 *result = cfg->baseclass;
5371 *result = cfg->subclass;
5374 *result = cfg->progif;
5377 *result = cfg->revid;
5380 *result = cfg->intpin;
5383 *result = cfg->intline;
5386 *result = cfg->domain;
5389 *result = cfg->bus;
5392 *result = cfg->slot;
5395 *result = cfg->func;
5398 *result = cfg->cmdreg;
5401 *result = cfg->cachelnsz;
5404 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) {
5405 *result = -1;
5408 *result = cfg->mingnt;
5411 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) {
5412 *result = -1;
5415 *result = cfg->maxlat;
5418 *result = cfg->lattimer;
5435 dinfo->cfg.intpin = value;
5489 if (dinfo->cfg.dev)
5490 name = device_get_name(dinfo->cfg.dev);
5492 p = &dinfo->conf;
5496 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
5498 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
5499 p->pc_sel.pc_func, (p->pc_class << 16) |
5500 (p->pc_subclass << 8) | p->pc_progif,
5501 (p->pc_subdevice << 16) | p->pc_subvendor,
5502 (p->pc_device << 16) | p->pc_vendor,
5503 p->pc_revid, p->pc_hdr);
5514 struct resource_list *rl = &dinfo->resources;
5530 mapsize = pm->pm_size;
5531 map = pm->pm_value;
5547 if (PCIR_IS_BIOS(&dinfo->cfg, *rid))
5556 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) {
5637 rl = &dinfo->resources;
5638 cfg = &dinfo->cfg;
5648 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
5649 cfg->msix.msix_alloc > 0))
5657 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
5658 (cfg->intpin != 0))
5664 * PCI-PCI bridge I/O window resources are not BARs.
5668 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) {
5708 if (dinfo->cfg.flags & PCICFG_VF) {
5737 cfg = &dinfo->cfg;
5740 if (cfg->flags & PCICFG_VF) {
5754 * PCI-PCI bridge I/O window resources are not BARs. For
5757 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE &&
5768 rl = &dinfo->resources;
5783 if (dinfo->cfg.flags & PCICFG_VF) {
5806 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
5831 if (dinfo->cfg.flags & PCICFG_VF) {
5853 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
5871 if (dinfo->cfg.flags & PCICFG_VF) {
5900 if (dinfo->cfg.flags & PCICFG_VF) {
5928 if (dinfo->cfg.flags & PCICFG_VF) {
5952 rl = &dinfo->resources;
5966 if (rle->res) {
5967 if (rman_get_flags(rle->res) & RF_ACTIVE ||
5968 resource_list_busy(rl, rle->type, rle->rid)) {
5969 pci_printf(&dinfo->cfg,
5972 rle->type, rle->rid,
5973 rman_get_start(rle->res));
5974 bus_release_resource(child, rle->type, rle->rid,
5975 rle->res);
5977 resource_list_unreserve(rl, dev, child, rle->type,
5978 rle->rid);
5997 rl = &dinfo->resources;
6002 if (rle->res) {
6003 if (rman_get_flags(rle->res) & RF_ACTIVE ||
6008 type, rid, rman_get_start(rle->res));
6021 return (&dinfo->resources);
6038 tag = sc->sc_dma_tag;
6048 return (sc->sc_dma_tag);
6056 pcicfgregs *cfg = &dinfo->cfg;
6060 * SR-IOV VFs don't implement the VID or DID registers, so we have to
6063 if (cfg->flags & PCICFG_VF) {
6067 return (cfg->device << 16 | cfg->vendor);
6069 return (cfg->vendor);
6071 return (cfg->vendor & 0xff);
6077 /* Note that an unaligned 4-byte read is an error. */
6079 return (cfg->device);
6081 return (cfg->device & 0xff);
6090 cfg->bus, cfg->slot, cfg->func, reg, width));
6098 pcicfgregs *cfg = &dinfo->cfg;
6101 cfg->bus, cfg->slot, cfg->func, reg, val, width);
6121 cfg = &dinfo->cfg;
6123 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
6124 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
6125 cfg->progif);
6151 pcicfgregs *cfg = &dinfo->cfg;
6154 cfg->intpin));
6162 int domain, bus, slot, func;
6168 * Accept pciconf-style selectors of either pciD:B:S:F or
6190 func = val;
6192 func = slot;
6200 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX))
6203 *dev = pci_find_dbsf(domain, bus, slot, func);
6240 cfg = &dinfo->cfg.pcie;
6241 pos = cfg->pcie_location;
6243 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
6245 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl);
6247 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6248 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
6249 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
6250 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl);
6252 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6253 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
6254 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
6255 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl);
6257 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6258 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
6259 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl);
6262 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2);
6263 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2);
6264 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2);
6272 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND,
6273 dinfo->cfg.pcix.pcix_command, 2);
6290 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
6291 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
6292 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
6293 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
6294 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
6295 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
6296 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) {
6298 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
6299 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
6303 dinfo->cfg.bridge.br_seclat, 1);
6305 dinfo->cfg.bridge.br_subbus, 1);
6307 dinfo->cfg.bridge.br_secbus, 1);
6309 dinfo->cfg.bridge.br_pribus, 1);
6311 dinfo->cfg.bridge.br_control, 2);
6315 dinfo->cfg.bridge.br_seclat, 1);
6317 dinfo->cfg.bridge.br_subbus, 1);
6319 dinfo->cfg.bridge.br_secbus, 1);
6321 dinfo->cfg.bridge.br_pribus, 1);
6323 dinfo->cfg.bridge.br_control, 2);
6328 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE)
6329 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
6332 * Restore extended capabilities for PCI-Express and PCI-X
6334 if (dinfo->cfg.pcie.pcie_location != 0)
6336 if (dinfo->cfg.pcix.pcix_location != 0)
6339 /* Restore MSI and MSI-X configurations if they are present. */
6340 if (dinfo->cfg.msi.msi_location != 0)
6342 if (dinfo->cfg.msix.msix_location != 0)
6346 if (dinfo->cfg.iov != NULL)
6358 cfg = &dinfo->cfg.pcie;
6359 pos = cfg->pcie_location;
6361 cfg->pcie_flags = RREG(PCIER_FLAGS);
6363 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
6365 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL);
6367 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6368 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
6369 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
6370 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL);
6372 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6373 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
6374 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
6375 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL);
6377 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6378 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
6379 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL);
6382 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2);
6383 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2);
6384 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2);
6392 dinfo->cfg.pcix.pcix_command = pci_read_config(dev,
6393 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2);
6409 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
6410 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
6411 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
6412 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
6413 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
6414 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
6415 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
6416 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
6417 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
6418 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
6419 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
6420 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) {
6422 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
6423 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
6424 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
6425 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
6428 dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
6430 dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
6432 dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
6434 dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
6436 dinfo->cfg.bridge.br_control = pci_read_config(dev,
6440 dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
6442 dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
6444 dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
6446 dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
6448 dinfo->cfg.bridge.br_control = pci_read_config(dev,
6450 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2);
6451 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2);
6455 if (dinfo->cfg.pcie.pcie_location != 0)
6458 if (dinfo->cfg.pcix.pcix_location != 0)
6462 if (dinfo->cfg.iov != NULL)
6469 * We should (a) have drivers that can easily detach and (b) use
6541 ("%s: non-pci device %s", __func__, device_get_nameunit(dev)));
6544 * Walk the bridge hierarchy until we find a PCI-e root
6545 * port or a non-PCI device.
6558 * PCI-PCI bridge.
6564 if (dinfo->cfg.pcie.pcie_location != 0 &&
6565 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)
6573 * Wait for pending transactions to complete on a PCI-express function.
6579 * exceeded. If dev is not a PCI-express function, this returns true.
6588 cap = dinfo->cfg.pcie.pcie_location;
6600 max_delay -= 100;
6615 * For non-PCI-express functions this returns 0.
6623 cap = dinfo->cfg.pcie.pcie_location;
6632 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 ||
6672 s = "Uncorrectable (Non-Fatal)";
6708 if (dinfo->cfg.pcie.pcie_location != 0) {
6709 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
6714 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
6729 * If dev is not a PCI-express function or does not support FLR, this
6734 * PCI-standard registers via pci_save_state() and
6745 cap = dinfo->cfg.pcie.pcie_location;
6758 * which will re-enable busmastering.
6767 pci_printf(&dinfo->cfg,
6772 * Extend the post-FLR delay to cover the maximum
6793 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n");
6798 * Attempt a power-management reset by cycling the device in/out of D3
6898 while (nelt-- > 0) {
6900 if (id->match_flag_vendor)
6901 match &= vendor == id->vendor;
6902 if (id->match_flag_device)
6903 match &= device == id->device;
6904 if (id->match_flag_subvendor)
6905 match &= subvendor == id->subvendor;
6906 if (id->match_flag_subdevice)
6907 match &= subdevice == id->subdevice;
6908 if (id->match_flag_class)
6909 match &= class == id->class_id;
6910 if (id->match_flag_subclass)
6911 match &= subclass == id->subclass;
6912 if (id->match_flag_revid)
6913 match &= revid == id->revid;
6927 dev = dinfo->cfg.dev;
6928 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus,
6929 dinfo->cfg.slot, dinfo->cfg.func);
6945 dev = dinfo->cfg.dev;
6954 if (dinfo->cfg.pcie.pcie_location != 0) {
6956 dinfo->cfg.pcie.pcie_location +
6964 dinfo->cfg.pcie.pcie_location +
7008 dev = dinfo->cfg.dev;
7009 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
7011 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
7031 dev = dinfo->cfg.dev;
7040 if (dinfo->cfg.pcie.pcie_location != 0)