Lines Matching +full:keyboard +full:- +full:controller +full:- +full:style
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
77 #include <dev/usb/controller/xhcireg.h>
78 #include <dev/usb/controller/ehcireg.h>
79 #include <dev/usb/controller/ohcireg.h>
80 #include <dev/usb/controller/uhcireg.h>
88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
255 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
256 * or the CMIC-SL (AKA ServerWorks GC_LE).
274 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
287 * controller depending on SoftPciRst register (PM_IO 0x55 [7]).
350 "firmware-assigned ranges fail to allocate during the initial device scan.");
363 "Transition from D3 -> D0 on resume.");
368 "Transition from D0 -> D3 on suspend.");
376 "Enable support for MSI-X interrupts");
381 "Rewrite entire MSI-X table when updating MSI-X entries");
385 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
396 " keyboard or mouse) but do not load USB drivers");
400 "Ignore firmware-assigned resources for BARs.");
404 "Ignore firmware-assigned bus numbers.");
434 &pci_intx_reroute, 0, "Re-route INTx interrupts when scanning devices");
441 for (q = &pci_quirks[0]; q->devid; q++) { in pci_has_quirk()
442 if (q->devid == devid && q->type == quirk) in pci_has_quirk()
465 if ((dinfo->cfg.domain == domain) && in pci_find_dbsf()
466 (dinfo->cfg.bus == bus) && in pci_find_dbsf()
467 (dinfo->cfg.slot == slot) && in pci_find_dbsf()
468 (dinfo->cfg.func == func)) { in pci_find_dbsf()
473 return (dinfo != NULL ? dinfo->cfg.dev : NULL); in pci_find_dbsf()
484 if ((dinfo->cfg.vendor == vendor) && in pci_find_device()
485 (dinfo->cfg.device == device)) { in pci_find_device()
486 return (dinfo->cfg.dev); in pci_find_device()
499 if (dinfo->cfg.baseclass == class && in pci_find_class()
500 dinfo->cfg.subclass == subclass) { in pci_find_class()
501 return (dinfo->cfg.dev); in pci_find_class()
516 if (from != dinfo->cfg.dev) in pci_find_class_from()
521 if (dinfo->cfg.baseclass == class && in pci_find_class_from()
522 dinfo->cfg.subclass == subclass) { in pci_find_class_from()
523 return (dinfo->cfg.dev); in pci_find_class_from()
538 if (from != dinfo->cfg.dev) in pci_find_base_class_from()
543 if (dinfo->cfg.baseclass == class) { in pci_find_base_class_from()
544 return (dinfo->cfg.dev); in pci_find_base_class_from()
557 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, in pci_printf()
558 cfg->func); in pci_printf()
666 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) in pci_fixancient()
670 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) in pci_fixancient()
671 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; in pci_fixancient()
680 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_hdrtypedata()
682 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); in pci_hdrtypedata()
683 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); in pci_hdrtypedata()
684 cfg->mingnt = REG(PCIR_MINGNT, 1); in pci_hdrtypedata()
685 cfg->maxlat = REG(PCIR_MAXLAT, 1); in pci_hdrtypedata()
686 cfg->nummaps = PCI_MAXMAPS_0; in pci_hdrtypedata()
689 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); in pci_hdrtypedata()
690 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); in pci_hdrtypedata()
691 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); in pci_hdrtypedata()
692 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); in pci_hdrtypedata()
693 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); in pci_hdrtypedata()
694 cfg->nummaps = PCI_MAXMAPS_1; in pci_hdrtypedata()
697 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); in pci_hdrtypedata()
698 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); in pci_hdrtypedata()
699 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); in pci_hdrtypedata()
700 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); in pci_hdrtypedata()
701 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); in pci_hdrtypedata()
702 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); in pci_hdrtypedata()
703 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); in pci_hdrtypedata()
704 cfg->nummaps = PCI_MAXMAPS_2; in pci_hdrtypedata()
743 cfg = &devlist_entry->cfg; in pci_fill_devinfo()
745 cfg->domain = d; in pci_fill_devinfo()
746 cfg->bus = b; in pci_fill_devinfo()
747 cfg->slot = s; in pci_fill_devinfo()
748 cfg->func = f; in pci_fill_devinfo()
749 cfg->vendor = vid; in pci_fill_devinfo()
750 cfg->device = did; in pci_fill_devinfo()
751 cfg->cmdreg = REG(PCIR_COMMAND, 2); in pci_fill_devinfo()
752 cfg->statreg = REG(PCIR_STATUS, 2); in pci_fill_devinfo()
753 cfg->baseclass = REG(PCIR_CLASS, 1); in pci_fill_devinfo()
754 cfg->subclass = REG(PCIR_SUBCLASS, 1); in pci_fill_devinfo()
755 cfg->progif = REG(PCIR_PROGIF, 1); in pci_fill_devinfo()
756 cfg->revid = REG(PCIR_REVID, 1); in pci_fill_devinfo()
757 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); in pci_fill_devinfo()
758 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); in pci_fill_devinfo()
759 cfg->lattimer = REG(PCIR_LATTIMER, 1); in pci_fill_devinfo()
760 cfg->intpin = REG(PCIR_INTPIN, 1); in pci_fill_devinfo()
761 cfg->intline = REG(PCIR_INTLINE, 1); in pci_fill_devinfo()
763 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; in pci_fill_devinfo()
764 cfg->hdrtype &= ~PCIM_MFDEV; in pci_fill_devinfo()
765 STAILQ_INIT(&cfg->maps); in pci_fill_devinfo()
767 cfg->iov = NULL; in pci_fill_devinfo()
777 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; in pci_fill_devinfo()
778 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; in pci_fill_devinfo()
779 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; in pci_fill_devinfo()
780 devlist_entry->conf.pc_sel.pc_func = cfg->func; in pci_fill_devinfo()
781 devlist_entry->conf.pc_hdr = cfg->hdrtype; in pci_fill_devinfo()
783 devlist_entry->conf.pc_subvendor = cfg->subvendor; in pci_fill_devinfo()
784 devlist_entry->conf.pc_subdevice = cfg->subdevice; in pci_fill_devinfo()
785 devlist_entry->conf.pc_vendor = cfg->vendor; in pci_fill_devinfo()
786 devlist_entry->conf.pc_device = cfg->device; in pci_fill_devinfo()
788 devlist_entry->conf.pc_class = cfg->baseclass; in pci_fill_devinfo()
789 devlist_entry->conf.pc_subclass = cfg->subclass; in pci_fill_devinfo()
790 devlist_entry->conf.pc_progif = cfg->progif; in pci_fill_devinfo()
791 devlist_entry->conf.pc_revid = cfg->revid; in pci_fill_devinfo()
803 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ in pci_ea_fill_info()
804 cfg->ea.ea_location + (n), w) in pci_ea_fill_info()
814 if (cfg->ea.ea_location == 0) in pci_ea_fill_info()
817 STAILQ_INIT(&cfg->ea.ea_entries); in pci_ea_fill_info()
827 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) in pci_ea_fill_info()
832 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; in pci_ea_fill_info()
844 eae->eae_flags = val; in pci_ea_fill_info()
845 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; in pci_ea_fill_info()
860 eae->eae_base = base; in pci_ea_fill_info()
861 eae->eae_max_offset = max_offset; in pci_ea_fill_info()
863 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); in pci_ea_fill_info()
867 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, in pci_ea_fill_info()
868 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); in pci_ea_fill_info()
877 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) in pci_read_cap()
878 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) in pci_read_cap()
885 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_read_cap()
915 cfg->pp.pp_location = ptr; in pci_read_cap()
916 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); in pci_read_cap()
919 /* Determine HT-specific capability type. */ in pci_read_cap()
923 cfg->ht.ht_slave = ptr; in pci_read_cap()
937 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", in pci_read_cap()
938 cfg->domain, cfg->bus, in pci_read_cap()
939 cfg->slot, cfg->func, in pci_read_cap()
944 cfg->ht.ht_msimap = ptr; in pci_read_cap()
945 cfg->ht.ht_msictrl = val; in pci_read_cap()
946 cfg->ht.ht_msiaddr = addr; in pci_read_cap()
952 cfg->msi.msi_location = ptr; in pci_read_cap()
953 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); in pci_read_cap()
955 case PCIY_MSIX: /* PCI MSI-X */ in pci_read_cap()
956 cfg->msix.msix_location = ptr; in pci_read_cap()
957 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); in pci_read_cap()
959 cfg->msix.msix_table_bar = PCIR_BAR(val & in pci_read_cap()
961 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; in pci_read_cap()
963 cfg->msix.msix_pba_bar = PCIR_BAR(val & in pci_read_cap()
965 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; in pci_read_cap()
968 cfg->vpd.vpd_reg = ptr; in pci_read_cap()
972 if ((cfg->hdrtype & PCIM_HDRTYPE) == in pci_read_cap()
975 cfg->subvendor = val & 0xffff; in pci_read_cap()
976 cfg->subdevice = val >> 16; in pci_read_cap()
979 case PCIY_PCIX: /* PCI-X */ in pci_read_cap()
981 * Assume we have a PCI-X chipset if we have in pci_read_cap()
982 * at least one PCI-PCI bridge with a PCI-X in pci_read_cap()
984 * PCI-express or HT chipsets might match on in pci_read_cap()
987 if ((cfg->hdrtype & PCIM_HDRTYPE) == in pci_read_cap()
990 cfg->pcix.pcix_location = ptr; in pci_read_cap()
992 case PCIY_EXPRESS: /* PCI-express */ in pci_read_cap()
994 * Assume we have a PCI-express chipset if we have in pci_read_cap()
995 * at least one PCI-express device. in pci_read_cap()
998 cfg->pcie.pcie_location = ptr; in pci_read_cap()
1000 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; in pci_read_cap()
1003 cfg->ea.ea_location = ptr; in pci_read_cap()
1014 * slaves. PCI-PCI bridges have their windows enabled via in pci_read_cap()
1017 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && in pci_read_cap()
1018 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { in pci_read_cap()
1021 cfg->domain, cfg->bus, cfg->slot, cfg->func); in pci_read_cap()
1022 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; in pci_read_cap()
1023 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, in pci_read_cap()
1043 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); in pci_read_vpd_reg()
1045 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { in pci_read_vpd_reg()
1046 if (--count < 0) in pci_read_vpd_reg()
1050 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); in pci_read_vpd_reg()
1063 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
1064 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
1065 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
1066 if (--count < 0)
1086 /* return 0 and one byte in *data if no read error, -1 else */
1093 if (vrs->bytesinval == 0) { in vpd_nextbyte()
1094 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) in vpd_nextbyte()
1095 return (-1); in vpd_nextbyte()
1096 vrs->val = le32toh(reg); in vpd_nextbyte()
1097 vrs->off += 4; in vpd_nextbyte()
1098 byte = vrs->val & 0xff; in vpd_nextbyte()
1099 vrs->bytesinval = 3; in vpd_nextbyte()
1101 vrs->val = vrs->val >> 8; in vpd_nextbyte()
1102 byte = vrs->val & 0xff; in vpd_nextbyte()
1103 vrs->bytesinval--; in vpd_nextbyte()
1106 vrs->cksum += byte; in vpd_nextbyte()
1111 /* return 0 on match, -1 and "unget" byte on no match */
1118 return (-1); in vpd_expectbyte()
1123 vrs->cksum -= data; in vpd_expectbyte()
1124 vrs->val = (vrs->val << 8) + data; in vpd_expectbyte()
1125 vrs->bytesinval++; in vpd_expectbyte()
1126 return (-1); in vpd_expectbyte()
1129 /* return size if tag matches, -1 on no match, -2 on read error */
1136 return (-1); in vpd_read_tag_size()
1142 return (-2); in vpd_read_tag_size()
1144 return (-2); in vpd_read_tag_size()
1165 /* read VPD keyword and return element size, return -1 on read error */
1172 return (-1); in vpd_read_elem_head()
1174 return (-1); in vpd_read_elem_head()
1176 return (-1); in vpd_read_elem_head()
1210 return (-1); in vpd_read_elem_data()
1226 vrs->cksum -= fixup; in vpd_fixup_cksum()
1229 /* fetch one read-only element and return size of heading + data */
1238 cfg = vrs->cfg; in next_vpd_ro_elem()
1239 vpd = &cfg->vpd; in next_vpd_ro_elem()
1242 return (-1); in next_vpd_ro_elem()
1243 vpd->vpd_ros = alloc_buffer(vpd->vpd_ros, sizeof(*vpd->vpd_ros), vpd->vpd_rocnt); in next_vpd_ro_elem()
1244 vpd_ros = &vpd->vpd_ros[vpd->vpd_rocnt]; in next_vpd_ro_elem()
1245 maxsize -= 3; in next_vpd_ro_elem()
1246 len = vpd_read_elem_data(vrs, vpd_ros->keyword, &vpd_ros->value, maxsize); in next_vpd_ro_elem()
1247 if (vpd_ros->value == NULL) in next_vpd_ro_elem()
1248 return (-1); in next_vpd_ro_elem()
1249 vpd_ros->len = len; in next_vpd_ro_elem()
1250 if (vpd_ros->keyword[0] == 'R' && vpd_ros->keyword[1] == 'V') { in next_vpd_ro_elem()
1251 vpd_fixup_cksum(vrs, vpd_ros->value, len); in next_vpd_ro_elem()
1252 if (vrs->cksum != 0) { in next_vpd_ro_elem()
1254 "invalid VPD checksum %#hhx\n", vrs->cksum); in next_vpd_ro_elem()
1255 return (-1); in next_vpd_ro_elem()
1258 vpd->vpd_rocnt++; in next_vpd_ro_elem()
1272 cfg = vrs->cfg; in next_vpd_rw_elem()
1273 vpd = &cfg->vpd; in next_vpd_rw_elem()
1276 return (-1); in next_vpd_rw_elem()
1277 vpd->vpd_w = alloc_buffer(vpd->vpd_w, sizeof(*vpd->vpd_w), vpd->vpd_wcnt); in next_vpd_rw_elem()
1278 if (vpd->vpd_w == NULL) { in next_vpd_rw_elem()
1280 return (-1); in next_vpd_rw_elem()
1282 vpd_w = &vpd->vpd_w[vpd->vpd_wcnt]; in next_vpd_rw_elem()
1283 maxsize -= 3; in next_vpd_rw_elem()
1284 vpd_w->start = vrs->off + 3 - vrs->bytesinval; in next_vpd_rw_elem()
1285 len = vpd_read_elem_data(vrs, vpd_w->keyword, &vpd_w->value, maxsize); in next_vpd_rw_elem()
1286 if (vpd_w->value == NULL) in next_vpd_rw_elem()
1287 return (-1); in next_vpd_rw_elem()
1288 vpd_w->len = len; in next_vpd_rw_elem()
1289 vpd->vpd_wcnt++; in next_vpd_rw_elem()
1300 free(vpd->vpd_ident, M_DEVBUF); in vpd_free()
1301 for (i = 0; i < vpd->vpd_rocnt; i++) in vpd_free()
1302 free(vpd->vpd_ros[i].value, M_DEVBUF); in vpd_free()
1303 free(vpd->vpd_ros, M_DEVBUF); in vpd_free()
1304 vpd->vpd_rocnt = 0; in vpd_free()
1305 for (i = 0; i < vpd->vpd_wcnt; i++) in vpd_free()
1306 free(vpd->vpd_w[i].value, M_DEVBUF); in vpd_free()
1307 free(vpd->vpd_w, M_DEVBUF); in vpd_free()
1308 vpd->vpd_wcnt = 0; in vpd_free()
1330 /* read VPD ident element - mandatory */ in pci_parse_vpd()
1336 cfg->vpd.vpd_ident = vpd_read_value(&vrs, size); in pci_parse_vpd()
1337 if (cfg->vpd.vpd_ident == NULL) { in pci_parse_vpd()
1342 /* read VPD RO elements - mandatory */ in pci_parse_vpd()
1345 pci_printf(cfg, "no read-only VPD data found\n"); in pci_parse_vpd()
1351 pci_printf(cfg, "error accessing read-only VPD data\n"); in pci_parse_vpd()
1352 return (-1); in pci_parse_vpd()
1354 size -= elem_size; in pci_parse_vpd()
1358 return (-1); in pci_parse_vpd()
1360 /* read VPD RW elements - optional */ in pci_parse_vpd()
1362 if (size == -2) in pci_parse_vpd()
1363 return (-1); in pci_parse_vpd()
1368 return (-1); in pci_parse_vpd()
1370 size -= elem_size; in pci_parse_vpd()
1373 /* read empty END tag - mandatory */ in pci_parse_vpd()
1388 vpd_free(&cfg->vpd); in pci_read_vpd()
1389 cfg->vpd.vpd_cached = 1; in pci_read_vpd()
1398 pcicfgregs *cfg = &dinfo->cfg; in pci_get_vpd_ident_method()
1400 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_get_vpd_ident_method()
1403 *identptr = cfg->vpd.vpd_ident; in pci_get_vpd_ident_method()
1416 pcicfgregs *cfg = &dinfo->cfg; in pci_get_vpd_readonly_method()
1419 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_get_vpd_readonly_method()
1422 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) in pci_get_vpd_readonly_method()
1423 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, in pci_get_vpd_readonly_method()
1424 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { in pci_get_vpd_readonly_method()
1425 *vptr = cfg->vpd.vpd_ros[i].value; in pci_get_vpd_readonly_method()
1437 pcicfgregs *cfg = &dinfo->cfg; in pci_fetch_vpd_list()
1439 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) in pci_fetch_vpd_list()
1441 return (&cfg->vpd); in pci_fetch_vpd_list()
1535 pcicfgregs *cfg = &dinfo->cfg; in pci_find_cap_method()
1550 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_find_cap_method()
1569 for (cnt = 0; ptr != 0 && cnt < (PCIE_REGMAX - 0x40) / 2; cnt++) { in pci_find_cap_method()
1618 pcicfgregs *cfg = &dinfo->cfg; in pci_find_extcap_method()
1622 /* Only supported for PCI-express devices. */ in pci_find_extcap_method()
1623 if (cfg->pcie.pcie_location == 0) in pci_find_extcap_method()
1655 pcicfgregs *cfg = &dinfo->cfg; in pci_find_next_extcap_method()
1659 /* Only supported for PCI-express devices. */ in pci_find_next_extcap_method()
1660 if (cfg->pcie.pcie_location == 0) in pci_find_next_extcap_method()
1681 * Support for MSI-X message interrupts.
1687 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_write_msix_entry()
1690 KASSERT(msix->msix_table_len > index, ("bogus index")); in pci_write_msix_entry()
1691 offset = msix->msix_table_offset + index * 16; in pci_write_msix_entry()
1692 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); in pci_write_msix_entry()
1693 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); in pci_write_msix_entry()
1694 bus_write_4(msix->msix_table_res, offset + 8, data); in pci_write_msix_entry()
1704 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_enable_msix_method()
1715 msix->msix_location + PCIR_MSIX_CTRL, in pci_enable_msix_method()
1716 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); in pci_enable_msix_method()
1721 /* Enable MSI -> HT mapping. */ in pci_enable_msix_method()
1729 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_mask_msix()
1732 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); in pci_mask_msix()
1733 offset = msix->msix_table_offset + index * 16 + 12; in pci_mask_msix()
1734 val = bus_read_4(msix->msix_table_res, offset); in pci_mask_msix()
1741 bus_write_4(msix->msix_table_res, offset, val); in pci_mask_msix()
1748 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_unmask_msix()
1751 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); in pci_unmask_msix()
1752 offset = msix->msix_table_offset + index * 16 + 12; in pci_unmask_msix()
1753 val = bus_read_4(msix->msix_table_res, offset); in pci_unmask_msix()
1760 bus_write_4(msix->msix_table_res, offset, val); in pci_unmask_msix()
1767 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_pending_msix()
1770 KASSERT(msix->msix_table_len > index, ("bogus index")); in pci_pending_msix()
1771 offset = msix->msix_pba_offset + (index / 32) * 4; in pci_pending_msix()
1773 return (bus_read_4(msix->msix_pba_res, offset) & bit); in pci_pending_msix()
1777 * Restore MSI-X registers and table during resume. If MSI-X is
1778 * enabled then walk the virtual table to restore the actual MSI-X
1785 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_resume_msix()
1790 if (msix->msix_alloc > 0) { in pci_resume_msix()
1791 msgnum = PCI_MSIX_MSGNUM(msix->msix_ctrl); in pci_resume_msix()
1798 for (i = 0; i < msix->msix_table_len; i++) { in pci_resume_msix()
1799 mte = &msix->msix_table[i]; in pci_resume_msix()
1800 if (mte->mte_vector == 0 || mte->mte_handlers == 0) in pci_resume_msix()
1802 mv = &msix->msix_vectors[mte->mte_vector - 1]; in pci_resume_msix()
1803 pci_write_msix_entry(dev, i, mv->mv_address, in pci_resume_msix()
1804 mv->mv_data); in pci_resume_msix()
1808 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, in pci_resume_msix()
1809 msix->msix_ctrl, 2); in pci_resume_msix()
1813 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1821 pcicfgregs *cfg = &dinfo->cfg; in pci_alloc_msix_method()
1832 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_alloc_msix_method()
1833 if (rle != NULL && rle->res != NULL) in pci_alloc_msix_method()
1837 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) in pci_alloc_msix_method()
1840 /* If MSI-X is blacklisted for this system, fail. */ in pci_alloc_msix_method()
1844 /* MSI-X capability present? */ in pci_alloc_msix_method()
1845 if (cfg->msix.msix_location == 0 || !pci_do_msix) in pci_alloc_msix_method()
1849 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, in pci_alloc_msix_method()
1850 cfg->msix.msix_table_bar); in pci_alloc_msix_method()
1851 if (rle == NULL || rle->res == NULL || in pci_alloc_msix_method()
1852 !(rman_get_flags(rle->res) & RF_ACTIVE)) in pci_alloc_msix_method()
1854 cfg->msix.msix_table_res = rle->res; in pci_alloc_msix_method()
1855 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { in pci_alloc_msix_method()
1856 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, in pci_alloc_msix_method()
1857 cfg->msix.msix_pba_bar); in pci_alloc_msix_method()
1858 if (rle == NULL || rle->res == NULL || in pci_alloc_msix_method()
1859 !(rman_get_flags(rle->res) & RF_ACTIVE)) in pci_alloc_msix_method()
1862 cfg->msix.msix_pba_res = rle->res; in pci_alloc_msix_method()
1864 ctrl = pci_read_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, in pci_alloc_msix_method()
1869 "attempting to allocate %d MSI-X vectors (%d supported)\n", in pci_alloc_msix_method()
1880 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, in pci_alloc_msix_method()
1886 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); in pci_alloc_msix_method()
1888 device_printf(child, "using IRQ %ju for MSI-X\n", in pci_alloc_msix_method()
1889 rle->start); in pci_alloc_msix_method()
1898 device_printf(child, "using IRQs %ju", rle->start); in pci_alloc_msix_method()
1899 irq = rle->start; in pci_alloc_msix_method()
1902 rle = resource_list_find(&dinfo->resources, in pci_alloc_msix_method()
1906 if (rle->start == irq + 1) { in pci_alloc_msix_method()
1914 printf("-%d", irq); in pci_alloc_msix_method()
1919 printf(",%ju", rle->start); in pci_alloc_msix_method()
1920 irq = rle->start; in pci_alloc_msix_method()
1925 printf("-%d", irq); in pci_alloc_msix_method()
1926 printf(" for MSI-X\n"); in pci_alloc_msix_method()
1934 cfg->msix.msix_ctrl = ctrl; in pci_alloc_msix_method()
1939 cfg->msix.msix_vectors = mallocarray(actual, sizeof(struct msix_vector), in pci_alloc_msix_method()
1941 cfg->msix.msix_table = mallocarray(actual, in pci_alloc_msix_method()
1944 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_alloc_msix_method()
1945 cfg->msix.msix_vectors[i].mv_irq = rle->start; in pci_alloc_msix_method()
1946 cfg->msix.msix_table[i].mte_vector = i + 1; in pci_alloc_msix_method()
1949 /* Update control register to enable MSI-X. */ in pci_alloc_msix_method()
1951 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, in pci_alloc_msix_method()
1953 cfg->msix.msix_ctrl = ctrl; in pci_alloc_msix_method()
1956 cfg->msix.msix_alloc = actual; in pci_alloc_msix_method()
1957 cfg->msix.msix_table_len = actual; in pci_alloc_msix_method()
1964 * resources consecutively to the first N messages in the MSI-X table.
1967 * populate the MSI-X table sparsely. This method allows the driver
1973 * maps directly to the MSI-X table in that index 0 in the array
1974 * specifies the vector for the first message in the MSI-X table, etc.
1981 * On successful return, each message with a non-zero vector will have
1987 * For example, suppose a driver has a MSI-X table with 6 messages and
1991 * have an MSI-X table of ABC--- (where - means no vector assigned).
1993 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1998 * at MSI-X table index X - 1 and will only be valid if a vector is
2006 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_remap_msix_method()
2013 * table can't be bigger than the actual MSI-X table in the in pci_remap_msix_method()
2016 if (count < 1 || count > PCI_MSIX_MSGNUM(msix->msix_ctrl)) in pci_remap_msix_method()
2021 if (vectors[i] > msix->msix_alloc) in pci_remap_msix_method()
2029 used = mallocarray(msix->msix_alloc, sizeof(*used), M_DEVBUF, M_WAITOK | in pci_remap_msix_method()
2033 used[vectors[i] - 1] = true; in pci_remap_msix_method()
2034 for (i = 0; i < msix->msix_alloc - 1; i++) in pci_remap_msix_method()
2045 for (i = 0; i < msix->msix_table_len; i++) { in pci_remap_msix_method()
2046 if (msix->msix_table[i].mte_vector == 0) in pci_remap_msix_method()
2048 if (msix->msix_table[i].mte_handlers > 0) { in pci_remap_msix_method()
2052 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_remap_msix_method()
2054 if (rle->res != NULL) { in pci_remap_msix_method()
2061 for (i = 0; i < msix->msix_table_len; i++) { in pci_remap_msix_method()
2062 if (msix->msix_table[i].mte_vector == 0) in pci_remap_msix_method()
2064 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_remap_msix_method()
2071 free(msix->msix_table, M_DEVBUF); in pci_remap_msix_method()
2072 msix->msix_table = mallocarray(count, sizeof(struct msix_table_entry), in pci_remap_msix_method()
2075 msix->msix_table[i].mte_vector = vectors[i]; in pci_remap_msix_method()
2076 msix->msix_table_len = count; in pci_remap_msix_method()
2079 j = msix->msix_alloc - 1; in pci_remap_msix_method()
2085 msix->msix_vectors[j].mv_irq); in pci_remap_msix_method()
2086 j--; in pci_remap_msix_method()
2090 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * in pci_remap_msix_method()
2092 free(msix->msix_vectors, M_DEVBUF); in pci_remap_msix_method()
2093 msix->msix_vectors = vec; in pci_remap_msix_method()
2094 msix->msix_alloc = j + 1; in pci_remap_msix_method()
2102 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; in pci_remap_msix_method()
2103 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, in pci_remap_msix_method()
2108 device_printf(child, "Remapped MSI-X IRQs as: "); in pci_remap_msix_method()
2113 printf("---"); in pci_remap_msix_method()
2116 msix->msix_vectors[vectors[i] - 1].mv_irq); in pci_remap_msix_method()
2128 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_release_msix()
2133 if (msix->msix_alloc == 0) in pci_release_msix()
2137 for (i = 0; i < msix->msix_table_len; i++) { in pci_release_msix()
2138 if (msix->msix_table[i].mte_vector == 0) in pci_release_msix()
2140 if (msix->msix_table[i].mte_handlers > 0) in pci_release_msix()
2142 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msix()
2144 if (rle->res != NULL) in pci_release_msix()
2148 /* Update control register to disable MSI-X. */ in pci_release_msix()
2149 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; in pci_release_msix()
2150 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, in pci_release_msix()
2151 msix->msix_ctrl, 2); in pci_release_msix()
2154 for (i = 0; i < msix->msix_table_len; i++) { in pci_release_msix()
2155 if (msix->msix_table[i].mte_vector == 0) in pci_release_msix()
2157 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msix()
2159 free(msix->msix_table, M_DEVBUF); in pci_release_msix()
2160 msix->msix_table_len = 0; in pci_release_msix()
2163 for (i = 0; i < msix->msix_alloc; i++) in pci_release_msix()
2165 msix->msix_vectors[i].mv_irq); in pci_release_msix()
2166 free(msix->msix_vectors, M_DEVBUF); in pci_release_msix()
2167 msix->msix_alloc = 0; in pci_release_msix()
2172 * Return the max supported MSI-X messages this device supports.
2181 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_count_method()
2184 if (pci_do_msix && msix->msix_location != 0) { in pci_msix_count_method()
2185 ctrl = pci_read_config(child, msix->msix_location + in pci_msix_count_method()
2196 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_pba_bar_method()
2198 if (pci_do_msix && msix->msix_location != 0) in pci_msix_pba_bar_method()
2199 return (msix->msix_pba_bar); in pci_msix_pba_bar_method()
2200 return (-1); in pci_msix_pba_bar_method()
2207 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_msix_table_bar_method()
2209 if (pci_do_msix && msix->msix_location != 0) in pci_msix_table_bar_method()
2210 return (msix->msix_table_bar); in pci_msix_table_bar_method()
2211 return (-1); in pci_msix_table_bar_method()
2221 struct pcicfg_ht *ht = &dinfo->cfg.ht; in pci_ht_map_msi()
2223 if (!ht->ht_msimap) in pci_ht_map_msi()
2226 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && in pci_ht_map_msi()
2227 ht->ht_msiaddr >> 20 == addr >> 20) { in pci_ht_map_msi()
2228 /* Enable MSI -> HT mapping. */ in pci_ht_map_msi()
2229 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; in pci_ht_map_msi()
2230 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, in pci_ht_map_msi()
2231 ht->ht_msictrl, 2); in pci_ht_map_msi()
2234 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { in pci_ht_map_msi()
2235 /* Disable MSI -> HT mapping. */ in pci_ht_map_msi()
2236 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; in pci_ht_map_msi()
2237 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, in pci_ht_map_msi()
2238 ht->ht_msictrl, 2); in pci_ht_map_msi()
2249 cap = dinfo->cfg.pcie.pcie_location; in pci_get_relaxed_ordering_enabled()
2264 cap = dinfo->cfg.pcie.pcie_location; in pci_get_max_payload()
2280 cap = dinfo->cfg.pcie.pcie_location; in pci_get_max_read_req()
2296 cap = dinfo->cfg.pcie.pcie_location; in pci_set_max_read_req()
2303 size = (1 << (fls(size) - 1)); in pci_set_max_read_req()
2306 val |= (fls(size) - 8) << 12; in pci_set_max_read_req()
2317 cap = dinfo->cfg.pcie.pcie_location; in pcie_read_config()
2333 cap = dinfo->cfg.pcie.pcie_location; in pcie_write_config()
2340 * Adjusts a PCI-e capability register by clearing the bits in mask
2354 cap = dinfo->cfg.pcie.pcie_location; in pcie_adjust_config()
2376 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_enable_msi_method()
2379 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, in pci_enable_msi_method()
2381 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { in pci_enable_msi_method()
2382 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, in pci_enable_msi_method()
2384 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, in pci_enable_msi_method()
2387 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, in pci_enable_msi_method()
2391 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; in pci_enable_msi_method()
2392 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_enable_msi_method()
2393 msi->msi_ctrl, 2); in pci_enable_msi_method()
2395 /* Enable MSI -> HT mapping. */ in pci_enable_msi_method()
2403 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_disable_msi_method()
2405 /* Disable MSI -> HT mapping. */ in pci_disable_msi_method()
2409 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; in pci_disable_msi_method()
2410 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_disable_msi_method()
2411 msi->msi_ctrl, 2); in pci_disable_msi_method()
2423 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_resume_msi()
2427 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { in pci_resume_msi()
2428 address = msi->msi_addr; in pci_resume_msi()
2429 data = msi->msi_data; in pci_resume_msi()
2430 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, in pci_resume_msi()
2432 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { in pci_resume_msi()
2433 pci_write_config(dev, msi->msi_location + in pci_resume_msi()
2435 pci_write_config(dev, msi->msi_location + in pci_resume_msi()
2438 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, in pci_resume_msi()
2441 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, in pci_resume_msi()
2449 pcicfgregs *cfg = &dinfo->cfg; in pci_remap_intr_method()
2463 if (cfg->msi.msi_alloc > 0) { in pci_remap_intr_method()
2465 if (cfg->msi.msi_handlers == 0) in pci_remap_intr_method()
2467 for (i = 0; i < cfg->msi.msi_alloc; i++) { in pci_remap_intr_method()
2468 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, in pci_remap_intr_method()
2470 if (rle->start == irq) { in pci_remap_intr_method()
2476 dinfo->cfg.msi.msi_addr = addr; in pci_remap_intr_method()
2477 dinfo->cfg.msi.msi_data = data; in pci_remap_intr_method()
2486 * For MSI-X, we check to see if we have this IRQ. If we do, in pci_remap_intr_method()
2490 if (cfg->msix.msix_alloc > 0) { in pci_remap_intr_method()
2493 for (i = 0; i < cfg->msix.msix_alloc; i++) { in pci_remap_intr_method()
2494 mv = &cfg->msix.msix_vectors[i]; in pci_remap_intr_method()
2495 if (mv->mv_irq == irq) { in pci_remap_intr_method()
2500 mv->mv_address = addr; in pci_remap_intr_method()
2501 mv->mv_data = data; in pci_remap_intr_method()
2502 for (j = 0; j < cfg->msix.msix_table_len; j++) { in pci_remap_intr_method()
2503 mte = &cfg->msix.msix_table[j]; in pci_remap_intr_method()
2504 if (mte->mte_vector != i + 1) in pci_remap_intr_method()
2506 if (mte->mte_handlers == 0) in pci_remap_intr_method()
2538 * host-PCI bridge at device 0:0:0. In the future, it may become
2550 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ in pci_msi_blacklisted()
2572 * Returns true if the specified device is blacklisted because MSI-X
2574 * MSI-X doesn't either.
2590 * Determine if MSI-X is blacklisted globally on this system. If MSI
2591 * is blacklisted, assume that MSI-X is as well. Check for additional
2592 * chipsets where MSI works but MSI-X does not.
2619 pcicfgregs *cfg = &dinfo->cfg; in pci_alloc_msi_method()
2630 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_alloc_msi_method()
2631 if (rle != NULL && rle->res != NULL) in pci_alloc_msi_method()
2635 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) in pci_alloc_msi_method()
2643 if (cfg->msi.msi_location == 0 || !pci_do_msi) in pci_alloc_msi_method()
2646 ctrl = pci_read_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 2); in pci_alloc_msi_method()
2682 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, in pci_alloc_msi_method()
2700 if (irqs[i] == irqs[i - 1] + 1) { in pci_alloc_msi_method()
2707 printf("-%d", irqs[i - 1]); in pci_alloc_msi_method()
2717 printf("-%d", irqs[actual - 1]); in pci_alloc_msi_method()
2724 ctrl |= (ffs(actual) - 1) << 4; in pci_alloc_msi_method()
2725 cfg->msi.msi_ctrl = ctrl; in pci_alloc_msi_method()
2726 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); in pci_alloc_msi_method()
2729 cfg->msi.msi_alloc = actual; in pci_alloc_msi_method()
2730 cfg->msi.msi_handlers = 0; in pci_alloc_msi_method()
2740 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_release_msi_method()
2745 /* Try MSI-X first. */ in pci_release_msi_method()
2751 if (msi->msi_alloc == 0) in pci_release_msi_method()
2753 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); in pci_release_msi_method()
2756 if (msi->msi_handlers > 0) in pci_release_msi_method()
2758 for (i = 0; i < msi->msi_alloc; i++) { in pci_release_msi_method()
2759 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msi_method()
2761 if (rle->res != NULL) in pci_release_msi_method()
2763 irqs[i] = rle->start; in pci_release_msi_method()
2767 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), in pci_release_msi_method()
2769 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; in pci_release_msi_method()
2770 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_release_msi_method()
2771 msi->msi_ctrl, 2); in pci_release_msi_method()
2774 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); in pci_release_msi_method()
2775 for (i = 0; i < msi->msi_alloc; i++) in pci_release_msi_method()
2776 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); in pci_release_msi_method()
2779 msi->msi_alloc = 0; in pci_release_msi_method()
2780 msi->msi_addr = 0; in pci_release_msi_method()
2781 msi->msi_data = 0; in pci_release_msi_method()
2795 struct pcicfg_msi *msi = &dinfo->cfg.msi; in pci_msi_count_method()
2798 if (pci_do_msi && msi->msi_location != 0) { in pci_msi_count_method()
2799 ctrl = pci_read_config(child, msi->msi_location + PCIR_MSI_CTRL, in pci_msi_count_method()
2816 if (dinfo->cfg.vpd.vpd_reg) in pci_freecfg()
2817 vpd_free(&dinfo->cfg.vpd); in pci_freecfg()
2819 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { in pci_freecfg()
2829 pci_numdevs--; in pci_freecfg()
2840 pcicfgregs *cfg = &dinfo->cfg; in pci_set_powerstate_method()
2844 if (cfg->pp.pp_location == 0) in pci_set_powerstate_method()
2850 * behavior when going from D3 -> D3. in pci_set_powerstate_method()
2875 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + in pci_set_powerstate_method()
2882 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) in pci_set_powerstate_method()
2887 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) in pci_set_powerstate_method()
2902 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_location + PCIR_POWER_STATUS, in pci_set_powerstate_method()
2913 pcicfgregs *cfg = &dinfo->cfg; in pci_get_powerstate_method()
2917 if (cfg->pp.pp_location != 0) { in pci_get_powerstate_method()
2918 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + in pci_get_powerstate_method()
2949 pcicfgregs *cfg = &dinfo->cfg; in pci_clear_pme()
2952 if (cfg->pp.pp_location != 0) { in pci_clear_pme()
2953 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + in pci_clear_pme()
2957 pci_write_config(dev, dinfo->cfg.pp.pp_location + in pci_clear_pme()
2967 pcicfgregs *cfg = &dinfo->cfg; in pci_enable_pme()
2970 if (cfg->pp.pp_location != 0) { in pci_enable_pme()
2971 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + in pci_enable_pme()
2974 pci_write_config(dev, dinfo->cfg.pp.pp_location + in pci_enable_pme()
2983 pcicfgregs *cfg = &dinfo->cfg; in pci_has_pm()
2985 return (cfg->pp.pp_location != 0); in pci_has_pm()
3065 * New style pci driver. Parent device is either a pci-host-bridge or a
3066 * pci-pci-bridge. Both kinds are represented by instances of pcib.
3074 pcicfgregs *cfg = &dinfo->cfg; in pci_print_verbose()
3076 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", in pci_print_verbose()
3077 cfg->vendor, cfg->device, cfg->revid); in pci_print_verbose()
3079 cfg->domain, cfg->bus, cfg->slot, cfg->func); in pci_print_verbose()
3080 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", in pci_print_verbose()
3081 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, in pci_print_verbose()
3082 cfg->mfdev); in pci_print_verbose()
3084 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); in pci_print_verbose()
3086 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, in pci_print_verbose()
3087 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); in pci_print_verbose()
3088 if (cfg->intpin > 0) in pci_print_verbose()
3090 cfg->intpin +'a' -1, cfg->intline); in pci_print_verbose()
3091 if (cfg->pp.pp_location) { in pci_print_verbose()
3094 status = pci_read_config(cfg->dev, cfg->pp.pp_location + in pci_print_verbose()
3097 cfg->pp.pp_cap & PCIM_PCAP_SPEC, in pci_print_verbose()
3098 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", in pci_print_verbose()
3099 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", in pci_print_verbose()
3102 if (cfg->msi.msi_location) { in pci_print_verbose()
3105 ctrl = cfg->msi.msi_ctrl; in pci_print_verbose()
3112 if (cfg->msix.msix_location) { in pci_print_verbose()
3115 msgnum = PCI_MSIX_MSGNUM(cfg->msix.msix_ctrl); in pci_print_verbose()
3116 printf("\tMSI-X supports %d message%s ", in pci_print_verbose()
3118 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) in pci_print_verbose()
3120 cfg->msix.msix_table_bar); in pci_print_verbose()
3123 cfg->msix.msix_table_bar, in pci_print_verbose()
3124 cfg->msix.msix_pba_bar); in pci_print_verbose()
3151 * The device ROM BAR is special. It is always a 32-bit in pci_read_bar()
3156 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { in pci_read_bar()
3189 * and combines the result into a 64-bit value." (section 6.2.5.1) in pci_read_bar()
3204 * the BAR of the low-level console device and when booting verbose, in pci_read_bar()
3224 /* The device ROM BAR is always a 32-bit memory BAR. */ in pci_write_bar()
3226 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) in pci_write_bar()
3229 ln2range = pci_maprange(pm->pm_value); in pci_write_bar()
3230 pci_write_config(dev, pm->pm_reg, base, 4); in pci_write_bar()
3232 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); in pci_write_bar()
3233 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); in pci_write_bar()
3235 pm->pm_value |= (pci_addr_t)pci_read_config(dev, in pci_write_bar()
3236 pm->pm_reg + 4, 4) << 32; in pci_write_bar()
3246 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { in pci_find_bar()
3247 if (pm->pm_reg == reg) in pci_find_bar()
3259 return (STAILQ_FIRST(&dinfo->cfg.maps)); in pci_first_bar()
3275 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && in pci_bar_enabled()
3276 !(pm->pm_value & PCIM_BIOS_ENABLE)) in pci_bar_enabled()
3279 if ((dinfo->cfg.flags & PCICFG_VF) != 0) { in pci_bar_enabled()
3282 iov = dinfo->cfg.iov; in pci_bar_enabled()
3283 cmd = pci_read_config(iov->iov_pf, in pci_bar_enabled()
3284 iov->iov_pos + PCIR_SRIOV_CTL, 2); in pci_bar_enabled()
3289 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) in pci_bar_enabled()
3303 pm->pm_reg = reg; in pci_add_bar()
3304 pm->pm_value = value; in pci_add_bar()
3305 pm->pm_size = size; in pci_add_bar()
3306 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { in pci_add_bar()
3307 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", in pci_add_bar()
3310 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) in pci_add_bar()
3314 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); in pci_add_bar()
3316 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); in pci_add_bar()
3328 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { in pci_restore_bars()
3329 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) in pci_restore_bars()
3332 ln2range = pci_maprange(pm->pm_value); in pci_restore_bars()
3333 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); in pci_restore_bars()
3335 pci_write_config(dev, pm->pm_reg + 4, in pci_restore_bars()
3336 pm->pm_value >> 32, 4); in pci_restore_bars()
3361 maprange = pci_maprange(pm->pm_value); in pci_add_map()
3465 end = base + count - 1; in pci_add_map()
3579 pcicfgregs *cfg = &dinfo->cfg; in pci_assign_interrupt()
3584 if (cfg->intpin == 0) in pci_assign_interrupt()
3591 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); in pci_assign_interrupt()
3603 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) in pci_assign_interrupt()
3606 irq = cfg->intline; in pci_assign_interrupt()
3614 if (irq != cfg->intline) { in pci_assign_interrupt()
3615 cfg->intline = irq; in pci_assign_interrupt()
3620 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); in pci_assign_interrupt()
3670 * that the BIOS won't touch the keyboard anymore if it is connected in uhci_early_takeover()
3704 /* Synchronise with the BIOS if it owns the controller. */ in ehci_early_takeover()
3760 eec = -1; in xhci_early_takeover()
3762 /* Synchronise with the BIOS if it owns the controller. */ in xhci_early_takeover()
3811 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_reserve_secbus()
3876 count = end - start + 1; in pci_reserve_secbus()
3918 cfg = &dinfo->cfg; in pci_alloc_secbus()
3919 rl = &dinfo->resources; in pci_alloc_secbus()
3920 switch (cfg->hdrtype & PCIM_HDRTYPE) { in pci_alloc_secbus()
3967 iov = dinfo->cfg.iov; in pci_ea_bei_to_rid()
3969 iov_pos = iov->iov_pos; in pci_ea_bei_to_rid()
3987 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + in pci_ea_bei_to_rid()
3991 return (-1); in pci_ea_bei_to_rid()
4002 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { in pci_ea_is_enabled()
4003 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) in pci_ea_is_enabled()
4004 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); in pci_ea_is_enabled()
4025 rl = &dinfo->resources; in pci_add_resources_ea()
4029 iov = dinfo->cfg.iov; in pci_add_resources_ea()
4032 if (dinfo->cfg.ea.ea_location == 0) in pci_add_resources_ea()
4035 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { in pci_add_resources_ea()
4037 * TODO: Ignore EA-BAR if is not enabled. in pci_add_resources_ea()
4042 * a legacy-BAR mechanism. in pci_add_resources_ea()
4044 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) in pci_add_resources_ea()
4047 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { in pci_add_resources_ea()
4066 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || in pci_add_resources_ea()
4067 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) in pci_add_resources_ea()
4074 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || in pci_add_resources_ea()
4075 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && in pci_add_resources_ea()
4076 (ea->eae_bei != PCIM_EA_BEI_ROM)) in pci_add_resources_ea()
4080 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); in pci_add_resources_ea()
4089 start = ea->eae_base; in pci_add_resources_ea()
4090 count = ea->eae_max_offset + 1; in pci_add_resources_ea()
4093 count = count * iov->iov_num_vfs; in pci_add_resources_ea()
4095 end = start + count - 1; in pci_add_resources_ea()
4110 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); in pci_add_resources_ea()
4112 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); in pci_add_resources_ea()
4118 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); in pci_add_resources_ea()
4139 cfg = &dinfo->cfg; in pci_add_resources()
4140 rl = &dinfo->resources; in pci_add_resources()
4141 devid = (cfg->device << 16) | cfg->vendor; in pci_add_resources()
4154 for (i = 0; i < cfg->nummaps;) { in pci_add_resources()
4166 for (q = &pci_quirks[0]; q->devid != 0; q++) in pci_add_resources()
4167 if (q->devid == devid && in pci_add_resources()
4168 q->type == PCI_QUIRK_UNMAP_REG && in pci_add_resources()
4169 q->arg1 == PCIR_BAR(i)) in pci_add_resources()
4171 if (q->devid != 0) { in pci_add_resources()
4182 for (q = &pci_quirks[0]; q->devid != 0; q++) in pci_add_resources()
4183 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) in pci_add_resources()
4184 pci_add_map(bus, dev, q->arg1, rl, force, 0); in pci_add_resources()
4186 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline) && in pci_add_resources()
4189 * Try to re-route interrupts. Sometimes the BIOS or in pci_add_resources()
4191 * If the re-route fails, then just stick with what we in pci_add_resources()
4248 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); in pci_add_children()
4387 vf_dinfo->cfg.flags |= PCICFG_VF; in pci_add_iov_child()
4390 return (vf_dinfo->cfg.dev); in pci_add_iov_child()
4412 if (dinfo->cfg.pcie.pcie_location == 0) in pcie_setup_mps()
4448 if (dinfo->cfg.pcie.pcie_location != 0 && in pci_add_child_clear_aer()
4449 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { in pci_add_child_clear_aer()
4450 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4454 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4461 pci_printf(&dinfo->cfg, in pci_add_child_clear_aer()
4462 "clearing AER UC 0x%08x -> 0x%08x\n", in pci_add_child_clear_aer()
4490 pci_printf(&dinfo->cfg, in pci_add_child_clear_aer()
4491 "clearing AER COR 0x%08x -> 0x%08x\n", in pci_add_child_clear_aer()
4507 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4511 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pci_add_child_clear_aer()
4521 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY); in pci_add_child()
4523 resource_list_init(&dinfo->resources); in pci_add_child()
4531 pci_child_added(dinfo->cfg.dev); in pci_add_child()
4536 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); in pci_add_child()
4566 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, in pci_attach_common()
4568 if (sc->sc_bus == NULL) { in pci_attach_common()
4575 sc->sc_dma_tag = bus_get_dma_tag(dev); in pci_attach_common()
4611 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); in pci_detach()
4694 * as MSI/MSI-X interrupts are never shared. in pci_suspend_child()
4696 rle = resource_list_find(&dinfo->resources, in pci_suspend_child()
4698 if (rle != NULL && rle->res != NULL) in pci_suspend_child()
4699 (void)bus_suspend_intr(child, rle->res); in pci_suspend_child()
4728 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); in pci_resume_child()
4729 if (rle != NULL && rle->res != NULL) in pci_resume_child()
4730 (void)bus_resume_intr(child, rle->res); in pci_resume_child()
4816 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); in pci_driver_added()
4853 * Check to see if the interrupt is MSI or MSI-X. in pci_setup_intr()
4860 if (dinfo->cfg.msi.msi_alloc > 0) { in pci_setup_intr()
4861 if (dinfo->cfg.msi.msi_addr == 0) { in pci_setup_intr()
4862 KASSERT(dinfo->cfg.msi.msi_handlers == 0, in pci_setup_intr()
4868 dinfo->cfg.msi.msi_addr = addr; in pci_setup_intr()
4869 dinfo->cfg.msi.msi_data = data; in pci_setup_intr()
4871 if (dinfo->cfg.msi.msi_handlers == 0) in pci_setup_intr()
4872 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, in pci_setup_intr()
4873 dinfo->cfg.msi.msi_data); in pci_setup_intr()
4874 dinfo->cfg.msi.msi_handlers++; in pci_setup_intr()
4876 KASSERT(dinfo->cfg.msix.msix_alloc > 0, in pci_setup_intr()
4877 ("No MSI or MSI-X interrupts allocated")); in pci_setup_intr()
4878 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, in pci_setup_intr()
4879 ("MSI-X index too high")); in pci_setup_intr()
4880 mte = &dinfo->cfg.msix.msix_table[rid - 1]; in pci_setup_intr()
4881 KASSERT(mte->mte_vector != 0, ("no message vector")); in pci_setup_intr()
4882 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; in pci_setup_intr()
4883 KASSERT(mv->mv_irq == rman_get_start(irq), in pci_setup_intr()
4885 if (mv->mv_address == 0) { in pci_setup_intr()
4886 KASSERT(mte->mte_handlers == 0, in pci_setup_intr()
4887 ("MSI-X table entry has handlers, but vector not mapped")); in pci_setup_intr()
4892 mv->mv_address = addr; in pci_setup_intr()
4893 mv->mv_data = data; in pci_setup_intr()
4903 mte->mte_handlers++; in pci_setup_intr()
4904 if (mte->mte_handlers == 1) { in pci_setup_intr()
4905 pci_enable_msix(child, rid - 1, mv->mv_address, in pci_setup_intr()
4906 mv->mv_data); in pci_setup_intr()
4907 pci_unmask_msix(child, rid - 1); in pci_setup_intr()
4912 * Make sure that INTx is disabled if we are using MSI/MSI-X, in pci_setup_intr()
4914 * in which case we "enable" INTx so MSI/MSI-X actually works. in pci_setup_intr()
4954 * Check to see if the interrupt is MSI or MSI-X. If so, in pci_teardown_intr()
4956 * MSI-X message, or disable MSI messages if the count in pci_teardown_intr()
4960 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); in pci_teardown_intr()
4961 if (rle->res != irq) in pci_teardown_intr()
4963 if (dinfo->cfg.msi.msi_alloc > 0) { in pci_teardown_intr()
4964 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, in pci_teardown_intr()
4965 ("MSI-X index too high")); in pci_teardown_intr()
4966 if (dinfo->cfg.msi.msi_handlers == 0) in pci_teardown_intr()
4968 dinfo->cfg.msi.msi_handlers--; in pci_teardown_intr()
4969 if (dinfo->cfg.msi.msi_handlers == 0) in pci_teardown_intr()
4972 KASSERT(dinfo->cfg.msix.msix_alloc > 0, in pci_teardown_intr()
4973 ("No MSI or MSI-X interrupts allocated")); in pci_teardown_intr()
4974 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, in pci_teardown_intr()
4975 ("MSI-X index too high")); in pci_teardown_intr()
4976 mte = &dinfo->cfg.msix.msix_table[rid - 1]; in pci_teardown_intr()
4977 if (mte->mte_handlers == 0) in pci_teardown_intr()
4979 mte->mte_handlers--; in pci_teardown_intr()
4980 if (mte->mte_handlers == 0) in pci_teardown_intr()
4981 pci_mask_msix(child, rid - 1); in pci_teardown_intr()
4987 ("%s: generic teardown failed for MSI/MSI-X", __func__)); in pci_teardown_intr()
4999 rl = &dinfo->resources; in pci_print_child()
5025 {PCIC_OLD, -1, 1, "old"},
5026 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"},
5027 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"},
5028 {PCIC_STORAGE, -1, 1, "mass storage"},
5038 {PCIC_NETWORK, -1, 1, "network"},
5044 {PCIC_DISPLAY, -1, 1, "display"},
5048 {PCIC_MULTIMEDIA, -1, 1, "multimedia"},
5053 {PCIC_MEMORY, -1, 1, "memory"},
5056 {PCIC_BRIDGE, -1, 1, "bridge"},
5057 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"},
5058 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"},
5059 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"},
5060 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"},
5061 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"},
5062 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"},
5063 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"},
5064 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"},
5065 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"},
5066 {PCIC_SIMPLECOMM, -1, 1, "simple comms"},
5071 {PCIC_BASEPERIPH, -1, 0, "base peripheral"},
5072 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"},
5073 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"},
5076 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"},
5077 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"},
5079 {PCIC_INPUTDEV, -1, 1, "input device"},
5080 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"},
5085 {PCIC_DOCKING, -1, 1, "docking station"},
5086 {PCIC_PROCESSOR, -1, 1, "processor"},
5087 {PCIC_SERIALBUS, -1, 1, "serial bus"},
5094 {PCIC_WIRELESS, -1, 1, "wireless controller"},
5098 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"},
5100 {PCIC_SATCOM, -1, 1, "satellite communication"},
5105 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"},
5108 {PCIC_DASP, -1, 0, "dasp"},
5113 {PCIC_INSTRUMENT, -1, 0, "non-essential instrumentation"},
5140 if (pci_nomatch_tab[i].subclass == -1) { in pci_probe_nomatch()
5171 rl = &dinfo->resources; in pci_child_detached()
5179 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); in pci_child_detached()
5180 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { in pci_child_detached()
5181 if (dinfo->cfg.msi.msi_alloc != 0) in pci_child_detached()
5182 pci_printf(&dinfo->cfg, "Device leaked %d MSI " in pci_child_detached()
5183 "vectors\n", dinfo->cfg.msi.msi_alloc); in pci_child_detached()
5185 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " in pci_child_detached()
5186 "vectors\n", dinfo->cfg.msix.msix_alloc); in pci_child_detached()
5190 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); in pci_child_detached()
5192 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); in pci_child_detached()
5194 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); in pci_child_detached()
5212 * - devices cannot be listed without a corresponding VENDOR line.
5221 * is set to -1. Returns nonzero at the end of the database.
5233 *device = -1; in pci_describe_parse_line()
5234 *vendor = -1; in pci_describe_parse_line()
5237 left = pci_vendordata_size - (cp - pci_vendordata); in pci_describe_parse_line()
5255 left--; in pci_describe_parse_line()
5259 left--; in pci_describe_parse_line()
5265 left--; in pci_describe_parse_line()
5306 if (vendor != -1) { in pci_describe_device()
5333 cfg = &dinfo->cfg; in pci_read_ivar()
5344 *result = cfg->subvendor; in pci_read_ivar()
5347 *result = cfg->subdevice; in pci_read_ivar()
5350 *result = cfg->vendor; in pci_read_ivar()
5353 *result = cfg->device; in pci_read_ivar()
5356 *result = (cfg->device << 16) | cfg->vendor; in pci_read_ivar()
5359 *result = cfg->baseclass; in pci_read_ivar()
5362 *result = cfg->subclass; in pci_read_ivar()
5365 *result = cfg->progif; in pci_read_ivar()
5368 *result = cfg->revid; in pci_read_ivar()
5371 *result = cfg->intpin; in pci_read_ivar()
5374 *result = cfg->intline; in pci_read_ivar()
5377 *result = cfg->domain; in pci_read_ivar()
5380 *result = cfg->bus; in pci_read_ivar()
5383 *result = cfg->slot; in pci_read_ivar()
5386 *result = cfg->func; in pci_read_ivar()
5389 *result = cfg->cmdreg; in pci_read_ivar()
5392 *result = cfg->cachelnsz; in pci_read_ivar()
5395 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { in pci_read_ivar()
5396 *result = -1; in pci_read_ivar()
5399 *result = cfg->mingnt; in pci_read_ivar()
5402 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { in pci_read_ivar()
5403 *result = -1; in pci_read_ivar()
5406 *result = cfg->maxlat; in pci_read_ivar()
5409 *result = cfg->lattimer; in pci_read_ivar()
5426 dinfo->cfg.intpin = value; in pci_write_ivar()
5480 if (dinfo->cfg.dev) in DB_SHOW_COMMAND_FLAGS()
5481 name = device_get_name(dinfo->cfg.dev); in DB_SHOW_COMMAND_FLAGS()
5483 p = &dinfo->conf; in DB_SHOW_COMMAND_FLAGS()
5487 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : in DB_SHOW_COMMAND_FLAGS()
5489 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, in DB_SHOW_COMMAND_FLAGS()
5490 p->pc_sel.pc_func, (p->pc_class << 16) | in DB_SHOW_COMMAND_FLAGS()
5491 (p->pc_subclass << 8) | p->pc_progif, in DB_SHOW_COMMAND_FLAGS()
5492 (p->pc_subdevice << 16) | p->pc_subvendor, in DB_SHOW_COMMAND_FLAGS()
5493 (p->pc_device << 16) | p->pc_vendor, in DB_SHOW_COMMAND_FLAGS()
5494 p->pc_revid, p->pc_hdr); in DB_SHOW_COMMAND_FLAGS()
5505 struct resource_list *rl = &dinfo->resources; in pci_reserve_map()
5521 mapsize = pm->pm_size; in pci_reserve_map()
5522 map = pm->pm_value; in pci_reserve_map()
5538 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) in pci_reserve_map()
5547 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { in pci_reserve_map()
5628 rl = &dinfo->resources; in pci_alloc_multi_resource()
5629 cfg = &dinfo->cfg; in pci_alloc_multi_resource()
5639 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || in pci_alloc_multi_resource()
5640 cfg->msix.msix_alloc > 0)) in pci_alloc_multi_resource()
5648 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && in pci_alloc_multi_resource()
5649 (cfg->intpin != 0)) in pci_alloc_multi_resource()
5655 * PCI-PCI bridge I/O window resources are not BARs. in pci_alloc_multi_resource()
5659 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { in pci_alloc_multi_resource()
5699 if (dinfo->cfg.flags & PCICFG_VF) { in pci_alloc_resource()
5728 cfg = &dinfo->cfg; in pci_release_resource()
5731 if (cfg->flags & PCICFG_VF) { in pci_release_resource()
5745 * PCI-PCI bridge I/O window resources are not BARs. For in pci_release_resource()
5748 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && in pci_release_resource()
5759 rl = &dinfo->resources; in pci_release_resource()
5774 if (dinfo->cfg.flags & PCICFG_VF) { in pci_activate_resource()
5797 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) in pci_activate_resource()
5822 if (dinfo->cfg.flags & PCICFG_VF) { in pci_deactivate_resource()
5844 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) in pci_deactivate_resource()
5862 if (dinfo->cfg.flags & PCICFG_VF) { in pci_adjust_resource()
5891 if (dinfo->cfg.flags & PCICFG_VF) { in pci_map_resource()
5919 if (dinfo->cfg.flags & PCICFG_VF) { in pci_unmap_resource()
5943 rl = &dinfo->resources; in pci_child_deleted()
5957 if (rle->res) { in pci_child_deleted()
5958 if (rman_get_flags(rle->res) & RF_ACTIVE || in pci_child_deleted()
5959 resource_list_busy(rl, rle->type, rle->rid)) { in pci_child_deleted()
5960 pci_printf(&dinfo->cfg, in pci_child_deleted()
5963 rle->type, rle->rid, in pci_child_deleted()
5964 rman_get_start(rle->res)); in pci_child_deleted()
5965 bus_release_resource(child, rle->type, rle->rid, in pci_child_deleted()
5966 rle->res); in pci_child_deleted()
5968 resource_list_unreserve(rl, dev, child, rle->type, in pci_child_deleted()
5969 rle->rid); in pci_child_deleted()
5988 rl = &dinfo->resources; in pci_delete_resource()
5993 if (rle->res) { in pci_delete_resource()
5994 if (rman_get_flags(rle->res) & RF_ACTIVE || in pci_delete_resource()
5999 type, rid, rman_get_start(rle->res)); in pci_delete_resource()
6012 return (&dinfo->resources); in pci_get_resource_list()
6029 tag = sc->sc_dma_tag; in pci_get_dma_tag()
6039 return (sc->sc_dma_tag); in pci_get_dma_tag()
6047 pcicfgregs *cfg = &dinfo->cfg; in pci_read_config_method()
6051 * SR-IOV VFs don't implement the VID or DID registers, so we have to in pci_read_config_method()
6054 if (cfg->flags & PCICFG_VF) { in pci_read_config_method()
6058 return (cfg->device << 16 | cfg->vendor); in pci_read_config_method()
6060 return (cfg->vendor); in pci_read_config_method()
6062 return (cfg->vendor & 0xff); in pci_read_config_method()
6068 /* Note that an unaligned 4-byte read is an error. */ in pci_read_config_method()
6070 return (cfg->device); in pci_read_config_method()
6072 return (cfg->device & 0xff); in pci_read_config_method()
6081 cfg->bus, cfg->slot, cfg->func, reg, width)); in pci_read_config_method()
6089 pcicfgregs *cfg = &dinfo->cfg; in pci_write_config_method()
6092 cfg->bus, cfg->slot, cfg->func, reg, val, width); in pci_write_config_method()
6112 cfg = &dinfo->cfg; in pci_child_pnpinfo_method()
6114 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, in pci_child_pnpinfo_method()
6115 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, in pci_child_pnpinfo_method()
6116 cfg->progif); in pci_child_pnpinfo_method()
6142 pcicfgregs *cfg = &dinfo->cfg; in pci_assign_interrupt_method()
6145 cfg->intpin)); in pci_assign_interrupt_method()
6159 * Accept pciconf-style selectors of either pciD:B:S:F or in pci_lookup()
6231 cfg = &dinfo->cfg.pcie; in pci_cfg_restore_pcie()
6232 pos = cfg->pcie_location; in pci_cfg_restore_pcie()
6234 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; in pci_cfg_restore_pcie()
6236 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); in pci_cfg_restore_pcie()
6238 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6239 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || in pci_cfg_restore_pcie()
6240 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) in pci_cfg_restore_pcie()
6241 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); in pci_cfg_restore_pcie()
6243 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6244 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && in pci_cfg_restore_pcie()
6245 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) in pci_cfg_restore_pcie()
6246 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); in pci_cfg_restore_pcie()
6248 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_restore_pcie()
6249 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) in pci_cfg_restore_pcie()
6250 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); in pci_cfg_restore_pcie()
6253 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); in pci_cfg_restore_pcie()
6254 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); in pci_cfg_restore_pcie()
6255 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); in pci_cfg_restore_pcie()
6263 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, in pci_cfg_restore_pcix()
6264 dinfo->cfg.pcix.pcix_command, 2); in pci_cfg_restore_pcix()
6281 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); in pci_cfg_restore()
6282 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); in pci_cfg_restore()
6283 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); in pci_cfg_restore()
6284 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); in pci_cfg_restore()
6285 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); in pci_cfg_restore()
6286 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); in pci_cfg_restore()
6287 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { in pci_cfg_restore()
6289 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); in pci_cfg_restore()
6290 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); in pci_cfg_restore()
6294 dinfo->cfg.bridge.br_seclat, 1); in pci_cfg_restore()
6296 dinfo->cfg.bridge.br_subbus, 1); in pci_cfg_restore()
6298 dinfo->cfg.bridge.br_secbus, 1); in pci_cfg_restore()
6300 dinfo->cfg.bridge.br_pribus, 1); in pci_cfg_restore()
6302 dinfo->cfg.bridge.br_control, 2); in pci_cfg_restore()
6306 dinfo->cfg.bridge.br_seclat, 1); in pci_cfg_restore()
6308 dinfo->cfg.bridge.br_subbus, 1); in pci_cfg_restore()
6310 dinfo->cfg.bridge.br_secbus, 1); in pci_cfg_restore()
6312 dinfo->cfg.bridge.br_pribus, 1); in pci_cfg_restore()
6314 dinfo->cfg.bridge.br_control, 2); in pci_cfg_restore()
6319 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) in pci_cfg_restore()
6320 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); in pci_cfg_restore()
6323 * Restore extended capabilities for PCI-Express and PCI-X in pci_cfg_restore()
6325 if (dinfo->cfg.pcie.pcie_location != 0) in pci_cfg_restore()
6327 if (dinfo->cfg.pcix.pcix_location != 0) in pci_cfg_restore()
6330 /* Restore MSI and MSI-X configurations if they are present. */ in pci_cfg_restore()
6331 if (dinfo->cfg.msi.msi_location != 0) in pci_cfg_restore()
6333 if (dinfo->cfg.msix.msix_location != 0) in pci_cfg_restore()
6337 if (dinfo->cfg.iov != NULL) in pci_cfg_restore()
6349 cfg = &dinfo->cfg.pcie; in pci_cfg_save_pcie()
6350 pos = cfg->pcie_location; in pci_cfg_save_pcie()
6352 cfg->pcie_flags = RREG(PCIER_FLAGS); in pci_cfg_save_pcie()
6354 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; in pci_cfg_save_pcie()
6356 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); in pci_cfg_save_pcie()
6358 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6359 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || in pci_cfg_save_pcie()
6360 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) in pci_cfg_save_pcie()
6361 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); in pci_cfg_save_pcie()
6363 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6364 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && in pci_cfg_save_pcie()
6365 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) in pci_cfg_save_pcie()
6366 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); in pci_cfg_save_pcie()
6368 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || in pci_cfg_save_pcie()
6369 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) in pci_cfg_save_pcie()
6370 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); in pci_cfg_save_pcie()
6373 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); in pci_cfg_save_pcie()
6374 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); in pci_cfg_save_pcie()
6375 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); in pci_cfg_save_pcie()
6383 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, in pci_cfg_save_pcix()
6384 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); in pci_cfg_save_pcix()
6400 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); in pci_cfg_save()
6401 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); in pci_cfg_save()
6402 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); in pci_cfg_save()
6403 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); in pci_cfg_save()
6404 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); in pci_cfg_save()
6405 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); in pci_cfg_save()
6406 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); in pci_cfg_save()
6407 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); in pci_cfg_save()
6408 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); in pci_cfg_save()
6409 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); in pci_cfg_save()
6410 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); in pci_cfg_save()
6411 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { in pci_cfg_save()
6413 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); in pci_cfg_save()
6414 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); in pci_cfg_save()
6415 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); in pci_cfg_save()
6416 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); in pci_cfg_save()
6419 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, in pci_cfg_save()
6421 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, in pci_cfg_save()
6423 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, in pci_cfg_save()
6425 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, in pci_cfg_save()
6427 dinfo->cfg.bridge.br_control = pci_read_config(dev, in pci_cfg_save()
6431 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, in pci_cfg_save()
6433 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, in pci_cfg_save()
6435 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, in pci_cfg_save()
6437 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, in pci_cfg_save()
6439 dinfo->cfg.bridge.br_control = pci_read_config(dev, in pci_cfg_save()
6441 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); in pci_cfg_save()
6442 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); in pci_cfg_save()
6446 if (dinfo->cfg.pcie.pcie_location != 0) in pci_cfg_save()
6449 if (dinfo->cfg.pcix.pcix_location != 0) in pci_cfg_save()
6453 if (dinfo->cfg.iov != NULL) in pci_cfg_save()
6532 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); in pci_find_pcie_root_port()
6535 * Walk the bridge hierarchy until we find a PCI-e root in pci_find_pcie_root_port()
6536 * port or a non-PCI device. in pci_find_pcie_root_port()
6549 * PCI-PCI bridge. in pci_find_pcie_root_port()
6555 if (dinfo->cfg.pcie.pcie_location != 0 && in pci_find_pcie_root_port()
6556 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) in pci_find_pcie_root_port()
6564 * Wait for pending transactions to complete on a PCI-express function.
6570 * exceeded. If dev is not a PCI-express function, this returns true.
6579 cap = dinfo->cfg.pcie.pcie_location; in pcie_wait_for_pending_transactions()
6591 max_delay -= 100; in pcie_wait_for_pending_transactions()
6606 * For non-PCI-express functions this returns 0.
6614 cap = dinfo->cfg.pcie.pcie_location; in pcie_get_max_completion_timeout()
6623 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || in pcie_get_max_completion_timeout()
6663 s = "Uncorrectable (Non-Fatal)"; in pcie_apei_error()
6699 if (dinfo->cfg.pcie.pcie_location != 0) { in pcie_apei_error()
6700 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in pcie_apei_error()
6705 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in pcie_apei_error()
6720 * If dev is not a PCI-express function or does not support FLR, this
6725 * PCI-standard registers via pci_save_state() and
6736 cap = dinfo->cfg.pcie.pcie_location; in pcie_flr()
6747 * which will re-enable busmastering. in pcie_flr()
6756 pci_printf(&dinfo->cfg, in pcie_flr()
6761 * Extend the post-FLR delay to cover the maximum in pcie_flr()
6782 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); in pcie_flr()
6787 * Attempt a power-management reset by cycling the device in/out of D3
6887 while (nelt-- > 0) { in pci_match_device()
6889 if (id->match_flag_vendor) in pci_match_device()
6890 match &= vendor == id->vendor; in pci_match_device()
6891 if (id->match_flag_device) in pci_match_device()
6892 match &= device == id->device; in pci_match_device()
6893 if (id->match_flag_subvendor) in pci_match_device()
6894 match &= subvendor == id->subvendor; in pci_match_device()
6895 if (id->match_flag_subdevice) in pci_match_device()
6896 match &= subdevice == id->subdevice; in pci_match_device()
6897 if (id->match_flag_class) in pci_match_device()
6898 match &= class == id->class_id; in pci_match_device()
6899 if (id->match_flag_subclass) in pci_match_device()
6900 match &= subclass == id->subclass; in pci_match_device()
6901 if (id->match_flag_revid) in pci_match_device()
6902 match &= revid == id->revid; in pci_match_device()
6916 dev = dinfo->cfg.dev; in pci_print_faulted_dev_name()
6917 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, in pci_print_faulted_dev_name()
6918 dinfo->cfg.slot, dinfo->cfg.func); in pci_print_faulted_dev_name()
6934 dev = dinfo->cfg.dev; in pci_print_faulted_dev()
6943 if (dinfo->cfg.pcie.pcie_location != 0) { in pci_print_faulted_dev()
6945 dinfo->cfg.pcie.pcie_location + in pci_print_faulted_dev()
6953 dinfo->cfg.pcie.pcie_location + in pci_print_faulted_dev()
6997 dev = dinfo->cfg.dev; in db_clear_pcie_errors()
6998 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + in db_clear_pcie_errors()
7000 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + in db_clear_pcie_errors()
7020 dev = dinfo->cfg.dev; in DB_COMMAND_FLAGS()
7029 if (dinfo->cfg.pcie.pcie_location != 0) in DB_COMMAND_FLAGS()