Lines Matching +full:wakeup +full:- +full:latency
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2000-2001 Jonathan Chen All rights reserved.
5 * Copyright (c) 2002-2004 M. Warner Losh <imp@FreeBSD.org>
30 /*-
65 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS
127 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X},
128 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X},
129 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X},
131 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX},
132 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX},
133 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX},
134 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX},
135 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX},
136 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X},
137 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X},
138 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X},
139 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX},
140 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX},
141 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX},
142 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX},
143 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX},
144 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/
145 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX},
146 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX},
147 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX},
148 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX},
149 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX},
150 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX},
151 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX},
152 {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX},
153 {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX},
154 {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX},
155 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX},
156 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX},
157 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
158 {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
159 {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
160 {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
163 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX},
164 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX},
165 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX},
166 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX},
167 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX},
168 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX},
171 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X},
172 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X},
173 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X},
174 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X},
175 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X},
176 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X},
179 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95},
180 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95},
181 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97},
182 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97},
185 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS},
186 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS},
187 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS},
190 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO},
191 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO},
192 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO},
193 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO},
194 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO},
195 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO},
196 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO},
197 {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO},
198 {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO},
199 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO},
200 {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO},
201 {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO},
204 {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS},
219 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp)
222 *namep = ycp->yc_name;
223 return (ycp->yc_chiptype);
253 device_set_desc(brdev, "PCI-CardBus Bridge");
286 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF);
287 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL);
288 sc->dev = brdev;
289 sc->cbdev = NULL;
290 sc->domain = pci_get_domain(brdev);
291 sc->pribus = pcib_get_bus(parent);
292 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1);
293 pcib_setup_secbus(brdev, &sc->bus, 1);
294 SLIST_INIT(&sc->rl);
297 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid,
299 if (!sc->base_res) {
301 mtx_destroy(&sc->mtx);
305 rman_get_start(sc->base_res)));
309 sc->cbdev = device_add_child(brdev, "cardbus", DEVICE_UNIT_ANY);
310 if (sc->cbdev == NULL)
312 else if (device_probe_and_attach(sc->cbdev) != 0)
315 sc->bst = rman_get_bustag(sc->base_res);
316 sc->bsh = rman_get_bushandle(sc->base_res);
317 exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET);
318 sc->exca.flags |= EXCA_HAS_MEMREG_WIN;
319 sc->exca.chipset = EXCA_CARDBUS;
320 sc->chipinit = cbb_chipinit;
321 sc->chipinit(sc);
327 CTLFLAG_RD, &sc->domain, 0, "Domain number");
329 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
331 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
333 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
336 CTLFLAG_RD, &sc->subbus, 0, "Memory window open");
338 CTLFLAG_RD, &sc->subbus, 0, "Prefetch memory window open");
340 CTLFLAG_RD, &sc->subbus, 0, "io range 1 open");
342 CTLFLAG_RD, &sc->subbus, 0, "io range 2 open");
347 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid,
349 if (sc->irq_res == NULL) {
354 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE,
355 cbb_pci_filt, NULL, sc, &sc->intrhand)) {
360 /* reset 16-bit pcmcia bus */
361 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET);
376 if (kproc_create(cbb_event_thread, sc, &sc->event_thread, 0, 0,
381 sc->sc_root_token = root_mount_hold(device_get_nameunit(sc->dev));
384 if (sc->irq_res)
385 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res);
386 if (sc->base_res) {
388 sc->base_res);
390 mtx_destroy(&sc->mtx);
402 pcib_free_secbus(brdev, &sc->bus);
411 /* Set CardBus latency timer */
412 if (pci_read_config(sc->dev, PCIR_SECLAT_2, 1) < 0x20)
413 pci_write_config(sc->dev, PCIR_SECLAT_2, 0x20, 1);
415 /* Set PCI latency timer */
416 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20)
417 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1);
420 pci_enable_busmaster(sc->dev);
421 pci_enable_io(sc->dev, SYS_RES_IOPORT);
422 pci_enable_io(sc->dev, SYS_RES_MEMORY);
425 switch (sc->chipset) {
427 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL,
432 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4);
437 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL,
448 switch (sc->chipset) {
456 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL,
460 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL,
490 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4);
491 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4);
498 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4);
508 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4);
534 reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C);
537 exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg);
543 pci_write_config(sc->dev, TOPIC97_ZV_CONTROL, 0, 1);
549 PCI_MASK_CONFIG(sc->dev, TOPIC_INTCTRL,
555 exca_setb(&sc->exca, EXCA_TOPIC97_CTRL,
562 PCI_MASK_CONFIG(sc->dev, TOPIC95_SOCKETCTRL,
576 pci_write_config(sc->dev, TOPIC_SLOTCTRL,
587 PCI_MASK2_CONFIG(sc->dev, TOPIC_CDC,
598 exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE);
599 exca_putb(&sc->exca, EXCA_CSC_INTR, 0);
604 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4);
605 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4);
606 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4);
607 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4);
608 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4);
609 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4);
610 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4);
611 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4);
619 return (rman_get_start(sc->irq_res));
631 sc->cardok = 0;
638 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET);
647 exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0);
678 * fired. So now we only read it for 16-bit cards, and we only claim
680 * the next step would be to read this if we have a 16-bit card *OR*
684 * in one place and a double wakeup would be benign there.
686 if (sc->flags & CBB_16BIT_CARD) {
687 csc = exca_getb(&sc->exca, EXCA_CSC);
689 atomic_add_int(&sc->powerintr, 1);
690 wakeup((void *)&sc->powerintr);
723 sc->cardok = 0;
725 wakeup(&sc->intrhand);
730 * Wakeup anybody waiting for a power interrupt. We have to
736 atomic_add_int(&sc->powerintr, 1);
737 wakeup((void *)&sc->powerintr);
759 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end,
773 if (!rman_is_region_manager(r, &sc->bus.rman))
788 if (!rman_is_region_manager(r, &sc->bus.rman))
841 sc->cardok = 0; /* Card is bogus now */
861 * command register and BARs, but cbb-specific registers are
864 sc->chipinit(sc);
866 /* reset interrupt -- Do we really need to do this? */
873 /* Signal the thread to wakeup. */
874 wakeup(&sc->intrhand);
904 /* 16-bit card interface */
929 nitems(yc_chipsets) - 1);