Lines Matching +full:timing +full:- +full:0

1 #-
33 # Dallas Semiconductor 1-Wire bus Link Layer (owll)
36 # 1-Wire protocol specification.
39 # Note: 1-Wire is a registered trademark of Maxim Integrated Products, Inc.
43 # SoCs have a 1-Wire controller with more smarts or hardware offload.
44 # Maxim datasheets also describe how to use UARTs to generate timing,
45 # as well as both usb and i2c 1-Wire controllers.
47 # Chapter 4 has all the electrical timing diagrams that make up the link
60 #	0 <= tRELEASE < 45us		0 <= tRELEASE < 4us
74 # Note: This is the polling / busy-wait interface. An interrupt-based interface
75 # may be different. But an interrupt-based, non-blocking interface can be tricky.
80 # WRITE-ONE (see above for timings) From Figure 4-1 AN-937
82 #		       |<---------tSLOT---->|<-tREC->|
87 #      	       	       |<-tLOW1->|     |  |
88 #    		       |<------15us--->|  |
89 #                      |<--------60us---->|
94 	struct ow_timing *timing;	/* timing values */
98 # WRITE-ZERO (see above for timings) From Figure 4-2 AN-937
100 #		       |<---------tSLOT------>|<-tREC->|
105 #      	       	       |<--15us->|     |    |
106 #      	       	       |<------60us--->|    |
107 #                      |<-------tLOW0------>|
112 	struct ow_timing *timing;	/* timing values */
115 # READ-DATA (see above for timings) From Figure 4-3 AN-937
117 #		       |<---------tSLOT------>|<-tREC->|
123 #      	       	       |<------tRDV---->|   |
124 #                                     ->|   |<-tRELEASE
126 # r -- allowed to pull high via the resistor when slave writes a 1-bit
130 	struct ow_timing *timing;	/* timing values */
134 # RESET AND PRESENCE PULSE (see above for timings) From Figure 4-4 AN-937
136 #				    |<---------tRSTH------------>|
141 #      	       	   |<----tRSTL--->| |  	   |<-tPDL---->|
142 #		   |   	       	->| |<-tR  |	       |
154 	struct ow_timing *timing;	/* timing values */
155 	int		*present;	/* 0 = slave 1 = no slave -1 = bus error */