Lines Matching refs:mw
173 struct ntb_plx_mw_info *mw; in ntb_plx_init() local
180 mw = &sc->mw_info[sc->b2b_mw]; in ntb_plx_init()
181 if (mw->mw_64bit) { in ntb_plx_init()
183 val64 = 0x2000000000000000 * mw->mw_bar | 0x4; in ntb_plx_init()
188 val = 0x20000000 * mw->mw_bar; in ntb_plx_init()
194 mw = &sc->mw_info[i]; in ntb_plx_init()
195 if (mw->mw_64bit) { in ntb_plx_init()
196 val64 = 0x2000000000000000 * mw->mw_bar; in ntb_plx_init()
197 NTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4, val64); in ntb_plx_init()
198 NTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4 + 4, val64 >> 32); in ntb_plx_init()
200 val = 0x20000000 * mw->mw_bar; in ntb_plx_init()
201 NTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4, val); in ntb_plx_init()
322 struct ntb_plx_mw_info *mw; in ntb_plx_attach() local
361 mw = &sc->mw_info[sc->mw_count]; in ntb_plx_attach()
362 mw->mw_bar = i; in ntb_plx_attach()
363 mw->mw_rid = PCIR_BAR(mw->mw_bar); in ntb_plx_attach()
364 mw->mw_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, in ntb_plx_attach()
365 &mw->mw_rid, RF_ACTIVE); in ntb_plx_attach()
366 if (mw->mw_res == NULL) in ntb_plx_attach()
368 mw->mw_pbase = rman_get_start(mw->mw_res); in ntb_plx_attach()
369 mw->mw_size = rman_get_size(mw->mw_res); in ntb_plx_attach()
370 mw->mw_vbase = rman_get_virtual(mw->mw_res); in ntb_plx_attach()
372 mw->splits[j].mw_map_mode = VM_MEMATTR_UNCACHEABLE; in ntb_plx_attach()
376 val = pci_read_config(dev, PCIR_BAR(mw->mw_bar), 4); in ntb_plx_attach()
378 mw->mw_64bit = 1; in ntb_plx_attach()
406 mw = &sc->mw_info[sc->b2b_mw]; in ntb_plx_attach()
407 if (mw->mw_size >= 2 * 1024 * 1024) in ntb_plx_attach()
408 sc->b2b_off = mw->mw_size / 2; in ntb_plx_attach()
482 struct ntb_plx_mw_info *mw; in ntb_plx_detach() local
493 mw = &sc->mw_info[i]; in ntb_plx_detach()
494 bus_release_resource(dev, SYS_RES_MEMORY, mw->mw_rid, in ntb_plx_detach()
495 mw->mw_res); in ntb_plx_detach()
642 struct ntb_plx_mw_info *mw; in ntb_plx_mw_get_range() local
655 mw = &sc->mw_info[mw_idx]; in ntb_plx_mw_get_range()
656 split = (mw->mw_bar == 2) ? sc->split : 0; in ntb_plx_mw_get_range()
657 ss = (mw->mw_size - off) >> split; in ntb_plx_mw_get_range()
661 *base = mw->mw_pbase + off + ss * sp; in ntb_plx_mw_get_range()
663 *vbase = mw->mw_vbase + off + ss * sp; in ntb_plx_mw_get_range()
675 if (sc->alut && mw->mw_bar == 2) in ntb_plx_mw_get_range()
676 *align = (mw->mw_size - off) / 128 / sc->alut; in ntb_plx_mw_get_range()
678 *align = mw->mw_size - off; in ntb_plx_mw_get_range()
690 if (sc->alut && mw->mw_bar == 2) in ntb_plx_mw_get_range()
691 *align_size = (mw->mw_size - off) / 128 / sc->alut; in ntb_plx_mw_get_range()
693 *align_size = (mw->mw_size - off) / 2; in ntb_plx_mw_get_range()
695 *align_size = mw->mw_size - off; in ntb_plx_mw_get_range()
700 *plimit = mw->mw_64bit ? BUS_SPACE_MAXADDR : in ntb_plx_mw_get_range()
709 struct ntb_plx_mw_info *mw; in ntb_plx_mw_set_trans_internal() local
714 mw = &sc->mw_info[mw_idx]; in ntb_plx_mw_set_trans_internal()
716 split = (mw->mw_bar == 2) ? sc->split : 0; in ntb_plx_mw_set_trans_internal()
720 bsize = mw->mw_size - off; in ntb_plx_mw_set_trans_internal()
722 bsize = mw->splits[0].mw_xlat_size; in ntb_plx_mw_set_trans_internal()
738 if (sc->b2b_mw >= 0 && mw->mw_64bit) { in ntb_plx_mw_set_trans_internal()
743 PNTX_WRITE(sc, 0xe8 + (mw->mw_bar - 2) * 4, val64); in ntb_plx_mw_set_trans_internal()
744 PNTX_WRITE(sc, 0xe8 + (mw->mw_bar - 2) * 4 + 4, val64 >> 32); in ntb_plx_mw_set_trans_internal()
746 val64 = 0x2000000000000000 * mw->mw_bar + off; in ntb_plx_mw_set_trans_internal()
747 PNTX_WRITE(sc, PCIR_BAR(mw->mw_bar), val64); in ntb_plx_mw_set_trans_internal()
748 PNTX_WRITE(sc, PCIR_BAR(mw->mw_bar) + 4, val64 >> 32); in ntb_plx_mw_set_trans_internal()
753 PNTX_WRITE(sc, 0xe8 + (mw->mw_bar - 2) * 4, val); in ntb_plx_mw_set_trans_internal()
755 val64 = 0x20000000 * mw->mw_bar + off; in ntb_plx_mw_set_trans_internal()
756 PNTX_WRITE(sc, PCIR_BAR(mw->mw_bar), val64); in ntb_plx_mw_set_trans_internal()
760 addr = split ? UINT64_MAX : mw->splits[0].mw_xlat_addr; in ntb_plx_mw_set_trans_internal()
761 if (mw->mw_64bit) { in ntb_plx_mw_set_trans_internal()
762 PNTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4, addr); in ntb_plx_mw_set_trans_internal()
763 PNTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4 + 4, addr >> 32); in ntb_plx_mw_set_trans_internal()
765 PNTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4, addr); in ntb_plx_mw_set_trans_internal()
769 size = split ? 0 : mw->splits[0].mw_xlat_size; in ntb_plx_mw_set_trans_internal()
770 if (sc->alut && mw->mw_bar == 2 && (sc->split > 0 || in ntb_plx_mw_set_trans_internal()
775 eaddr = addr = mw->splits[sp].mw_xlat_addr; in ntb_plx_mw_set_trans_internal()
776 size = mw->splits[sp++].mw_xlat_size; in ntb_plx_mw_set_trans_internal()
790 } else if (sc->alut && mw->mw_bar == 2) in ntb_plx_mw_set_trans_internal()
800 struct ntb_plx_mw_info *mw; in ntb_plx_mw_set_trans() local
806 mw = &sc->mw_info[mw_idx]; in ntb_plx_mw_set_trans()
807 if (!mw->mw_64bit && in ntb_plx_mw_set_trans()
811 mw->splits[sp].mw_xlat_addr = addr; in ntb_plx_mw_set_trans()
812 mw->splits[sp].mw_xlat_size = size; in ntb_plx_mw_set_trans()
827 struct ntb_plx_mw_info *mw; in ntb_plx_mw_get_wc() local
833 mw = &sc->mw_info[mw_idx]; in ntb_plx_mw_get_wc()
834 *mode = mw->splits[sp].mw_map_mode; in ntb_plx_mw_get_wc()
842 struct ntb_plx_mw_info *mw; in ntb_plx_mw_set_wc() local
850 mw = &sc->mw_info[mw_idx]; in ntb_plx_mw_set_wc()
851 if (mw->splits[sp].mw_map_mode == mode) in ntb_plx_mw_set_wc()
861 split = (mw->mw_bar == 2) ? sc->split : 0; in ntb_plx_mw_set_wc()
862 ss = (mw->mw_size - off) >> split; in ntb_plx_mw_set_wc()
863 rc = pmap_change_attr((vm_offset_t)mw->mw_vbase + off + ss * sp, in ntb_plx_mw_set_wc()
866 mw->splits[sp].mw_map_mode = mode; in ntb_plx_mw_set_wc()
1037 struct ntb_plx_mw_info *mw; in ntb_plx_peer_db_addr() local
1042 mw = &sc->mw_info[sc->b2b_mw]; in ntb_plx_peer_db_addr()
1043 *db_addr = (uint64_t)mw->mw_pbase + PLX_NTX_BASE(sc) + 0xc4c; in ntb_plx_peer_db_addr()