Lines Matching +full:0 +full:x38000
108 #define PLX_NT0_BASE 0x3E000
109 #define PLX_NT1_BASE 0x3C000
111 #define PLX_NTX_LINK_OFFSET 0x01000
115 (PLX_NTX_BASE(sc) + ((sc)->link ? PLX_NTX_LINK_OFFSET : 0))
117 (PLX_NTX_BASE(sc) + ((sc)->link ? 0 : PLX_NTX_LINK_OFFSET))
142 #define PLX_PORT_CONTROL(sc) (PLX_STATION_PORT_BASE(sc) + 0x208)
153 case 0x87a010b5: in ntb_plx_probe()
156 case 0x87a110b5: in ntb_plx_probe()
159 case 0x87b010b5: in ntb_plx_probe()
162 case 0x87b110b5: in ntb_plx_probe()
178 if (sc->b2b_mw >= 0) { in ntb_plx_init()
182 PNTX_WRITE(sc, 0xe4, 0x3); /* 64-bit */ in ntb_plx_init()
183 val64 = 0x2000000000000000 * mw->mw_bar | 0x4; in ntb_plx_init()
184 PNTX_WRITE(sc, PCIR_BAR(0), val64); in ntb_plx_init()
185 PNTX_WRITE(sc, PCIR_BAR(0) + 4, val64 >> 32); in ntb_plx_init()
187 PNTX_WRITE(sc, 0xe4, 0x2); /* 32-bit */ in ntb_plx_init()
188 val = 0x20000000 * mw->mw_bar; in ntb_plx_init()
189 PNTX_WRITE(sc, PCIR_BAR(0), val); in ntb_plx_init()
193 for (i = 0; i < sc->mw_count; i++) { in ntb_plx_init()
196 val64 = 0x2000000000000000 * mw->mw_bar; in ntb_plx_init()
197 NTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4, val64); in ntb_plx_init()
198 NTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4 + 4, val64 >> 32); in ntb_plx_init()
200 val = 0x20000000 * mw->mw_bar; in ntb_plx_init()
201 NTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4, val); in ntb_plx_init()
207 PNTX_WRITE(sc, 0xc94, 0); in ntb_plx_init()
210 for (i = 0; i < 32; i += 2) { in ntb_plx_init()
211 PNTX_WRITE(sc, 0xdb4 + i * 2, in ntb_plx_init()
212 0x00010001 | ((i + 1) << 19) | (i << 3)); in ntb_plx_init()
217 * Enable Virtual Interface LUT entry 0 for 0:0.*. in ntb_plx_init()
219 * entries 2-5 for 0/64/128/192:4.* of I/OAT DMA engines. in ntb_plx_init()
223 val = (NTX_READ(sc, 0xc90) << 16) | 0x00010001; in ntb_plx_init()
224 NTX_WRITE(sc, sc->link ? 0xdb4 : 0xd94, val); in ntb_plx_init()
225 NTX_WRITE(sc, sc->link ? 0xdb8 : 0xd98, 0x40210021); in ntb_plx_init()
226 NTX_WRITE(sc, sc->link ? 0xdbc : 0xd9c, 0xc0218021); in ntb_plx_init()
229 for (i = 0; i < sc->mw_count; i++) in ntb_plx_init()
233 if (sc->b2b_mw >= 0) in ntb_plx_init()
236 return (0); in ntb_plx_init()
246 ntb_db_event((device_t)arg, 0); in ntb_plx_isr()
251 val = NTX_READ(sc, 0xfe0); in ntb_plx_isr()
252 if (val == 0) in ntb_plx_isr()
254 NTX_WRITE(sc, 0xfe0, val); in ntb_plx_isr()
282 sc->int_rid = 0; in ntb_plx_setup_intr()
291 if (error != 0) { in ntb_plx_setup_intr()
297 NTX_WRITE(sc, 0xfe0, 0xf); /* Clear link interrupts. */ in ntb_plx_setup_intr()
298 NTX_WRITE(sc, 0xfe4, 0x0); /* Unmask link interrupts. */ in ntb_plx_setup_intr()
300 return (0); in ntb_plx_setup_intr()
309 NTX_WRITE(sc, 0xfe4, 0xf); /* Mask link interrupts. */ in ntb_plx_teardown_intr()
323 int error = 0, i, j; in ntb_plx_attach()
329 val = pci_read_config(dev, 0xc8c, 4); in ntb_plx_attach()
330 sc->ntx = (val & 1) != 0; in ntb_plx_attach()
331 sc->link = (val & 0x80000000) != 0; in ntb_plx_attach()
334 sc->conf_rid = PCIR_BAR(0); in ntb_plx_attach()
349 val = bus_read_4(sc->conf_res, 0x360); in ntb_plx_attach()
350 sc->port = (val >> ((sc->ntx == 0) ? 8 : 16)) & 0x1f; in ntb_plx_attach()
354 sc->alut = (val == 0x3) ? 1 : ((val & (1 << sc->ntx)) ? 2 : 0); in ntb_plx_attach()
359 sc->mw_count = 0; in ntb_plx_attach()
371 for (j = 0; j < PLX_MAX_SPLIT; j++) in ntb_plx_attach()
391 } else if (i == 0) { in ntb_plx_attach()
398 if (sc->mw_count == 0) { in ntb_plx_attach()
410 sc->b2b_off = 0; in ntb_plx_attach()
418 sc->split = 0; in ntb_plx_attach()
419 } else if (sc->split > 0 && sc->alut == 0) { in ntb_plx_attach()
421 sc->split = 0; in ntb_plx_attach()
422 } else if (sc->split > 0 && (sc->mw_count == 0 || sc->mw_info[0].mw_bar != 2)) { in ntb_plx_attach()
424 sc->split = 0; in ntb_plx_attach()
425 } else if (sc->split > 0 && (sc->b2b_mw == 0 && sc->b2b_off == 0)) { in ntb_plx_attach()
427 sc->split = 0; in ntb_plx_attach()
428 } else if (sc->split > 0) { in ntb_plx_attach()
438 sc->spad_offp1 = sc->spad_off1 = PLX_NTX_OUR_BASE(sc) + 0xc6c; in ntb_plx_attach()
439 sc->spad_offp2 = sc->spad_off2 = PLX_PORT_BASE(sc->ntx * 8) + 0x20c; in ntb_plx_attach()
440 if (sc->b2b_mw >= 0) { in ntb_plx_attach()
443 bus_write_4(sc->conf_res, sc->spad_off2, 0x12345678); in ntb_plx_attach()
444 if (bus_read_4(sc->conf_res, sc->spad_off2) == 0x12345678) in ntb_plx_attach()
456 bus_write_4(sc->conf_res, sc->spad_off2, 0x12345678); in ntb_plx_attach()
457 if (bus_read_4(sc->conf_res, sc->spad_off2) == 0x12345678) in ntb_plx_attach()
473 if (error != 0) in ntb_plx_attach()
492 for (i = 0; i < sc->mw_count; i++) { in ntb_plx_detach()
498 return (0); in ntb_plx_detach()
506 return (sc->link ? 1 : 0); in ntb_plx_port_number()
521 if (pidx != 0) in ntb_plx_peer_port_number()
524 return (sc->link ? 0 : 1); in ntb_plx_peer_port_number()
532 peer_port = ntb_plx_peer_port_number(dev, 0); in ntb_plx_peer_port_idx()
536 return (0); in ntb_plx_peer_port_idx()
549 return ((link & PCIEM_LINK_STA_WIDTH) != 0); in ntb_plx_link_is_up()
562 return (0); in ntb_plx_link_enable()
567 if ((val & (1 << (sc->port & 7))) == 0) { in ntb_plx_link_enable()
570 return (0); in ntb_plx_link_enable()
574 return (0); in ntb_plx_link_enable()
585 return (0); in ntb_plx_link_disable()
591 return (0); in ntb_plx_link_disable()
606 return ((val & (1 << (sc->port & 7))) == 0); in ntb_plx_link_enabled()
617 if (sc->b2b_mw >= 0 && sc->b2b_off == 0) in ntb_plx_mw_count()
630 return (0); in ntb_plx_user_mw_to_idx()
632 *sp = 0; in ntb_plx_user_mw_to_idx()
649 off = 0; in ntb_plx_mw_get_range()
651 KASSERT(sc->b2b_off != 0, in ntb_plx_mw_get_range()
656 split = (mw->mw_bar == 2) ? sc->split : 0; in ntb_plx_mw_get_range()
692 else if (sc->b2b_mw >= 0) in ntb_plx_mw_get_range()
702 return (0); in ntb_plx_mw_get_range()
715 off = (mw_idx == sc->b2b_mw) ? sc->b2b_off : 0; in ntb_plx_mw_set_trans_internal()
716 split = (mw->mw_bar == 2) ? sc->split : 0; in ntb_plx_mw_set_trans_internal()
719 if (split || sc->b2b_mw < 0) { in ntb_plx_mw_set_trans_internal()
722 bsize = mw->splits[0].mw_xlat_size; in ntb_plx_mw_set_trans_internal()
725 if (bsize > 0 && bsize < 1024 * 1024) in ntb_plx_mw_set_trans_internal()
734 if ((off & (bsize - 1)) != 0) in ntb_plx_mw_set_trans_internal()
738 if (sc->b2b_mw >= 0 && mw->mw_64bit) { in ntb_plx_mw_set_trans_internal()
739 val64 = 0; in ntb_plx_mw_set_trans_internal()
740 if (bsize > 0) in ntb_plx_mw_set_trans_internal()
741 val64 = (~(bsize - 1) & ~0xfffff); in ntb_plx_mw_set_trans_internal()
742 val64 |= 0xc; in ntb_plx_mw_set_trans_internal()
743 PNTX_WRITE(sc, 0xe8 + (mw->mw_bar - 2) * 4, val64); in ntb_plx_mw_set_trans_internal()
744 PNTX_WRITE(sc, 0xe8 + (mw->mw_bar - 2) * 4 + 4, val64 >> 32); in ntb_plx_mw_set_trans_internal()
746 val64 = 0x2000000000000000 * mw->mw_bar + off; in ntb_plx_mw_set_trans_internal()
749 } else if (sc->b2b_mw >= 0) { in ntb_plx_mw_set_trans_internal()
750 val = 0; in ntb_plx_mw_set_trans_internal()
751 if (bsize > 0) in ntb_plx_mw_set_trans_internal()
752 val = (~(bsize - 1) & ~0xfffff); in ntb_plx_mw_set_trans_internal()
753 PNTX_WRITE(sc, 0xe8 + (mw->mw_bar - 2) * 4, val); in ntb_plx_mw_set_trans_internal()
755 val64 = 0x20000000 * mw->mw_bar + off; in ntb_plx_mw_set_trans_internal()
760 addr = split ? UINT64_MAX : mw->splits[0].mw_xlat_addr; in ntb_plx_mw_set_trans_internal()
762 PNTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4, addr); in ntb_plx_mw_set_trans_internal()
763 PNTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4 + 4, addr >> 32); in ntb_plx_mw_set_trans_internal()
765 PNTX_WRITE(sc, 0xc3c + (mw->mw_bar - 2) * 4, addr); in ntb_plx_mw_set_trans_internal()
769 size = split ? 0 : mw->splits[0].mw_xlat_size; in ntb_plx_mw_set_trans_internal()
770 if (sc->alut && mw->mw_bar == 2 && (sc->split > 0 || in ntb_plx_mw_set_trans_internal()
771 ((addr & (bsize - 1)) != 0 || size != bsize))) { in ntb_plx_mw_set_trans_internal()
773 for (i = sp = 0; i < 128 * sc->alut; i++) { in ntb_plx_mw_set_trans_internal()
774 if (i % (128 * sc->alut >> sc->split) == 0) { in ntb_plx_mw_set_trans_internal()
778 val = sc->link ? 0 : 1; in ntb_plx_mw_set_trans_internal()
781 val *= 0x1000 * sc->alut; in ntb_plx_mw_set_trans_internal()
782 val += 0x38000 + i * 4 + (i >= 128 ? 0x0e00 : 0); in ntb_plx_mw_set_trans_internal()
784 bus_write_4(sc->conf_res, val + 0x400, eaddr >> 32); in ntb_plx_mw_set_trans_internal()
785 bus_write_4(sc->conf_res, val + 0x800, in ntb_plx_mw_set_trans_internal()
786 (eaddr < addr + size) ? 0x3 : 0); in ntb_plx_mw_set_trans_internal()
789 NTX_WRITE(sc, 0xc94, 0x10000000); in ntb_plx_mw_set_trans_internal()
791 NTX_WRITE(sc, 0xc94, 0); in ntb_plx_mw_set_trans_internal()
793 return (0); in ntb_plx_mw_set_trans_internal()
820 return (ntb_plx_mw_set_trans(dev, mw_idx, 0, 0)); in ntb_plx_mw_clear_trans()
835 return (0); in ntb_plx_mw_get_wc()
852 return (0); in ntb_plx_mw_set_wc()
854 off = 0; in ntb_plx_mw_set_wc()
856 KASSERT(sc->b2b_off != 0, in ntb_plx_mw_set_wc()
861 split = (mw->mw_bar == 2) ? sc->split : 0; in ntb_plx_mw_set_wc()
865 if (rc == 0) in ntb_plx_mw_set_wc()
890 return (0); in ntb_plx_spad_write()
898 for (t = 0; t <= 1000; t++) { in ntb_plx_spad_write()
901 return (0); in ntb_plx_spad_write()
905 "Can't write Physical Layer User Test Pattern (0x%x)\n", in ntb_plx_spad_write()
917 for (i = 0; i < sc->spad_count1 + sc->spad_count2; i++) in ntb_plx_spad_clear()
918 ntb_plx_spad_write(dev, i, 0); in ntb_plx_spad_clear()
935 return (0); in ntb_plx_spad_read()
951 if (sc->b2b_mw >= 0) in ntb_plx_peer_spad_write()
955 return (0); in ntb_plx_peer_spad_write()
971 if (sc->b2b_mw >= 0) in ntb_plx_peer_spad_read()
975 return (0); in ntb_plx_peer_spad_read()
996 if (vector > 0) in ntb_plx_db_vector_mask()
997 return (0); in ntb_plx_db_vector_mask()
1006 NTX_WRITE(sc, sc->link ? 0xc60 : 0xc50, bits); in ntb_plx_db_clear()
1014 NTX_WRITE(sc, sc->link ? 0xc68 : 0xc58, bits); in ntb_plx_db_clear_mask()
1022 return (NTX_READ(sc, sc->link ? 0xc5c : 0xc4c)); in ntb_plx_db_read()
1030 NTX_WRITE(sc, sc->link ? 0xc64 : 0xc54, bits); in ntb_plx_db_set_mask()
1041 if (sc->b2b_mw >= 0) { in ntb_plx_peer_db_addr()
1043 *db_addr = (uint64_t)mw->mw_pbase + PLX_NTX_BASE(sc) + 0xc4c; in ntb_plx_peer_db_addr()
1046 *db_addr += sc->link ? 0xc4c : 0xc5c; in ntb_plx_peer_db_addr()
1049 return (0); in ntb_plx_peer_db_addr()
1057 if (sc->b2b_mw >= 0) in ntb_plx_peer_db_set()
1058 BNTX_WRITE(sc, 0xc4c, bit); in ntb_plx_peer_db_set()
1060 NTX_WRITE(sc, sc->link ? 0xc4c : 0xc5c, bit); in ntb_plx_peer_db_set()