Lines Matching +full:0 +full:x0040
42 * Params: [in] P = Bit position of start of the bit field (lsb is 0).
51 #define NTB_LINK_STATUS_ACTIVE 0x2000
52 #define NTB_LINK_SPEED_MASK 0x000f
53 #define NTB_LINK_WIDTH_MASK 0x03f0
67 #define XEON_SPCICMD_OFFSET 0x0504
68 #define XEON_DEVCTRL_OFFSET 0x0598
69 #define XEON_DEVSTS_OFFSET 0x059a
70 #define XEON_LINK_STATUS_OFFSET 0x01a2
71 #define XEON_SLINK_STATUS_OFFSET 0x05a2
73 #define XEON_PBAR2LMT_OFFSET 0x0000
74 #define XEON_PBAR4LMT_OFFSET 0x0008
75 #define XEON_PBAR5LMT_OFFSET 0x000c
76 #define XEON_PBAR2XLAT_OFFSET 0x0010
77 #define XEON_PBAR4XLAT_OFFSET 0x0018
78 #define XEON_PBAR5XLAT_OFFSET 0x001c
79 #define XEON_SBAR2LMT_OFFSET 0x0020
80 #define XEON_SBAR4LMT_OFFSET 0x0028
81 #define XEON_SBAR5LMT_OFFSET 0x002c
82 #define XEON_SBAR2XLAT_OFFSET 0x0030
83 #define XEON_SBAR4XLAT_OFFSET 0x0038
84 #define XEON_SBAR5XLAT_OFFSET 0x003c
85 #define XEON_SBAR0BASE_OFFSET 0x0040
86 #define XEON_SBAR2BASE_OFFSET 0x0048
87 #define XEON_SBAR4BASE_OFFSET 0x0050
88 #define XEON_SBAR5BASE_OFFSET 0x0054
89 #define XEON_NTBCNTL_OFFSET 0x0058
90 #define XEON_SBDF_OFFSET 0x005c
91 #define XEON_PDOORBELL_OFFSET 0x0060
92 #define XEON_PDBMSK_OFFSET 0x0062
93 #define XEON_SDOORBELL_OFFSET 0x0064
94 #define XEON_SDBMSK_OFFSET 0x0066
95 #define XEON_USMEMMISS_OFFSET 0x0070
96 #define XEON_SPAD_OFFSET 0x0080
98 #define XEON_SPADSEMA4_OFFSET 0x00c0
99 #define XEON_WCCNTRL_OFFSET 0x00e0
100 #define XEON_UNCERRSTS_OFFSET 0x014c
101 #define XEON_CORERRSTS_OFFSET 0x0158
102 #define XEON_B2B_SPAD_OFFSET 0x0100
103 #define XEON_B2B_DOORBELL_OFFSET 0x0140
104 #define XEON_B2B_XLAT_OFFSETL 0x0144
105 #define XEON_B2B_XLAT_OFFSETU 0x0148
112 #define ATOM_SPCICMD_OFFSET 0xb004
113 #define ATOM_MBAR23_OFFSET 0xb018
114 #define ATOM_MBAR45_OFFSET 0xb020
115 #define ATOM_DEVCTRL_OFFSET 0xb048
116 #define ATOM_LINK_STATUS_OFFSET 0xb052
117 #define ATOM_ERRCORSTS_OFFSET 0xb110
119 #define ATOM_SBAR2XLAT_OFFSET 0x0008
120 #define ATOM_SBAR4XLAT_OFFSET 0x0010
121 #define ATOM_PDOORBELL_OFFSET 0x0020
122 #define ATOM_PDBMSK_OFFSET 0x0028
123 #define ATOM_NTBCNTL_OFFSET 0x0060
124 #define ATOM_EBDF_OFFSET 0x0064
125 #define ATOM_SPAD_OFFSET 0x0080
127 #define ATOM_SPADSEMA_OFFSET 0x00c0
128 #define ATOM_STKYSPAD_OFFSET 0x00c4
129 #define ATOM_PBAR2XLAT_OFFSET 0x8008
130 #define ATOM_PBAR4XLAT_OFFSET 0x8010
131 #define ATOM_B2B_DOORBELL_OFFSET 0x8020
132 #define ATOM_B2B_SPAD_OFFSET 0x8080
133 #define ATOM_B2B_SPADSEMA_OFFSET 0x80c0
134 #define ATOM_B2B_STKYSPAD_OFFSET 0x80c4
136 #define ATOM_MODPHY_PCSREG4 0x1c004
137 #define ATOM_MODPHY_PCSREG6 0x1c006
139 #define ATOM_IP_BASE 0xc000
140 #define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024)
141 #define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180)
142 #define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040)
143 #define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324)
148 #define ATOM_IBIST_ERR_OFLOW 0x7fff7fff
150 #define NTB_CNTL_CFG_LOCK (1 << 0)
160 #define XEON_PBAR23SZ_OFFSET 0x00d0
161 #define XEON_PBAR45SZ_OFFSET 0x00d1
162 #define XEON_PBAR4SZ_OFFSET 0x00d1
163 #define XEON_PBAR5SZ_OFFSET 0x00d5
164 #define XEON_SBAR23SZ_OFFSET 0x00d2
165 #define XEON_SBAR4SZ_OFFSET 0x00d3
166 #define XEON_SBAR5SZ_OFFSET 0x00d6
167 #define NTB_PPD_OFFSET 0x00d4
168 #define XEON_PPD_CONN_TYPE 0x0003
169 #define XEON_PPD_DEV_TYPE 0x0010
170 #define XEON_PPD_SPLIT_BAR 0x0040
171 #define ATOM_PPD_INIT_LINK 0x0008
172 #define ATOM_PPD_CONN_TYPE 0x0300
173 #define ATOM_PPD_DEV_TYPE 0x1000
176 #define XEON_B2B_BAR0_ADDR 0x1000000000000000ull
177 #define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull
178 #define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull
179 #define XEON_B2B_BAR4_ADDR32 0x20000000ull
180 #define XEON_B2B_BAR5_ADDR32 0x40000000ull
183 #define XEON_B2B_MIN_SIZE 0x8000
200 #define XEON_GEN3_INT_REG_BAR0BASE 0x10
201 #define XEON_GEN3_INT_REG_BAR1BASE 0x18
202 #define XEON_GEN3_INT_REG_BAR2BASE 0x20
203 #define XEON_GEN3_INT_REG_IMBAR1SZ 0xd0
204 #define XEON_GEN3_INT_REG_IMBAR2SZ 0xd1
205 #define XEON_GEN3_INT_REG_EMBAR1SZ 0xd2
206 #define XEON_GEN3_INT_REG_EMBAR2SZ 0xd3
207 #define XEON_GEN3_INT_REG_PPD 0xd4
208 #define XEON_GEN3_INT_LNK_STS_OFFSET 0x01a2
214 #define XEON_GEN3_EXT_REG_PCI_CMD 0x4504
215 #define XEON_GEN3_EXT_REG_BAR0BASE 0x4510
216 #define XEON_GEN3_EXT_REG_BAR1BASE 0x4518
217 #define XEON_GEN3_EXT_REG_BAR2BASE 0x4520
222 #define XEON_GEN3_REG_IMNTB_CTRL 0x0000
223 #define XEON_GEN3_REG_IMBAR1XBASE 0x0010
224 #define XEON_GEN3_REG_IMBAR1XLIMIT 0x0018
225 #define XEON_GEN3_REG_IMBAR2XBASE 0x0020
226 #define XEON_GEN3_REG_IMBAR2XLIMIT 0x0028
227 #define XEON_GEN3_REG_IMINT_STATUS 0x0040
228 #define XEON_GEN3_REG_IMINT_DISABLE 0x0048
229 #define XEON_GEN3_REG_IMSPAD 0x0080
230 #define XEON_GEN3_REG_IMINTVEC00 0x00d0
231 #define XEON_GEN3_REG_IMDOORBELL 0x0100
232 #define XEON_GEN3_REG_IMB2B_SSPAD 0x0180 /* Pseudo SP registers */
237 #define XEON_GEN3_REG_EMBAR0XBASE 0x4008
238 #define XEON_GEN3_REG_EMBAR1XBASE 0x4010
239 #define XEON_GEN3_REG_EMBAR1XLIMIT 0x4018
240 #define XEON_GEN3_REG_EMBAR2XBASE 0x4020
241 #define XEON_GEN3_REG_EMBAR2XLIMIT 0x4028
242 #define XEON_GEN3_REG_EMINT_STATUS 0x4040
243 #define XEON_GEN3_REG_EMINT_DISABLE 0x4048
244 #define XEON_GEN3_REG_EMSPAD 0x4080
245 #define XEON_GEN3_REG_EMDOORBELL 0x4100
248 #define XEON_GEN3_REG_PPD_PORT_DEF_F(X) M8_F(X, 0, 2)
256 #define XEON_GEN4_CFG_REG_BAR0BASE 0x0010
257 #define XEON_GEN4_CFG_REG_BAR1BASE 0x0018
258 #define XEON_GEN4_CFG_REG_BAR2BASE 0x0020
259 #define XEON_GEN4_CFG_REG_IMBAR1SZ 0x00c4
260 #define XEON_GEN4_CFG_REG_IMBAR2SZ 0x00c5
261 #define XEON_GEN4_CFG_REG_EMBAR1SZ 0x00c6
262 #define XEON_GEN4_CFG_REG_EMBAR2SZ 0x00c7
263 #define XEON_GEN4_CFG_REG_DEVCTRL 0x0048
264 #define XEON_GEN4_CFG_REG_DEVSTS 0x004a
265 #define XEON_GEN4_CFG_REG_UNCERRSTS 0x0104
266 #define XEON_GEN4_CFG_REG_CORERRSTS 0x0110
269 #define XEON_GEN4_REG_IMNTB_CTL 0x0000
270 #define XEON_GEN4_REG_IMBAR1XBASE 0x0010
271 #define XEON_GEN4_REG_IMBAR1XLIMIT 0x0018
272 #define XEON_GEN4_REG_IMBAR2XBASE 0x0020
273 #define XEON_GEN4_REG_IMBAR2XLIMIT 0x0028
274 #define XEON_GEN4_REG_IMINT_STATUS 0x0040
275 #define XEON_GEN4_REG_IMINT_DISABLE 0x0048
276 #define XEON_GEN4_REG_INTVEC 0x0050 /* 0-32 vecs */
277 #define XEON_GEN4_REG_IMSPAD 0x0080 /* 0-15 SPADs */
278 #define XEON_GEN4_REG_IMDOORBELL 0x0100 /* 0-31 doorbells */
284 #define XEON_GEN4_REG_EXT_BAR1BASE 0x3018
285 #define XEON_GEN4_REG_EXT_BAR2BASE 0x3020
286 #define XEON_GEN4_REG_EXT_LTR_SWSEL 0x30ec
287 #define XEON_GEN4_REG_EXT_LTR_ACTIVE 0x30f0
288 #define XEON_GEN4_REG_EXT_LTR_IDLE 0x30f4
290 #define XEON_GEN4_REG_EMSPAD 0x8080 /* 32K + SPAD_offset */
293 #define XEON_GEN4_REG_LINK_CTRL 0xb050
294 #define XEON_GEN4_REG_LINK_STATUS 0xb052
295 #define XEON_GEN4_REG_SLOTSTS 0xb05a
296 #define XEON_GEN4_REG_PPD0 0xb0d4
297 #define XEON_GEN4_REG_PPD1 0xb4c0
298 #define XEON_GEN4_REG_LTSSMSTATEJMP 0xf040
301 #define PCI_DEV_REV_ICX_MIN 0x2
302 #define PCI_DEV_REV_ICX_MAX 0xF
313 #define NTB_CTL_E2I_BAR23_SNOOP 0x000004
314 #define NTB_CTL_E2I_BAR23_NOSNOOP 0x000008
315 #define NTB_CTL_I2E_BAR23_SNOOP 0x000010
316 #define NTB_CTL_I2E_BAR23_NOSNOOP 0x000020
317 #define NTB_CTL_E2I_BAR45_SNOOP 0x000040
318 #define NTB_CTL_E2I_BAR45_NOSNOO 0x000080
319 #define NTB_CTL_I2E_BAR45_SNOOP 0x000100
320 #define NTB_CTL_I2E_BAR45_NOSNOOP 0x000200
321 #define NTB_CTL_BUSNO_DIS_INC 0x000400
322 #define NTB_CTL_LINK_DOWN 0x010000
324 #define NTB_SJC_FORCEDETECT 0x000004
327 #define GEN4_PPD_CLEAR_TRN 0x0001
328 #define GEN4_PPD_LINKTRN 0x0008
329 #define GEN4_PPD_CONN_MASK 0x0300
330 #define SPR_PPD_CONN_MASK 0x0700
331 #define GEN4_PPD_CONN_B2B 0x0200
332 #define GEN4_PPD_DEV_MASK 0x1000
333 #define GEN4_PPD_DEV_DSD 0x1000
334 #define GEN4_PPD_DEV_USD 0x0000
335 #define SPR_PPD_DEV_MASK 0x4000
336 #define SPR_PPD_DEV_DSD 0x4000
337 #define SPR_PPD_DEV_USD 0x0000
339 #define GEN4_LINK_CTRL_LINK_DISABLE 0x0010
340 #define GEN4_SLOTSTS_DLLSCS 0x100
357 #define NTB_LTR_SWSEL_ACTIVE 0x0
358 #define NTB_LTR_SWSEL_IDLE 0x1
361 #define NTB_LTR_ACTIVE_VAL 0x0000 /* 0 us */
362 #define NTB_LTR_ACTIVE_LATSCALE 0x0800 /* 1us scale */
363 #define NTB_LTR_ACTIVE_REQMNT 0x8000 /* snoop req enable */
365 #define NTB_LTR_IDLE_VAL 0x0258 /* 600 us */
366 #define NTB_LTR_IDLE_LATSCALE 0x0800 /* 1us scale */
367 #define NTB_LTR_IDLE_REQMNT 0x8000 /* snoop req enable */