Lines Matching full:bar
238 /* Offset of peer bar0 in B2B BAR */
295 #define intel_ntb_bar_read(SIZE, bar, offset) \ argument
296 bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \
297 ntb->bar_info[(bar)].pci_bus_handle, (offset))
298 #define intel_ntb_bar_write(SIZE, bar, offset, val) \ argument
299 bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \
300 ntb->bar_info[(bar)].pci_bus_handle, (offset), (val))
336 static int map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar);
338 struct ntb_pci_bar_info *bar);
390 static void save_bar_parameters(struct ntb_pci_bar_info *bar);
679 "(split-BAR mode).");
682 "(split-BAR mode).");
693 "(split-BAR mode).");
696 "(split-BAR mode).");
830 bar_is_64bit(struct ntb_softc *ntb, enum ntb_bar bar) in bar_is_64bit() argument
833 KASSERT(bar < NTB_MAX_BARS, ("bogus bar")); in bar_is_64bit()
834 return (bar < NTB_B2B_BAR_2 || !HAS_FEATURE(ntb, NTB_SPLIT_BAR)); in bar_is_64bit()
838 bar_get_xlat_params(struct ntb_softc *ntb, enum ntb_bar bar, uint32_t *base, in bar_get_xlat_params() argument
843 switch (bar) { in bar_get_xlat_params()
860 KASSERT(bar >= NTB_B2B_BAR_1 && bar < NTB_MAX_BARS, in bar_get_xlat_params()
861 ("bad bar")); in bar_get_xlat_params()
877 struct ntb_pci_bar_info *bar; in intel_ntb_map_pci_bars() local
880 bar = &ntb->bar_info[NTB_CONFIG_BAR]; in intel_ntb_map_pci_bars()
881 bar->pci_resource_id = PCIR_BAR(0); in intel_ntb_map_pci_bars()
882 rc = map_mmr_bar(ntb, bar); in intel_ntb_map_pci_bars()
895 bar->size, 1, bar->size, 0, NULL, NULL, &ntb->bar0_dma_tag)) { in intel_ntb_map_pci_bars()
904 bar->pbase, bar->size, 0)) { in intel_ntb_map_pci_bars()
909 bar = &ntb->bar_info[NTB_B2B_BAR_1]; in intel_ntb_map_pci_bars()
910 bar->pci_resource_id = PCIR_BAR(2); in intel_ntb_map_pci_bars()
911 rc = map_memory_window_bar(ntb, bar); in intel_ntb_map_pci_bars()
915 bar->psz_off = XEON_GEN3_INT_REG_IMBAR1SZ; in intel_ntb_map_pci_bars()
916 bar->ssz_off = XEON_GEN3_INT_REG_EMBAR1SZ; in intel_ntb_map_pci_bars()
917 bar->pbarxlat_off = XEON_GEN3_REG_EMBAR1XBASE; in intel_ntb_map_pci_bars()
919 bar->psz_off = XEON_GEN4_CFG_REG_IMBAR1SZ; in intel_ntb_map_pci_bars()
920 bar->ssz_off = XEON_GEN4_CFG_REG_EMBAR1SZ; in intel_ntb_map_pci_bars()
921 bar->pbarxlat_off = XEON_GEN4_REG_EXT_BAR1BASE; in intel_ntb_map_pci_bars()
923 bar->psz_off = XEON_PBAR23SZ_OFFSET; in intel_ntb_map_pci_bars()
924 bar->ssz_off = XEON_SBAR23SZ_OFFSET; in intel_ntb_map_pci_bars()
925 bar->pbarxlat_off = XEON_PBAR2XLAT_OFFSET; in intel_ntb_map_pci_bars()
928 bar = &ntb->bar_info[NTB_B2B_BAR_2]; in intel_ntb_map_pci_bars()
929 bar->pci_resource_id = PCIR_BAR(4); in intel_ntb_map_pci_bars()
930 rc = map_memory_window_bar(ntb, bar); in intel_ntb_map_pci_bars()
934 bar->psz_off = XEON_GEN3_INT_REG_IMBAR2SZ; in intel_ntb_map_pci_bars()
935 bar->ssz_off = XEON_GEN3_INT_REG_EMBAR2SZ; in intel_ntb_map_pci_bars()
936 bar->pbarxlat_off = XEON_GEN3_REG_EMBAR2XBASE; in intel_ntb_map_pci_bars()
938 bar->psz_off = XEON_GEN4_CFG_REG_IMBAR2SZ; in intel_ntb_map_pci_bars()
939 bar->ssz_off = XEON_GEN4_CFG_REG_EMBAR2SZ; in intel_ntb_map_pci_bars()
940 bar->pbarxlat_off = XEON_GEN4_REG_EXT_BAR2BASE; in intel_ntb_map_pci_bars()
942 bar->psz_off = XEON_PBAR4SZ_OFFSET; in intel_ntb_map_pci_bars()
943 bar->ssz_off = XEON_SBAR4SZ_OFFSET; in intel_ntb_map_pci_bars()
944 bar->pbarxlat_off = XEON_PBAR4XLAT_OFFSET; in intel_ntb_map_pci_bars()
952 device_printf(ntb->device, "no split bar support\n"); in intel_ntb_map_pci_bars()
956 bar = &ntb->bar_info[NTB_B2B_BAR_3]; in intel_ntb_map_pci_bars()
957 bar->pci_resource_id = PCIR_BAR(5); in intel_ntb_map_pci_bars()
958 rc = map_memory_window_bar(ntb, bar); in intel_ntb_map_pci_bars()
959 bar->psz_off = XEON_PBAR5SZ_OFFSET; in intel_ntb_map_pci_bars()
960 bar->ssz_off = XEON_SBAR5SZ_OFFSET; in intel_ntb_map_pci_bars()
961 bar->pbarxlat_off = XEON_PBAR5XLAT_OFFSET; in intel_ntb_map_pci_bars()
971 print_map_success(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar, in print_map_success() argument
976 "Mapped BAR%d v:[%p-%p] p:[0x%jx-0x%jx] (0x%jx bytes) (%s)\n", in print_map_success()
977 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, in print_map_success()
978 (char *)bar->vbase + bar->size - 1, in print_map_success()
979 (uintmax_t)bar->pbase, (uintmax_t)(bar->pbase + bar->size - 1), in print_map_success()
980 (uintmax_t)bar->size, kind); in print_map_success()
984 map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) in map_mmr_bar() argument
987 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, in map_mmr_bar()
988 &bar->pci_resource_id, RF_ACTIVE); in map_mmr_bar()
989 if (bar->pci_resource == NULL) in map_mmr_bar()
992 save_bar_parameters(bar); in map_mmr_bar()
993 bar->map_mode = VM_MEMATTR_UNCACHEABLE; in map_mmr_bar()
994 print_map_success(ntb, bar, "mmr"); in map_mmr_bar()
999 map_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) in map_memory_window_bar() argument
1005 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, in map_memory_window_bar()
1006 &bar->pci_resource_id, RF_ACTIVE); in map_memory_window_bar()
1008 if (bar->pci_resource == NULL) in map_memory_window_bar()
1011 save_bar_parameters(bar); in map_memory_window_bar()
1013 * Ivytown NTB BAR sizes are misreported by the hardware due to a in map_memory_window_bar()
1023 * SYS_RES_MEMORY, &bar->pci_resource_id, 0ul, ~0ul, in map_memory_window_bar()
1029 if (bar->pci_resource_id == PCIR_BAR(2)) in map_memory_window_bar()
1037 bar->pci_resource, bar->pbase, in map_memory_window_bar()
1038 bar->pbase + (1ul << bar_size_bits) - 1); in map_memory_window_bar()
1041 "unable to resize bar\n"); in map_memory_window_bar()
1045 save_bar_parameters(bar); in map_memory_window_bar()
1048 bar->map_mode = VM_MEMATTR_UNCACHEABLE; in map_memory_window_bar()
1049 print_map_success(ntb, bar, "mw"); in map_memory_window_bar()
1056 if (mapmode == bar->map_mode) in map_memory_window_bar()
1059 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mapmode); in map_memory_window_bar()
1061 bar->map_mode = mapmode; in map_memory_window_bar()
1063 "Marked BAR%d v:[%p-%p] p:[0x%jx-0x%jx] as " in map_memory_window_bar()
1065 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, in map_memory_window_bar()
1066 (char *)bar->vbase + bar->size - 1, in map_memory_window_bar()
1067 (uintmax_t)bar->pbase, in map_memory_window_bar()
1068 (uintmax_t)(bar->pbase + bar->size - 1), in map_memory_window_bar()
1072 "Unable to mark BAR%d v:[%p-%p] p:[0x%jx-0x%jx] as " in map_memory_window_bar()
1074 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, in map_memory_window_bar()
1075 (char *)bar->vbase + bar->size - 1, in map_memory_window_bar()
1076 (uintmax_t)bar->pbase, in map_memory_window_bar()
1077 (uintmax_t)(bar->pbase + bar->size - 1), in map_memory_window_bar()
1086 struct ntb_pci_bar_info *bar; in intel_ntb_unmap_pci_bar() local
1096 bar = &ntb->bar_info[i]; in intel_ntb_unmap_pci_bar()
1097 if (bar->pci_resource != NULL) in intel_ntb_unmap_pci_bar()
1099 bar->pci_resource_id, bar->pci_resource); in intel_ntb_unmap_pci_bar()
2153 struct ntb_pci_bar_info *bar; in xeon_reset_sbar_size() local
2159 bar = &ntb->bar_info[idx]; in xeon_reset_sbar_size()
2160 bar_sz = pci_read_config(ntb->device, bar->psz_off, 1); in xeon_reset_sbar_size()
2167 pci_write_config(ntb->device, bar->ssz_off, bar_sz, 1); in xeon_reset_sbar_size()
2168 bar_sz = pci_read_config(ntb->device, bar->ssz_off, 1); in xeon_reset_sbar_size()
2209 struct ntb_pci_bar_info *bar; in xeon_set_pbar_xlat() local
2211 bar = &ntb->bar_info[idx]; in xeon_set_pbar_xlat()
2213 intel_ntb_reg_write(4, bar->pbarxlat_off, base_addr); in xeon_set_pbar_xlat()
2214 base_addr = intel_ntb_reg_read(4, bar->pbarxlat_off); in xeon_set_pbar_xlat()
2216 intel_ntb_reg_write(8, bar->pbarxlat_off, base_addr); in xeon_set_pbar_xlat()
2217 base_addr = intel_ntb_reg_read(8, bar->pbarxlat_off); in xeon_set_pbar_xlat()
2238 ("invalid b2b mw bar")); in xeon_setup_b2b_mw()
2250 "B2B bar size is too small!\n"); in xeon_setup_b2b_mw()
2256 * Reset the secondary bar sizes to match the primary bar sizes. in xeon_setup_b2b_mw()
2257 * (Except, disable or halve the size of the B2B secondary bar.) in xeon_setup_b2b_mw()
2274 KASSERT(false, ("invalid bar")); in xeon_setup_b2b_mw()
2280 * register BAR. The B2B BAR is either disabled above or configured in xeon_setup_b2b_mw()
2283 * Also set up incoming BAR limits == base (zero length window). in xeon_setup_b2b_mw()
2305 * We point the chosen MSIX MW BAR xlat to remote LAPIC for in xeon_setup_b2b_mw()
2325 /* Zero outgoing translation limits (whole bar size windows) */ in xeon_setup_b2b_mw()
2350 KASSERT(false, ("invalid bar")); in xeon_setup_b2b_mw()
2399 /* Config outgoing translation limits (whole bar size windows) */ in xeon_gen3_setup_b2b_mw()
3556 struct ntb_pci_bar_info *bar; in intel_ntb_mw_get_range() local
3566 bar = &ntb->bar_info[bar_num]; in intel_ntb_mw_get_range()
3580 *base = bar->pbase + bar_b2b_off; in intel_ntb_mw_get_range()
3582 *vbase = bar->vbase + bar_b2b_off; in intel_ntb_mw_get_range()
3584 *size = bar->size - bar_b2b_off; in intel_ntb_mw_get_range()
3586 *align = bar->size; in intel_ntb_mw_get_range()
3598 struct ntb_pci_bar_info *bar; in intel_ntb_mw_set_trans() local
3609 bar = &ntb->bar_info[bar_num]; in intel_ntb_mw_set_trans()
3611 bar_size = bar->size; in intel_ntb_mw_set_trans()
3617 /* Hardware requires that addr is aligned to bar size */ in intel_ntb_mw_set_trans()
3655 /* Configure 32-bit (split) BAR MW */ in intel_ntb_mw_set_trans()
3700 struct ntb_pci_bar_info *bar; in intel_ntb_mw_get_wc() local
3706 bar = &ntb->bar_info[intel_ntb_mw_to_bar(ntb, idx)]; in intel_ntb_mw_get_wc()
3707 *mode = bar->map_mode; in intel_ntb_mw_get_wc()
3726 struct ntb_pci_bar_info *bar; in intel_ntb_mw_set_wc_internal() local
3729 bar = &ntb->bar_info[intel_ntb_mw_to_bar(ntb, idx)]; in intel_ntb_mw_set_wc_internal()
3730 if (bar->map_mode == mode) in intel_ntb_mw_set_wc_internal()
3733 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mode); in intel_ntb_mw_set_wc_internal()
3735 bar->map_mode = mode; in intel_ntb_mw_set_wc_internal()
3791 struct ntb_pci_bar_info *bar; in intel_ntb_peer_db_addr() local
3797 bar = &ntb->bar_info[NTB_CONFIG_BAR]; in intel_ntb_peer_db_addr()
3803 bar = &ntb->bar_info[intel_ntb_mw_to_bar(ntb, ntb->b2b_mw_idx)]; in intel_ntb_peer_db_addr()
3806 KASSERT(bar->pci_bus_tag != X86_BUS_SPACE_IO, ("uh oh")); in intel_ntb_peer_db_addr()
3809 *db_addr = ((uint64_t)bar->pci_bus_handle + regoff); in intel_ntb_peer_db_addr()
3853 save_bar_parameters(struct ntb_pci_bar_info *bar) in save_bar_parameters() argument
3856 bar->pci_bus_tag = rman_get_bustag(bar->pci_resource); in save_bar_parameters()
3857 bar->pci_bus_handle = rman_get_bushandle(bar->pci_resource); in save_bar_parameters()
3858 bar->pbase = rman_get_start(bar->pci_resource); in save_bar_parameters()
3859 bar->size = rman_get_size(bar->pci_resource); in save_bar_parameters()
3860 bar->vbase = rman_get_virtual(bar->pci_resource); in save_bar_parameters()