Lines Matching +full:reset +full:- +full:duration +full:- +full:ms
61 bus_read_4((sc)->res[0], (reg))
63 bus_write_4((sc)->res[0], (reg), (val))
66 bus_read_region_4((sc)->res[0], (reg), (val), (c))
68 bus_write_region_4((sc)->res[0], (reg), (val), (c))
71 bus_read_4((sc)->res[0], MVNETA_PORTMIB_BASE + (reg))
81 * Default timer is duration of MTU sized frame transmission.
161 #define MVNETA_WATCHDOG_TXCOMP (hz / 10) /* 100ms */
181 ctr -= MVNETA_TX_RING_CNT; in tx_counter_adv()
192 ctr -= MVNETA_RX_RING_CNT; in rx_counter_adv()
209 KASSERT(mtx_owned(&(sc)->mtx), ("SC mutex not owned"))
211 KASSERT(mtx_owned(&(sc)->bm.bm_mtx), ("BM mutex not owned"))
213 KASSERT(mtx_owned(&(sc)->rx_ring[(q)].ring_mtx),\
216 KASSERT(mtx_owned(&(sc)->tx_ring[(q)].ring_mtx),\
274 boolean_t use_inband_status; /* In-band link status */
313 uint32_t counter_watchdog; /* manual reset when clearing mib */
314 uint32_t counter_watchdog_mib; /* reset after each mib update */
317 (&(sc)->rx_ring[(q)])
319 (&(sc)->tx_ring[(q)])