Lines Matching +full:rx +full:- +full:queue +full:- +full:3
46 /* XXX: Currently multi-queue can be used on the Tx side only */
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
62 #define MVNETA_TX_QUEUE_ALL ((1<<MVNETA_TX_QNUM_MAX)-1)
63 #define MVNETA_RX_QUEUE_ALL ((1<<MVNETA_RX_QNUM_MAX)-1)
73 #define MVNETA_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */
74 #define MVNETA_S(n) (0x2204 + ((n) << 3)) /* Size */
99 /* Rx DMA Hardware Parser Registers */
117 /* Rx DMA Miscellaneous Registers */
118 #define MVNETA_PMFS 0x247c /* Port Rx Minimal Frame Size */
119 #define MVNETA_PDFC 0x2484 /* Port Rx Discard Frame Counter */
121 #define MVNETA_RQC 0x2680 /* Receive Queue Command */
123 /* Rx DMA Networking Controller Miscellaneous Registers */
124 #define MVNETA_PRXC(q) (0x1400 + ((q) << 2)) /*Port RX queues Config*/
125 #define MVNETA_PRXSNP(q) (0x1420 + ((q) << 2)) /* Port RX queues Snoop */
129 #define MVNETA_PRXS(q) (0x14e0 + ((q) << 2)) /*Port RX queues Status */
132 #define MVNETA_PRXINIT 0x1cc0 /* Port RX Initialization */
134 /* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */
137 #define MVNETA_TQC 0x2448 /* Transmit Queue Command */
149 #define MVNETA_TXTBC(q) (0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/
157 /* Tx DMA Queue Arbiter Registers (Version 1) */
158 #define MVNETA_TQFPC_V1 0x24dc /* Transmit Queue Fixed Priority Cfg */
159 #define MVNETA_TQTBC_V1 0x24e0 /* Transmit Queue Token-Bucket Cfg */
161 #define MVNETA_PMTBS_V1 0x24ec /* Port Max Token-Bucket Size */
163 /* Transmit Queue Token-Bucket Counter */
165 /* Transmit Queue Token-Bucket Configuration */
168 /* Tx DMA Queue Arbiter Registers (Version 3) */
169 #define MVNETA_TQC1_V3 0x3e00 /* Transmit Queue Command1 */
170 #define MVNETA_TQFPC_V3 0x3e04 /* Transmit Queue Fixed Priority Cfg */
174 #define MVNETA_PMTBS_V3 0x3e14 /* Port Max Token-Bucket Size */
176 /* Transmit Queue Refill */
178 /* Transmit Queue Max Token-Bucket Size */
180 /* Transmit Queue Token-Bucket Counter */
182 /* Transmit Queue Arbiter Cfg */
184 /* Transmit Queue IPG(valid q=2..3) */
207 /* Gigabit Ethernet Auto-Negotiation Configuration Registers */
208 #define MVNETA_PANC 0x2c0c /* Port Auto-Negotiation Configuration*/
214 #define MVNETA_PMACC3 0x2c48 /* Port MAC Control 3 */
239 /* Port Rx Interrupt Threshold */
269 /* MAC MIB Counters 0x3000 - 0x307c */
274 /* Rx */
330 #define MVNETA_S_SIZE(size) (((size) - 1) & 0xffff0000)
333 #define MVNETA_BARE_EN_MASK ((1 << MVNETA_NWINDOW) - 1)
368 #define MVNETA_EUIC_ADDRVNOMATCH (1 << 3)
394 #define MVNETA_SDC_RXBSZ_8_64BITWORDS MVNETA_SDC_RXBSZ(3)
404 #define MVNETA_SDC_TXBSZ_8_64BITWORDS MVNETA_SDC_TXBSZ(3)
420 * Rx DMA Hardware Parser Registers
425 #define MVNETA_ETP_ETHERTYPEPRIQ (0x7 << 2) /*EtherType Prio Queue*/
433 #define MVNETA_DF_QUEUE_ALL ((MVNETA_RX_QNUM_MAX-1) << 1)
434 #define MVNETA_DF_QUEUE_MASK ((MVNETA_RX_QNUM_MAX-1) << 1)
437 * Rx DMA Miscellaneous Registers
439 /* Port Rx Minimal Frame Size (MVNETA_PMFS) */
440 #define MVNETA_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c)
442 /* Receive Queue Command (MVNETA_RQC) */
451 * Rx DMA Networking Controller Miscellaneous Registers
453 /* Port RX queues Configuration (MVNETA_PRXC) */
456 /* Port RX queues Snoop (MVNETA_PRXSNP) */
460 /* Port RX queues Descriptors Queue Size (MVNETA_PRXDQS) */
464 /* Port RX queues Descriptors Queue Threshold (MVNETA_PRXDQTH) */
470 /* Port RX queues Status (MVNETA_PRXS) */
478 /* Port RX queues Status Update (MVNETA_PRXSU) */
482 /* Port RX Initialization (MVNETA_PRXINIT) */
488 /* Transmit Queue Command (MVNETA_TQC) */
499 /* Port TX queues Descriptors Queue Size (MVNETA_PTXDQS) */
500 /* Descriptors Queue Size */
530 * Tx DMA Queue Arbiter Registers (Version 1 )
532 /* Transmit Queue Fixed Priority Configuration */
561 #define MVNETA_PXCX_TXCRCDIS (1 << 3)
604 #define MVNETA_PSPC_MUST_SET (1 << 3 | 1 << 4 | 1 << 5 | 0x23 << 6)
608 * Gigabit Ethernet Auto-Negotiation Configuration Registers
610 /* Port Auto-Negotiation Configuration (MVNETA_PANC) */
614 #define MVNETA_PANC_INBANDANBYPASSEN (1 << 3)
641 #define MVNETA_PMACC2_PCSEN (1 << 3)
642 #define MVNETA_PMACC2_PCSEN (1 << 3)
648 #define MVNETA_PMACC2_SDTT_MASK (3 << 12) /* Select Data To Transmit */
652 #define MVNETA_PMACC2_SDTT_OC (3 << 12) /* One Constant */
653 #define MVNETA_PMACC2_MUSTSET (3 << 14)
655 /* Port MAC Control 3 (MVNETA_PMACC3) */
670 #define MVNETA_PI_PCSRXPRLPI (1 << 11) /* PCS Rx path received LPI*/
672 #define MVNETA_PI_MACRXPRLPI (1 << 13) /* MAC Rx path received LPI*/
692 #define MVNETA_LPIS_PCSRXPLPIS (1 << 0) /* PCS Rx path LPI status */
694 #define MVNETA_LPIS_MACRXPLPIS (1 << 2)/* MAC Rx path LP idle status */
695 #define MVNETA_LPIS_MACTXPLPWS (1 << 3)/* MAC Tx path LP wait status */
712 #define MVNETA_PSR_FULLDX (1 << 3)
715 #define MVNETA_PSR_PRP (1 << 6) /* Port Rx Pause */
717 #define MVNETA_PSR_PDP (1 << 8) /*Port is Doing Back-Pressure*/
726 /* Port CPU to Queue */
740 /* Tx Buffer Threshold Cross Queue*/
744 /* Rx Buffer Int. Coaleasing Th. Pri. Alrt Q */
748 /* Rx Descriptor Threshold Alert Queue*/
810 #define MVNETA_DLE_LOCAL_SEL_BITS_MASK (3 << 10)
866 #define MVNETA_RX_L4_MASK (3 << 21) /* L4 Type */
872 #define MVNETA_RX_EC_MASK (3 << 17) /* Error code */
910 #define MVNETA_TX_F_DSA_TAG (3 << 30) /* DSA Tag */
913 /* bit 3 reserved */
914 #define MVNETA_TX_F_EC_MASK (3 << 1) /* Error code */