Lines Matching +full:rx +full:- +full:queue +full:- +full:2
12 * 2. Redistributions in binary form must reproduce the above copyright
46 /* XXX: Currently multi-queue can be used on the Tx side only */
48 #define MVNETA_TX_QNUM_MAX 2
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
54 #error "MVNETA_TX_QNUM_MAX Should be a power of 2"
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
57 #error "MVNETA_RX_QNUM_MAX Should be a power of 2"
62 #define MVNETA_TX_QUEUE_ALL ((1<<MVNETA_TX_QNUM_MAX)-1)
63 #define MVNETA_RX_QUEUE_ALL ((1<<MVNETA_RX_QNUM_MAX)-1)
75 #define MVNETA_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */
99 /* Rx DMA Hardware Parser Registers */
104 #define MVNETA_DSCP(n) (0x2420 + ((n) << 2))
108 #define MVNETA_DFSMT(n) (0x3400 + ((n) << 2))
111 #define MVNETA_DFOMT(n) (0x3500 + ((n) << 2))
114 #define MVNETA_DFUT(n) (0x3600 + ((n) << 2))
117 /* Rx DMA Miscellaneous Registers */
118 #define MVNETA_PMFS 0x247c /* Port Rx Minimal Frame Size */
119 #define MVNETA_PDFC 0x2484 /* Port Rx Discard Frame Counter */
121 #define MVNETA_RQC 0x2680 /* Receive Queue Command */
123 /* Rx DMA Networking Controller Miscellaneous Registers */
124 #define MVNETA_PRXC(q) (0x1400 + ((q) << 2)) /*Port RX queues Config*/
125 #define MVNETA_PRXSNP(q) (0x1420 + ((q) << 2)) /* Port RX queues Snoop */
126 #define MVNETA_PRXDQA(q) (0x1480 + ((q) << 2)) /*P RXqueues desc Q Addr*/
127 #define MVNETA_PRXDQS(q) (0x14a0 + ((q) << 2)) /*P RXqueues desc Q Size*/
128 #define MVNETA_PRXDQTH(q) (0x14c0 + ((q) << 2)) /*P RXqueues desc Q Thrs*/
129 #define MVNETA_PRXS(q) (0x14e0 + ((q) << 2)) /*Port RX queues Status */
130 #define MVNETA_PRXSU(q) (0x1500 + ((q) << 2)) /*P RXqueues Stat Update*/
131 #define MVNETA_PRXDI(q) (0x1520 + ((q) << 2)) /*P RXqueues Stat Update*/
132 #define MVNETA_PRXINIT 0x1cc0 /* Port RX Initialization */
134 /* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */
137 #define MVNETA_TQC 0x2448 /* Transmit Queue Command */
144 #define MVNETA_PTXDQA(q) (0x3c00 + ((q) << 2)) /*P TXqueues desc Q Addr*/
145 #define MVNETA_PTXDQS(q) (0x3c20 + ((q) << 2)) /*P TXqueues desc Q Size*/
146 #define MVNETA_PTXS(q) (0x3c40 + ((q) << 2)) /* Port TX queues Status*/
147 #define MVNETA_PTXSU(q) (0x3c60 + ((q) << 2)) /*P TXqueues Stat Update*/
148 #define MVNETA_PTXDI(q) (0x3c80 + ((q) << 2)) /* P TXqueues Desc Index*/
149 #define MVNETA_TXTBC(q) (0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/
154 #define MVNETA_TXMH(n) (0x3d44 + ((n) << 2))
157 /* Tx DMA Queue Arbiter Registers (Version 1) */
158 #define MVNETA_TQFPC_V1 0x24dc /* Transmit Queue Fixed Priority Cfg */
159 #define MVNETA_TQTBC_V1 0x24e0 /* Transmit Queue Token-Bucket Cfg */
161 #define MVNETA_PMTBS_V1 0x24ec /* Port Max Token-Bucket Size */
163 /* Transmit Queue Token-Bucket Counter */
165 /* Transmit Queue Token-Bucket Configuration */
168 /* Tx DMA Queue Arbiter Registers (Version 3) */
169 #define MVNETA_TQC1_V3 0x3e00 /* Transmit Queue Command1 */
170 #define MVNETA_TQFPC_V3 0x3e04 /* Transmit Queue Fixed Priority Cfg */
174 #define MVNETA_PMTBS_V3 0x3e14 /* Port Max Token-Bucket Size */
175 #define MVNETA_QREFILL_V3(q) (0x3e20 + ((q) << 2))
176 /* Transmit Queue Refill */
177 #define MVNETA_QMTBS_V3(q) (0x3e40 + ((q) << 2))
178 /* Transmit Queue Max Token-Bucket Size */
179 #define MVNETA_QTTBC_V3(q) (0x3e60 + ((q) << 2))
180 /* Transmit Queue Token-Bucket Counter */
181 #define MVNETA_TQAC_V3(q) (0x3e80 + ((q) << 2))
182 /* Transmit Queue Arbiter Cfg */
183 #define MVNETA_TQIPG_V3(q) (0x3ea0 + ((q) << 2))
184 /* Transmit Queue IPG(valid q=2..3) */
207 /* Gigabit Ethernet Auto-Negotiation Configuration Registers */
208 #define MVNETA_PANC 0x2c0c /* Port Auto-Negotiation Configuration*/
213 #define MVNETA_PMACC2 0x2c08 /* Port MAC Control 2 */
215 #define MVNETA_CCFCPST(p) (0x2c58 + ((p) << 2)) /*CCFC Port Speed Timerp*/
225 #define MVNETA_LPIC2 0x2cc8 /* LPI control 2 */
237 #define MVNETA_PCP2Q(cpu) (0x2540 + ((cpu) << 2))
238 #define MVNETA_PRXITTH(q) (0x2580 + ((q) << 2))
239 /* Port Rx Interrupt Threshold */
269 /* MAC MIB Counters 0x3000 - 0x307c */
274 /* Rx */
330 #define MVNETA_S_SIZE(size) (((size) - 1) & 0xffff0000)
333 #define MVNETA_BARE_EN_MASK ((1 << MVNETA_NWINDOW) - 1)
340 #define MVNETA_EPAP_EPAR(win, ac) ((ac) << ((win) * 2))
367 #define MVNETA_EUIC_ADDRVIOL (1 << 2)
393 #define MVNETA_SDC_RXBSZ_4_64BITWORDS MVNETA_SDC_RXBSZ(2)
403 #define MVNETA_SDC_TXBSZ_4_64BITWORDS MVNETA_SDC_TXBSZ(2)
420 * Rx DMA Hardware Parser Registers
425 #define MVNETA_ETP_ETHERTYPEPRIQ (0x7 << 2) /*EtherType Prio Queue*/
433 #define MVNETA_DF_QUEUE_ALL ((MVNETA_RX_QNUM_MAX-1) << 1)
434 #define MVNETA_DF_QUEUE_MASK ((MVNETA_RX_QNUM_MAX-1) << 1)
437 * Rx DMA Miscellaneous Registers
439 /* Port Rx Minimal Frame Size (MVNETA_PMFS) */
440 #define MVNETA_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c)
442 /* Receive Queue Command (MVNETA_RQC) */
451 * Rx DMA Networking Controller Miscellaneous Registers
453 /* Port RX queues Configuration (MVNETA_PRXC) */
456 /* Port RX queues Snoop (MVNETA_PRXSNP) */
460 /* Port RX queues Descriptors Queue Size (MVNETA_PRXDQS) */
464 /* Port RX queues Descriptors Queue Threshold (MVNETA_PRXDQTH) */
470 /* Port RX queues Status (MVNETA_PRXS) */
478 /* Port RX queues Status Update (MVNETA_PRXSU) */
482 /* Port RX Initialization (MVNETA_PRXINIT) */
488 /* Transmit Queue Command (MVNETA_TQC) */
499 /* Port TX queues Descriptors Queue Size (MVNETA_PTXDQS) */
500 /* Descriptors Queue Size */
530 * Tx DMA Queue Arbiter Registers (Version 1 )
532 /* Transmit Queue Fixed Priority Configuration */
605 #define MVNETA_PSP1C_MUST_SET (1 << 0 | 1 << 1 | 1 << 2)
608 * Gigabit Ethernet Auto-Negotiation Configuration Registers
610 /* Port Auto-Negotiation Configuration (MVNETA_PANC) */
613 #define MVNETA_PANC_INBANDANEN (1 << 2)
632 #define MVNETA_PMACC0_FRAMESIZELIMIT(x) ((((x) >> 1) << 2) & 0x7ffc)
639 /* Port MAC Control 2 (MVNETA_PMACC2) */
651 #define MVNETA_PMACC2_SDTT_ZC (2 << 12) /* Zero Constant */
664 #define MVNETA_PI_ACOP (1 << 2) /* AnCompleted OnPort */
670 #define MVNETA_PI_PCSRXPRLPI (1 << 11) /* PCS Rx path received LPI*/
672 #define MVNETA_PI_MACRXPRLPI (1 << 13) /* MAC Rx path received LPI*/
685 #define MVNETA_LPIC1_LPIMM (1 << 2) /* LPI manual mode */
688 /* LPI Control 2 (MVNETA_LPIC2) */
692 #define MVNETA_LPIS_PCSRXPLPIS (1 << 0) /* PCS Rx path LPI status */
694 #define MVNETA_LPIS_MACRXPLPIS (1 << 2)/* MAC Rx path LP idle status */
711 #define MVNETA_PSR_MIISPEED (1 << 2)
715 #define MVNETA_PSR_PRP (1 << 6) /* Port Rx Pause */
717 #define MVNETA_PSR_PDP (1 << 8) /*Port is Doing Back-Pressure*/
726 /* Port CPU to Queue */
727 #define MVNETA_MAXCPU 2
740 /* Tx Buffer Threshold Cross Queue*/
744 /* Rx Buffer Int. Coaleasing Th. Pri. Alrt Q */
748 /* Rx Descriptor Threshold Alert Queue*/
813 #define MVNETA_DLE_LOCAL_SEL_BITS_40BITS (2 << 10)
900 #define MVNETA_TX_CMD_IP_HEADER_LEN_MASK (0x1f << 8) /* IP header len >> 2 */