1 /*-
51 #define NCT_PPOD_LDN 0xf /* LDN used to select Push-Pull/Open-Drain */
63 #define NCT_PIN_IS_VALID(_sc, _p)   ((_p) < (_sc)->npins)
64 #define NCT_PIN_GROUP(_sc, _p)      ((_sc)->pinmap[(_p)].group)
65 #define NCT_PIN_GRPNUM(_sc, _p)     ((_sc)->pinmap[(_p)].grpnum)
66 #define NCT_PIN_BIT(_sc, _p)        ((_sc)->pinmap[(_p)].bit)
98 	uint8_t     ppod_reg; /* Push-Pull/Open-Drain */
130 #define GPIO_LOCK_INIT(_sc)	mtx_init(&(_sc)->mtx,		\
132 #define GPIO_LOCK_DESTROY(_sc)		mtx_destroy(&(_sc)->mtx)
133 #define GPIO_LOCK(_sc)		mtx_lock(&(_sc)->mtx)
134 #define GPIO_UNLOCK(_sc)	mtx_unlock(&(_sc)->mtx)
135 #define GPIO_ASSERT_LOCKED(_sc)	mtx_assert(&(_sc)->mtx, MA_OWNED)
136 #define GPIO_ASSERT_UNLOCKED(_sc)	mtx_assert(&(_sc)->mtx, MA_NOTOWNED)
251 		.descr   = "GPIO on Nuvoton NCT5104D (PC-Engines APU)",
282 		.descr   = "GPIO on Nuvoton NCT5104D (PC-Engines APU3)",
314 		.descr  = "GPIO on Nuvoton NCT6796D-E",
770 	if (grpnum == sc->curgrp)  in nct_io_set_group()
773 	NCT_VERBOSE_PRINTF(sc->dev, "write %s 0x%x ioport %d\n",  in nct_io_set_group()
775 	bus_write_1(sc->iores, NCT_IO_GSR, grpnum);  in nct_io_set_group()
776 	sc->curgrp = grpnum;  in nct_io_set_group()
782 	uint8_t val;  in nct_io_read()  local
786 	val = bus_read_1(sc->iores, reg);  in nct_io_read()
787 	NCT_VERBOSE_PRINTF(sc->dev, "read %s 0x%x ioport %d\n",  in nct_io_read()
788 		io2str(reg), val, reg);  in nct_io_read()
789 	return (val);  in nct_io_read()
793 nct_io_write(struct nct_softc *sc, uint8_t grpnum, uint8_t reg, uint8_t val)  in nct_io_write()  argument
797 	NCT_VERBOSE_PRINTF(sc->dev, "write %s 0x%x ioport %d\n",  in nct_io_write()
798 		io2str(reg), val, reg);  in nct_io_write()
799 	bus_write_1(sc->iores, reg, val);  in nct_io_write()
807 	if (sc->iores != NULL)  in nct_get_ioreg()
810 		iobase = sc->grpmap[grpnum]->iobase;  in nct_get_ioreg()
830 	uint8_t                val;  in nct_read_reg()  local
834 	if (sc->iores != NULL)  in nct_read_reg()
837 	gp  = sc->grpmap[grpnum];  in nct_read_reg()
838 	val = superio_ldn_read(sc->dev, gp->data_ldn, ioreg);  in nct_read_reg()
839 	NCT_VERBOSE_PRINTF(sc->dev, "read %s 0x%x from group GPIO%u ioreg 0x%x\n",  in nct_read_reg()
840 		reg2str(reg), val, grpnum, ioreg);  in nct_read_reg()
841 	return (val);  in nct_read_reg()
849 	uint8_t val;  in nct_get_pin_cache()  local
851 	KASSERT(NCT_PIN_IS_VALID(sc, pin_num), ("%s: invalid pin number %d",  in nct_get_pin_cache()
856 	val   = cache[group];  in nct_get_pin_cache()
857 	return (GET_BIT(val, bit));  in nct_get_pin_cache()
861 nct_write_reg(struct nct_softc *sc, reg_t reg, uint8_t grpnum, uint8_t val)  in nct_write_reg()  argument
868 	if (sc->iores != NULL) {  in nct_write_reg()
869 		nct_io_write(sc, grpnum, ioreg, val);  in nct_write_reg()
873 	gp = sc->grpmap[grpnum];  in nct_write_reg()
874 	superio_ldn_write(sc->dev, gp->data_ldn, ioreg, val);  in nct_write_reg()
876 	NCT_VERBOSE_PRINTF(sc->dev, "write %s 0x%x to group GPIO%u ioreg 0x%x\n",  in nct_write_reg()
877 		reg2str(reg), val, grpnum, ioreg);  in nct_write_reg()
881 nct_set_pin_reg(struct nct_softc *sc, reg_t reg, uint32_t pin_num, bool val)  in nct_set_pin_reg()  argument
890 	    ("%s: invalid pin number %d", __func__, pin_num));  in nct_set_pin_reg()
897 	bitval = (uint8_t)val << bit;  in nct_set_pin_reg()
900 		cache = &sc->cache.ior[group];  in nct_set_pin_reg()
902 		cache = &sc->cache.inv[group];  in nct_set_pin_reg()
911  * Set a pin to input (val is true) or output (val is false) mode.
914 nct_set_pin_input(struct nct_softc *sc, uint32_t pin_num, bool val)  in nct_set_pin_input()  argument
916 	nct_set_pin_reg(sc, REG_IOR, pin_num, val);  in nct_set_pin_input()
920  * Check whether a pin is configured as an input.
925 	return (nct_get_pin_cache(sc, pin_num, sc->cache.ior));  in nct_pin_is_input()
929  * Set a pin to inverted (val is true) or normal (val is false) mode.
932 nct_set_pin_inverted(struct nct_softc *sc, uint32_t pin_num, bool val)  in nct_set_pin_inverted()  argument
934 	nct_set_pin_reg(sc, REG_INV, pin_num, val);  in nct_set_pin_inverted()
940 	return (nct_get_pin_cache(sc, pin_num, sc->cache.inv));  in nct_pin_is_inverted()
944  * Write a value to an output pin.
947  * Writes to a pin in input mode are not allowed here as they cannot
951 nct_write_pin(struct nct_softc *sc, uint32_t pin_num, bool val)  in nct_write_pin()  argument
956 	KASSERT(!nct_pin_is_input(sc, pin_num), ("attempt to write input pin"));  in nct_write_pin()
960 	if (GET_BIT(sc->cache.out_known[group], bit) &&  in nct_write_pin()
961 	    GET_BIT(sc->cache.out[group], bit) == val) {  in nct_write_pin()
962 		/* The pin is already in requested state. */  in nct_write_pin()
965 	sc->cache.out_known[group] |= 1 << bit;  in nct_write_pin()
966 	if (val)  in nct_write_pin()
967 		sc->cache.out[group] |= 1 << bit;  in nct_write_pin()
969 		sc->cache.out[group] &= ~(1 << bit);  in nct_write_pin()
970 	nct_write_reg(sc, REG_DAT, group, sc->cache.out[group]);  in nct_write_pin()
978 	uint8_t            val;  in nct_get_pin_reg()  local
981 	KASSERT(NCT_PIN_IS_VALID(sc, pin_num), ("%s: invalid pin number %d",  in nct_get_pin_reg()
986 	val   = nct_read_reg(sc, reg, group);  in nct_get_pin_reg()
987 	b     = GET_BIT(val, bit);  in nct_get_pin_reg()
991 			NCT_VERBOSE_PRINTF(sc->dev, "read %d from input pin %u<GPIO%u%u>\n",  in nct_get_pin_reg()
994 			NCT_VERBOSE_PRINTF(sc->dev,  in nct_get_pin_reg()
995 				"read %d from output pin %u<GPIO%u%u>, cache miss\n",  in nct_get_pin_reg()
1003  * NB: state of an input pin cannot be cached, of course.
1012 	bool    val;  in nct_read_pin()  local
1021 	if (GET_BIT(sc->cache.out_known[group], bit)) {  in nct_read_pin()
1022 		val = GET_BIT(sc->cache.out[group], bit);  in nct_read_pin()
1024 		NCT_VERBOSE_PRINTF(sc->dev,  in nct_read_pin()
1025 			"read %d from output pin %u<GPIO%u%u>, cache hit\n",  in nct_read_pin()
1026 			val, pin_num, group, bit);  in nct_read_pin()
1028 		return (val);  in nct_read_pin()
1031 	val = nct_get_pin_reg(sc, REG_DAT, pin_num);  in nct_read_pin()
1032 	sc->cache.out_known[group] |= 1 << bit;  in nct_read_pin()
1033 	if (val)  in nct_read_pin()
1034 		sc->cache.out[group] |= 1 << bit;  in nct_read_pin()
1036 		sc->cache.out[group] &= ~(1 << bit);  in nct_read_pin()
1037 	return (val);  in nct_read_pin()
1046 	return (sc->grpmap[group]->ppod_reg);  in nct_ppod_reg()
1061 	outcfg = superio_ldn_read(sc->dev, NCT_PPOD_LDN, reg);  in nct_set_pin_opendrain()
1063 	superio_ldn_write(sc->dev, 0xf, reg, outcfg);  in nct_set_pin_opendrain()
1073 	outcfg = superio_ldn_read(sc->dev, NCT_PPOD_LDN, reg);  in nct_set_pin_pushpull()
1075 	superio_ldn_write(sc->dev, 0xf, reg, outcfg);  in nct_set_pin_pushpull()
1085 	outcfg = superio_ldn_read(sc->dev, NCT_PPOD_LDN, reg);  in nct_pin_is_opendrain()
1099 		if (devid == nctdevp->devid && nctdevp->extid == extid)  in nct_lookup_device()
1127 	device_set_desc(dev, nctdevp->descr);  in nct_probe()
1141 	sc->dev     = dev;  in nct_attach()
1142 	sc->nctdevp = nct_lookup_device(dev);  in nct_attach()
1164 			sc->curgrp = -1;  in nct_attach()
1165 			sc->iorid = 0;  in nct_attach()
1166 			err = bus_set_resource(dev, SYS_RES_IOPORT, sc->iorid,  in nct_attach()
1167 				iobase, 7); /* FIXME NCT6796D-E have 8 registers according to table 18.3. */  in nct_attach()
1169 				sc->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT,  in nct_attach()
1170 					&sc->iorid, RF_ACTIVE);  in nct_attach()
1171 				if (sc->iores == NULL) {  in nct_attach()
1182 		sc->iores, (sc->iores ? "direct" : "indirect"));  in nct_attach()
1185 	for (g = 0, gp = sc->nctdevp->groups; g < sc->nctdevp->ngroups; g++, gp++) {  in nct_attach()
1188 			gp->grpnum, gp->npins, gp->enable_mask, gp->enable_ldn,  in nct_attach()
1189 			gp->enable_reg);  in nct_attach()
1190 		v = superio_ldn_read(dev, gp->enable_ldn, gp->enable_reg);  in nct_attach()
1191 		v |= gp->enable_mask;  in nct_attach()
1192 		superio_ldn_write(dev, gp->enable_ldn, gp->enable_reg, v);  in nct_attach()
1199 	sc->npins = 0;  in nct_attach()
1200 	for (g = 0, gp = sc->nctdevp->groups; g < sc->nctdevp->ngroups; g++, gp++) {  in nct_attach()
1202 		sc->grpmap[gp->grpnum] = gp;  in nct_attach()
1208 		 * the output state of a pin when the pin is switched to input mode and  in nct_attach()
1213 		 * 'out' and 'out_known' bits form a tri-state output cache:  in nct_attach()
1214 		 * |-----+-----------+---------|  in nct_attach()
1216 		 * |-----+-----------+---------|  in nct_attach()
1220 		 * |-----+-----------+---------|  in nct_attach()
1222 		sc->cache.inv[gp->grpnum]       = nct_read_reg(sc, REG_INV, gp->grpnum);  in nct_attach()
1223 		sc->cache.ior[gp->grpnum]       = nct_read_reg(sc, REG_IOR, gp->grpnum);  in nct_attach()
1224 		sc->cache.out[gp->grpnum]       = nct_read_reg(sc, REG_DAT, gp->grpnum);  in nct_attach()
1225 		sc->cache.out_known[gp->grpnum] = ~sc->cache.ior[gp->grpnum];  in nct_attach()
1227 		sc->npins += gp->npins;  in nct_attach()
1228 		for (i = 0; i < gp->npins; i++, pin_num++) {  in nct_attach()
1229 			struct gpio_pin *pin;  in nct_attach()  local
1231 			sc->pinmap[pin_num].group  = gp;  in nct_attach()
1232 			sc->pinmap[pin_num].grpnum = gp->grpnum;  in nct_attach()
1233 			sc->pinmap[pin_num].bit    = gp->pinbits[i];  in nct_attach()
1235 			pin           = &sc->pins[pin_num];  in nct_attach()
1236 			pin->gp_pin   = pin_num;  in nct_attach()
1237 			pin->gp_caps  = gp->caps;  in nct_attach()
1238 			pin->gp_flags = 0;  in nct_attach()
1240 			snprintf(pin->gp_name, GPIOMAXNAME, "GPIO%u%u",  in nct_attach()
1241 				gp->grpnum, gp->pinbits[i]);  in nct_attach()
1244 				pin->gp_flags |= GPIO_PIN_INPUT;  in nct_attach()
1246 				pin->gp_flags |= GPIO_PIN_OUTPUT;  in nct_attach()
1249 				pin->gp_flags |= GPIO_PIN_OPENDRAIN;  in nct_attach()
1251 				pin->gp_flags |= GPIO_PIN_PUSHPULL;  in nct_attach()
1254 				pin->gp_flags |= (GPIO_PIN_INVIN | GPIO_PIN_INVOUT);  in nct_attach()
1257 	NCT_VERBOSE_PRINTF(dev, "%d pins available\n", sc->npins);  in nct_attach()
1261 	sc->busdev = gpiobus_attach_bus(dev);  in nct_attach()
1262 	if (sc->busdev == NULL) {  in nct_attach()
1279 	if (sc->iores != NULL)  in nct_detach()
1280 		bus_release_resource(dev, SYS_RES_IOPORT, sc->iorid, sc->iores);  in nct_detach()
1294 	return (sc->busdev);  in nct_gpio_get_bus()
1303 	*maxpin = sc->npins - 1;  in nct_gpio_pin_max()
1318 	if ((sc->pins[pin_num].gp_flags & GPIO_PIN_OUTPUT) == 0) {  in nct_gpio_pin_set()
1358 	if ((sc->pins[pin_num].gp_flags & GPIO_PIN_OUTPUT) == 0) {  in nct_gpio_pin_toggle()
1384 	*caps = sc->pins[pin_num].gp_caps;  in nct_gpio_pin_getcaps()
1402 	*flags = sc->pins[pin_num].gp_flags;  in nct_gpio_pin_getflags()
1420 	memcpy(name, sc->pins[pin_num].gp_name, GPIOMAXNAME);  in nct_gpio_pin_getname()
1430 	struct gpio_pin *pin;  in nct_gpio_pin_setflags()  local
1437 	pin = &sc->pins[pin_num];  in nct_gpio_pin_setflags()
1438 	if ((flags & pin->gp_caps) != flags)  in nct_gpio_pin_setflags()
1460 		pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);  in nct_gpio_pin_setflags()
1461 		pin->gp_flags |= flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);  in nct_gpio_pin_setflags()
1467 		pin->gp_flags |= (GPIO_PIN_INVIN | GPIO_PIN_INVOUT);  in nct_gpio_pin_setflags()
1470 		pin->gp_flags &= ~(GPIO_PIN_INVIN | GPIO_PIN_INVOUT);  in nct_gpio_pin_setflags()
1479 		pin->gp_flags &= ~(GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL);  in nct_gpio_pin_setflags()
1480 		pin->gp_flags |=  in nct_gpio_pin_setflags()