Lines Matching +full:0 +full:x30
51 #define NCT_PPOD_LDN 0xf /* LDN used to select Push-Pull/Open-Drain */
54 #define NCT_IO_GSR 0 /* Group Select */
79 } while (0)
86 REG_IOR = 0,
112 uint8_t ior[NCT_MAX_GROUP + 1]; /* direction, 1: input 0: output */
152 .devid = 0xa025,
158 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
159 .enable_ldn = 0x09,
160 .enable_reg = 0x30,
161 .enable_mask = 0x01,
162 .data_ldn = 0x09,
163 .ppod_reg = 0xe0, /* FIXME Need to check for this group. */
166 .iobase = 0xe3,
170 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
171 .enable_ldn = 0x09,
172 .enable_reg = 0x30,
173 .enable_mask = 0x02,
174 .data_ldn = 0x09,
175 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
178 .iobase = 0xf0,
182 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
183 .enable_ldn = 0x09,
184 .enable_reg = 0x30,
185 .enable_mask = 0x04,
186 .data_ldn = 0x09,
187 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
190 .iobase = 0xf4,
194 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
195 .enable_ldn = 0x09,
196 .enable_reg = 0x30,
197 .enable_mask = 0x08,
198 .data_ldn = 0x09,
199 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
202 .iobase = 0xe0,
206 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
207 .enable_ldn = 0x07,
208 .enable_reg = 0x30,
209 .enable_mask = 0x01,
210 .data_ldn = 0x07,
211 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
214 .iobase = 0xf4,
219 .devid = 0x1061,
224 .grpnum = 0,
225 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
226 .enable_ldn = 0x07,
227 .enable_reg = 0x30,
228 .enable_mask = 0x01,
229 .data_ldn = 0x07,
230 .ppod_reg = 0xe0,
233 .iobase = 0xe0,
237 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
238 .enable_ldn = 0x07,
239 .enable_reg = 0x30,
240 .enable_mask = 0x02,
241 .data_ldn = 0x07,
242 .ppod_reg = 0xe1,
245 .iobase = 0xe4,
250 .devid = 0xc452, /* FIXME Conflict with Nuvoton NCT6106D. See NetBSD's nct_match. */
255 .grpnum = 0,
256 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
257 .enable_ldn = 0x07,
258 .enable_reg = 0x30,
259 .enable_mask = 0x01,
260 .data_ldn = 0x07,
261 .ppod_reg = 0xe0,
264 .iobase = 0xe0,
268 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
269 .enable_ldn = 0x07,
270 .enable_reg = 0x30,
271 .enable_mask = 0x02,
272 .data_ldn = 0x07,
273 .ppod_reg = 0xe1,
276 .iobase = 0xe4,
281 .devid = 0xc453,
286 .grpnum = 0,
287 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
288 .enable_ldn = 0x07,
289 .enable_reg = 0x30,
290 .enable_mask = 0x01,
291 .data_ldn = 0x07,
292 .ppod_reg = 0xe0,
295 .iobase = 0xe0,
299 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
300 .enable_ldn = 0x07,
301 .enable_reg = 0x30,
302 .enable_mask = 0x02,
303 .data_ldn = 0x07,
304 .ppod_reg = 0xe1,
307 .iobase = 0xe4,
312 .devid = 0xd42a,
318 .grpnum = 0,
319 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
320 .enable_ldn = 0x08,
321 .enable_reg = 0x30,
322 .enable_mask = 0x02,
323 .data_ldn = 0x08,
324 .ppod_reg = 0xe0, /* FIXME Need to check for this group. */
327 .iobase = 0xe0,
331 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
332 .enable_ldn = 0x08,
333 .enable_reg = 0x30,
334 .enable_mask = 0x80,
335 .data_ldn = 0x08,
336 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
339 .iobase = 0xf0,
343 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
344 .enable_ldn = 0x09,
345 .enable_reg = 0x30,
346 .enable_mask = 0x01,
347 .data_ldn = 0x09,
348 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
351 .iobase = 0xe0,
355 .pinbits = { 0, 1, 2, 3, 4, 5, 6 },
356 .enable_ldn = 0x09,
357 .enable_reg = 0x30,
358 .enable_mask = 0x02,
359 .data_ldn = 0x09,
360 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
363 .iobase = 0xe4,
367 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
368 .enable_ldn = 0x09,
369 .enable_reg = 0x30,
370 .enable_mask = 0x04,
371 .data_ldn = 0x09,
372 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
375 .iobase = 0xf0, /* FIXME Page 344 say "F0~F2, E8",
380 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
381 .enable_ldn = 0x09,
382 .enable_reg = 0x30,
383 .enable_mask = 0x08,
384 .data_ldn = 0x09,
385 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
388 .iobase = 0xf4,
392 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
393 .enable_ldn = 0x07,
394 .enable_reg = 0x30,
395 .enable_mask = 0x01,
396 .data_ldn = 0x07,
397 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
400 .iobase = 0xf4,
404 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
405 .enable_ldn = 0x07,
406 .enable_reg = 0x30,
407 .enable_mask = 0x02,
408 .data_ldn = 0x07,
409 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
412 .iobase = 0xe0,
416 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
417 .enable_ldn = 0x07,
418 .enable_reg = 0x30,
419 .enable_mask = 0x04,
420 .data_ldn = 0x07,
421 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
424 .iobase = 0xe4,
428 .pinbits = { 0, 1, 2, 3 },
429 .enable_ldn = 0x07,
430 .enable_reg = 0x30,
431 .enable_mask = 0x08,
432 .data_ldn = 0x07,
433 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
436 .iobase = 0xe8,
441 .devid = 0xd42a,
448 .pinbits = { 0, 1, 2, 3, 4, 5, 6 },
449 .enable_ldn = 0x09,
450 .enable_reg = 0x30,
451 .enable_mask = 0x01,
452 .data_ldn = 0x09,
453 .ppod_reg = 0xe1,
456 .iobase = 0xe0,
461 .enable_ldn = 0x09,
462 .enable_reg = 0x30,
463 .enable_mask = 0x02,
464 .data_ldn = 0x09,
465 .ppod_reg = 0xe2,
468 .iobase = 0xe4,
472 .pinbits = { 0, 2, 6, 7 },
473 .enable_ldn = 0x09,
474 .enable_reg = 0x30,
475 .enable_mask = 0x08,
476 .data_ldn = 0x09,
477 .ppod_reg = 0xe4,
480 .iobase = 0xf4,
485 .enable_ldn = 0x07,
486 .enable_reg = 0x30,
487 .enable_mask = 0x02,
488 .data_ldn = 0x07,
489 .ppod_reg = 0xe6,
492 .iobase = 0xe0,
496 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
497 .enable_ldn = 0x07,
498 .enable_reg = 0x30,
499 .enable_mask = 0x04,
500 .data_ldn = 0x07,
501 .ppod_reg = 0xe7,
504 .iobase = 0xe4,
508 .pinbits = { 0, 2 },
509 .enable_ldn = 0x07,
510 .enable_reg = 0x30,
511 .enable_mask = 0x08,
512 .data_ldn = 0x07,
513 .ppod_reg = 0xea,
516 .iobase = 0xe8,
521 .devid = 0xc562,
526 .grpnum = 0,
527 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
528 .enable_ldn = 0x08,
529 .enable_reg = 0x30,
530 .enable_mask = 0x01,
531 .data_ldn = 0x08,
532 .ppod_reg = 0xe0, /* FIXME Need to check for this group. */
535 .iobase = 0xe0,
539 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
540 .enable_ldn = 0x09,
541 .enable_reg = 0x30,
542 .enable_mask = 0x01,
543 .data_ldn = 0x08,
544 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
547 .iobase = 0xf0,
551 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
552 .enable_ldn = 0x09,
553 .enable_reg = 0x30,
554 .enable_mask = 0x01,
555 .data_ldn = 0x09,
556 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
559 .iobase = 0xe0,
563 .pinbits = { 0, 1, 2, 3, 4, 5, 6 },
564 .enable_ldn = 0x09,
565 .enable_reg = 0x30,
566 .enable_mask = 0x02,
567 .data_ldn = 0x09,
568 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
571 .iobase = 0xe4,
575 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
576 .enable_ldn = 0x09,
577 .enable_reg = 0x30,
578 .enable_mask = 0x04,
579 .data_ldn = 0x09,
580 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
583 .iobase = 0xf0,
587 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
588 .enable_ldn = 0x09,
589 .enable_reg = 0x30,
590 .enable_mask = 0x08,
591 .data_ldn = 0x09,
592 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
595 .iobase = 0xf4,
599 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
600 .enable_ldn = 0x09,
601 .enable_reg = 0x30,
602 .enable_mask = 0x01,
603 .data_ldn = 0x07,
604 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
607 .iobase = 0xf4,
611 .pinbits = { 0, 1, 2, 3, 4, 5, 6 },
612 .enable_ldn = 0x09,
613 .enable_reg = 0x30,
614 .enable_mask = 0x02,
615 .data_ldn = 0x07,
616 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
619 .iobase = 0xe0,
623 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
624 .enable_ldn = 0x09,
625 .enable_reg = 0x30,
626 .enable_mask = 0x04,
627 .data_ldn = 0x07,
628 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
631 .iobase = 0xe4,
636 .devid = 0xd282,
641 .grpnum = 0,
642 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
643 .enable_ldn = 0x07,
644 .enable_reg = 0x30,
645 .enable_mask = 0x01,
646 .data_ldn = 0x07,
647 .ppod_reg = 0xe0,
650 .iobase = 0xe0,
654 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
655 .enable_ldn = 0x07,
656 .enable_reg = 0x30,
657 .enable_mask = 0x02,
658 .data_ldn = 0x07,
659 .ppod_reg = 0xe1,
662 .iobase = 0xe4,
666 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
667 .enable_ldn = 0x07,
668 .enable_reg = 0x30,
669 .enable_mask = 0x04,
670 .data_ldn = 0x07,
671 .ppod_reg = 0xe1,
674 .iobase = 0xe8,
678 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
679 .enable_ldn = 0x07,
680 .enable_reg = 0x30,
681 .enable_mask = 0x08,
682 .data_ldn = 0x07,
683 .ppod_reg = 0xe1,
686 .iobase = 0xec,
690 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
691 .enable_ldn = 0x07,
692 .enable_reg = 0x30,
693 .enable_mask = 0x10,
694 .data_ldn = 0x07,
695 .ppod_reg = 0xe1,
698 .iobase = 0xf0,
702 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
703 .enable_ldn = 0x07,
704 .enable_reg = 0x30,
705 .enable_mask = 0x20,
706 .data_ldn = 0x07,
707 .ppod_reg = 0xe1,
710 .iobase = 0xf4,
714 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
715 .enable_ldn = 0x07,
716 .enable_reg = 0x30,
717 .enable_mask = 0x40,
718 .data_ldn = 0x07,
719 .ppod_reg = 0xe1,
722 .iobase = 0xf8,
726 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
727 .enable_ldn = 0x07,
728 .enable_reg = 0x30,
729 .enable_mask = 0x80,
730 .data_ldn = 0x07,
731 .ppod_reg = 0xe1,
734 .iobase = 0xfc,
738 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
739 .enable_ldn = 0x09,
740 .enable_reg = 0x30,
741 .enable_mask = 0x01,
742 .data_ldn = 0x09,
743 .ppod_reg = 0xe1,
746 .iobase = 0xf0,
773 NCT_VERBOSE_PRINTF(sc->dev, "write %s 0x%x ioport %d\n", in nct_io_set_group()
787 NCT_VERBOSE_PRINTF(sc->dev, "read %s 0x%x ioport %d\n", in nct_io_read()
797 NCT_VERBOSE_PRINTF(sc->dev, "write %s 0x%x ioport %d\n", in nct_io_write()
839 NCT_VERBOSE_PRINTF(sc->dev, "read %s 0x%x from group GPIO%u ioreg 0x%x\n", in nct_read_reg()
876 NCT_VERBOSE_PRINTF(sc->dev, "write %s 0x%x to group GPIO%u ioreg 0x%x\n", in nct_write_reg()
1063 superio_ldn_write(sc->dev, 0xf, reg, outcfg); in nct_set_pin_opendrain()
1075 superio_ldn_write(sc->dev, 0xf, reg, outcfg); in nct_set_pin_pushpull()
1098 for (i = 0, nctdevp = nct_devices; i < nitems(nct_devices); i++, nctdevp++) { in nct_lookup_device()
1114 NCT_VERBOSE_PRINTF(dev, "ldn 0x%x not a Nuvoton device\n", ldn); in nct_probe()
1118 NCT_VERBOSE_PRINTF(dev, "ldn 0x%x not a GPIO device\n", ldn); in nct_probe()
1124 NCT_VERBOSE_PRINTF(dev, "ldn 0x%x not supported\n", ldn); in nct_probe()
1144 flags = 0; in nct_attach()
1147 if ((flags & NCT_PREFER_INDIRECT_CHANNEL) == 0) { in nct_attach()
1156 iobase = 0; in nct_attach()
1160 if (iobase != 0 && iobase != 0xffff) { in nct_attach()
1165 sc->iorid = 0; in nct_attach()
1168 if (err == 0) { in nct_attach()
1185 for (g = 0, gp = sc->nctdevp->groups; g < sc->nctdevp->ngroups; g++, gp++) { in nct_attach()
1187 "GPIO%d: %d pins, enable with mask 0x%x via ldn 0x%x reg 0x%x\n", in nct_attach()
1198 pin_num = 0; in nct_attach()
1199 sc->npins = 0; in nct_attach()
1200 for (g = 0, gp = sc->nctdevp->groups; g < sc->nctdevp->ngroups; g++, gp++) { in nct_attach()
1217 * | X | 0 | invalid | in nct_attach()
1218 * | 0 | 1 | 0 | in nct_attach()
1228 for (i = 0; i < gp->npins; i++, pin_num++) { in nct_attach()
1238 pin->gp_flags = 0; in nct_attach()
1269 return (0); in nct_attach()
1285 return (0); in nct_detach()
1305 return (0); in nct_gpio_pin_max()
1319 if ((sc->pins[pin_num].gp_flags & GPIO_PIN_OUTPUT) == 0) { in nct_gpio_pin_set()
1326 return (0); in nct_gpio_pin_set()
1344 return (0); in nct_gpio_pin_get()
1359 if ((sc->pins[pin_num].gp_flags & GPIO_PIN_OUTPUT) == 0) { in nct_gpio_pin_toggle()
1364 nct_write_pin(sc, pin_num, 0); in nct_gpio_pin_toggle()
1370 return (0); in nct_gpio_pin_toggle()
1388 return (0); in nct_gpio_pin_getcaps()
1406 return (0); in nct_gpio_pin_getflags()
1424 return (0); in nct_gpio_pin_getname()
1459 if ((flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) != 0) { in nct_gpio_pin_setflags()
1460 nct_set_pin_input(sc, pin_num, (flags & GPIO_PIN_INPUT) != 0); in nct_gpio_pin_setflags()
1466 if ((flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) != 0) { in nct_gpio_pin_setflags()
1470 nct_set_pin_inverted(sc, pin_num, 0); in nct_gpio_pin_setflags()
1475 if ((flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) != 0) { in nct_gpio_pin_setflags()
1486 return (0); in nct_gpio_pin_setflags()