Lines Matching +full:0 +full:xe000000
99 static int mxge_force_firmware = 0;
103 static int mxge_verbose = 0;
107 static int mxge_always_promisc = 0;
109 static int mxge_throttle = 0;
140 DRIVER_MODULE(mxge, pci, mxge_driver, 0, 0);
172 return 0; in mxge_probe()
188 if (err != 0) { in mxge_enable_wc()
191 sc->wc = 0; in mxge_enable_wc()
201 if (error == 0) { in mxge_dmamap_callback()
215 boundary = 0; in mxge_dma_alloc()
235 if (err != 0) { in mxge_dma_alloc()
244 if (err != 0) { in mxge_dma_alloc()
252 (void *)&dma->bus_addr, 0); in mxge_dma_alloc()
253 if (err != 0) { in mxge_dma_alloc()
257 return 0; in mxge_dma_alloc()
276 * SN=x\0
277 * MAC=x:x:x:x:x:x\0
278 * PC=text\0
289 found_mac = 0; in mxge_parse_strings()
290 found_sn2 = 0; in mxge_parse_strings()
291 while (*ptr != '\0') { in mxge_parse_strings()
292 if (strncmp(ptr, "MAC=", 4) == 0) { in mxge_parse_strings()
294 for (i = 0;;) { in mxge_parse_strings()
305 } else if (strncmp(ptr, "PC=", 3) == 0) { in mxge_parse_strings()
309 } else if (!found_sn2 && (strncmp(ptr, "SN=", 3) == 0)) { in mxge_parse_strings()
313 } else if (strncmp(ptr, "SN2=", 4) == 0) { in mxge_parse_strings()
320 while (*ptr++ != '\0') {} in mxge_parse_strings()
324 return 0; in mxge_parse_strings()
355 if (vendor_id != 0x10de) in mxge_enable_nvidia_ecrc()
358 base = 0; in mxge_enable_nvidia_ecrc()
360 if (device_id == 0x005d) { in mxge_enable_nvidia_ecrc()
362 base = 0xe0000000UL; in mxge_enable_nvidia_ecrc()
363 } else if (device_id >= 0x0374 && device_id <= 0x378) { in mxge_enable_nvidia_ecrc()
365 mcp55 = pci_find_bsf(0, 0, 0); in mxge_enable_nvidia_ecrc()
367 0x10de == pci_read_config(mcp55, PCIR_VENDOR, 2) && in mxge_enable_nvidia_ecrc()
368 0x0369 == pci_read_config(mcp55, PCIR_DEVICE, 2)) { in mxge_enable_nvidia_ecrc()
369 word = pci_read_config(mcp55, 0x90, 2); in mxge_enable_nvidia_ecrc()
370 base = ((unsigned long)word & 0x7ffeU) << 25; in mxge_enable_nvidia_ecrc()
378 config read/write beyond 0xff will access the config space in mxge_enable_nvidia_ecrc()
383 #if 0 in mxge_enable_nvidia_ecrc()
386 val = pci_read_config(pdev, 0x178, 4); in mxge_enable_nvidia_ecrc()
387 if (val != 0xffffffff) { in mxge_enable_nvidia_ecrc()
388 val |= 0x40; in mxge_enable_nvidia_ecrc()
389 pci_write_config(pdev, 0x178, val, 4); in mxge_enable_nvidia_ecrc()
395 * opteron/nvidia class machine the 0xe000000 mapping is in mxge_enable_nvidia_ecrc()
413 + 0x00100000UL * (unsigned long)bus in mxge_enable_nvidia_ecrc()
414 + 0x00001000UL * (unsigned long)(func in mxge_enable_nvidia_ecrc()
431 device_printf(sc->dev, "mapping failed: 0x%x:0x%x\n", in mxge_enable_nvidia_ecrc()
437 ptr32 = (uint32_t*)(cfgptr + 0x178); in mxge_enable_nvidia_ecrc()
440 if (val == 0xffffffff) { in mxge_enable_nvidia_ecrc()
445 *ptr32 = val | 0x40; in mxge_enable_nvidia_ecrc()
486 cmd.data2 = len * 0x10000; in mxge_dma_test()
488 if (status != 0) { in mxge_dma_test()
493 (cmd.data0 & 0xffff); in mxge_dma_test()
496 cmd.data2 = len * 0x1; in mxge_dma_test()
498 if (status != 0) { in mxge_dma_test()
503 (cmd.data0 & 0xffff); in mxge_dma_test()
507 cmd.data2 = len * 0x10001; in mxge_dma_test()
509 if (status != 0) { in mxge_dma_test()
514 (cmd.data0 & 0xffff); in mxge_dma_test()
517 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST) in mxge_dma_test()
555 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { in mxge_firmware_probe()
556 pectl = pci_read_config(dev, reg + 0x8, 2); in mxge_firmware_probe()
558 device_printf(dev, "Max Read Req. size != 4k (0x%x\n", in mxge_firmware_probe()
570 if (status != 0) { in mxge_firmware_probe()
584 return 0; in mxge_firmware_probe()
586 if (status == 0) in mxge_firmware_probe()
587 return 0; /* keep the aligned firmware */ in mxge_firmware_probe()
600 int aligned = 0; in mxge_select_firmware()
606 if (force_firmware != 0) { in mxge_select_firmware()
610 aligned = 0; in mxge_select_firmware()
620 if (sc->link_width != 0 && sc->link_width <= 4) { in mxge_select_firmware()
628 if (0 == mxge_firmware_probe(sc)) in mxge_select_firmware()
629 return 0; in mxge_select_firmware()
639 return (mxge_load_firmware(sc, 0)); in mxge_select_firmware()
647 device_printf(sc->dev, "Bad firmware type: 0x%x\n", in mxge_validate_firmware()
668 return 0; in mxge_validate_firmware()
729 if (status != 0) in mxge_load_firmware_helper()
733 for (i = 0; i < fw_len; i += 256) { in mxge_load_firmware_helper()
743 status = 0; in mxge_load_firmware_helper()
771 *confirm = 0; in mxge_dummy_rdma()
781 buf[0] = htobe32(dma_high); /* confirm addr MSW */ in mxge_dummy_rdma()
783 buf[2] = htobe32(0xffffffff); /* confirm data */ in mxge_dummy_rdma()
796 i = 0; in mxge_dummy_rdma()
797 while (*confirm != 0xffffffff && i < 20) { in mxge_dummy_rdma()
801 if (*confirm != 0xffffffff) { in mxge_dummy_rdma()
802 device_printf(sc->dev, "dummy rdma %s failed (%p = 0x%x)", in mxge_dummy_rdma()
817 int err, sleep_total = 0; in mxge_send_cmd()
832 response->result = 0xffffffff; in mxge_send_cmd()
838 for (sleep_total = 0; sleep_total < 20; sleep_total++) { in mxge_send_cmd()
843 case 0: in mxge_send_cmd()
845 err = 0; in mxge_send_cmd()
847 case 0xffffffff: in mxge_send_cmd()
966 return 0; in mxge_load_firmware()
970 *confirm = 0; in mxge_load_firmware()
980 buf[0] = htobe32(dma_high); /* confirm addr MSW */ in mxge_load_firmware()
982 buf[2] = htobe32(0xffffffff); /* confirm data */ in mxge_load_firmware()
992 buf[6] = htobe32(0); /* where to jump to */ in mxge_load_firmware()
999 i = 0; in mxge_load_firmware()
1000 while (*confirm != 0xffffffff && i < 20) { in mxge_load_firmware()
1006 if (*confirm != 0xffffffff) { in mxge_load_firmware()
1007 device_printf(sc->dev,"handoff failed (%p = 0x%x)", in mxge_load_firmware()
1012 return 0; in mxge_load_firmware()
1022 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16) in mxge_update_mac_address()
1049 return 0; in mxge_change_pause()
1084 if (ctx->error != 0) in mxge_add_maddr()
1085 return (0); in mxge_add_maddr()
1110 if (err != 0) { in mxge_set_multicast_list()
1126 if (err != 0) { in mxge_set_multicast_list()
1135 ctx.error = 0; in mxge_set_multicast_list()
1137 if (ctx.error != 0) { in mxge_set_multicast_list()
1146 if (err != 0) { in mxge_set_multicast_list()
1163 cmd.data0 = 0; in mxge_max_mtu()
1166 if (status == 0) in mxge_max_mtu()
1184 memset(&cmd, 0, sizeof (cmd)); in mxge_reset()
1186 if (status != 0) { in mxge_reset()
1203 * slice 0. It must also be called *after* in mxge_reset()
1212 if (status != 0) { in mxge_reset()
1226 if (status != 0) { in mxge_reset()
1235 for (slice = 0; slice < sc->num_slices; slice++) { in mxge_reset()
1237 memset(rx_done->entry, 0, sc->rx_ring_size); in mxge_reset()
1258 if (status != 0) { in mxge_reset()
1268 for (slice = 0; slice < sc->num_slices; slice++) { in mxge_reset()
1272 /* reset mcp/driver shared state back to 0 */ in mxge_reset()
1273 ss->rx_done.idx = 0; in mxge_reset()
1274 ss->rx_done.cnt = 0; in mxge_reset()
1275 ss->tx.req = 0; in mxge_reset()
1276 ss->tx.done = 0; in mxge_reset()
1277 ss->tx.pkt_done = 0; in mxge_reset()
1278 ss->tx.queue_active = 0; in mxge_reset()
1279 ss->tx.activate = 0; in mxge_reset()
1280 ss->tx.deactivate = 0; in mxge_reset()
1281 ss->tx.wake = 0; in mxge_reset()
1282 ss->tx.defrag = 0; in mxge_reset()
1283 ss->tx.stall = 0; in mxge_reset()
1284 ss->rx_big.cnt = 0; in mxge_reset()
1285 ss->rx_small.cnt = 0; in mxge_reset()
1286 ss->lc.lro_bad_csum = 0; in mxge_reset()
1287 ss->lc.lro_queued = 0; in mxge_reset()
1288 ss->lc.lro_flushed = 0; in mxge_reset()
1320 if (err != 0) { in mxge_change_throttle()
1325 return 0; in mxge_change_throttle()
1333 if (err == 0) in mxge_change_throttle()
1349 if (err != 0) { in mxge_change_intr_coal()
1353 return 0; in mxge_change_intr_coal()
1355 if (intr_coal_delay == 0 || intr_coal_delay > 1000*1000) in mxge_change_intr_coal()
1376 if (err != 0) { in mxge_change_flow_control()
1380 return 0; in mxge_change_flow_control()
1411 for (slice = 0; slice < sc->num_slices; slice++) { in mxge_rem_sysctls()
1434 fw = sc->ss[0].fw_stats; in mxge_add_sysctls()
1440 0, "firmware version"); in mxge_add_sysctls()
1444 0, "serial number"); in mxge_add_sysctls()
1448 0, "product_code"); in mxge_add_sysctls()
1452 0, "tx_boundary"); in mxge_add_sysctls()
1456 0, "tx_boundary"); in mxge_add_sysctls()
1460 0, "write combining PIO?"); in mxge_add_sysctls()
1464 0, "DMA Read speed in MB/s"); in mxge_add_sysctls()
1468 0, "DMA Write speed in MB/s"); in mxge_add_sysctls()
1472 0, "DMA concurrent Read/Write speed in MB/s"); in mxge_add_sysctls()
1476 0, "Number of times NIC was reset"); in mxge_add_sysctls()
1481 sc, 0, mxge_change_intr_coal, "I", in mxge_add_sysctls()
1485 "throttle", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, in mxge_add_sysctls()
1490 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, in mxge_add_sysctls()
1497 0, "Wait for IRQ line to go low in ihandler"); in mxge_add_sysctls()
1503 &fw->link_up, 0, mxge_handle_be32, "I", "link up"); in mxge_add_sysctls()
1506 &fw->rdma_tags_available, 0, mxge_handle_be32, "I", in mxge_add_sysctls()
1510 &fw->dropped_bad_crc32, 0, mxge_handle_be32, "I", in mxge_add_sysctls()
1514 &fw->dropped_bad_phy, 0, mxge_handle_be32, "I", "dropped_bad_phy"); in mxge_add_sysctls()
1518 &fw->dropped_link_error_or_filtered, 0, mxge_handle_be32, "I", in mxge_add_sysctls()
1523 &fw->dropped_link_overflow, 0, mxge_handle_be32, "I", in mxge_add_sysctls()
1528 &fw->dropped_multicast_filtered, 0, mxge_handle_be32, "I", in mxge_add_sysctls()
1533 &fw->dropped_no_big_buffer, 0, mxge_handle_be32, "I", in mxge_add_sysctls()
1538 &fw->dropped_no_small_buffer, 0, mxge_handle_be32, "I", in mxge_add_sysctls()
1543 &fw->dropped_overrun, 0, mxge_handle_be32, "I", in mxge_add_sysctls()
1547 &fw->dropped_pause, 0, mxge_handle_be32, "I", "dropped_pause"); in mxge_add_sysctls()
1550 &fw->dropped_runt, 0, mxge_handle_be32, "I", "dropped_runt"); in mxge_add_sysctls()
1555 &fw->dropped_unicast_filtered, 0, mxge_handle_be32, "I", in mxge_add_sysctls()
1562 0, "verbose printing"); in mxge_add_sysctls()
1568 "slice", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, ""); in mxge_add_sysctls()
1570 for (slice = 0; slice < sc->num_slices; slice++) { in mxge_add_sysctls()
1578 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, ""); in mxge_add_sysctls()
1583 0, "rx_small_cnt"); in mxge_add_sysctls()
1587 0, "rx_small_cnt"); in mxge_add_sysctls()
1590 0, "number of lro merge queues flushed"); in mxge_add_sysctls()
1594 0, "number of bad csums preventing LRO"); in mxge_add_sysctls()
1598 0, "number of frames appended to lro merge" in mxge_add_sysctls()
1604 0, "tx_req"); in mxge_add_sysctls()
1609 0, "tx_done"); in mxge_add_sysctls()
1613 0, "tx_done"); in mxge_add_sysctls()
1617 0, "tx_stall"); in mxge_add_sysctls()
1621 0, "tx_wake"); in mxge_add_sysctls()
1625 0, "tx_defrag"); in mxge_add_sysctls()
1629 0, "tx_queue_active"); in mxge_add_sysctls()
1633 0, "tx_activate"); in mxge_add_sysctls()
1637 0, "tx_deactivate"); in mxge_add_sysctls()
1680 src->flags = 0; in mxge_submit_req()
1686 for (i = 0; i < (cnt - 1); i += 2) { in mxge_submit_req()
1696 i = 0; in mxge_submit_req()
1744 m_copydata(m, 0, pi->ip_off + sizeof(*pi->ip), in mxge_parse_tx()
1750 return 0; in mxge_parse_tx()
1754 m_copydata(m, 0, pi->ip_off + pi->ip_hlen + in mxge_parse_tx()
1764 m_copydata(m, 0, pi->ip_off + sizeof(*pi->ip6), in mxge_parse_tx()
1768 nxt = 0; in mxge_parse_tx()
1775 return 0; in mxge_parse_tx()
1782 m_copydata(m, 0, pi->ip_off + pi->ip_hlen + in mxge_parse_tx()
1792 return 0; in mxge_parse_tx()
1822 if (__predict_false((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_TCP_IPV6)) == 0)) { in mxge_encap_tso()
1830 #if (CSUM_TCP_IPV6 != 0) && defined(INET6) in mxge_encap_tso()
1834 IPPROTO_TCP, 0); in mxge_encap_tso()
1866 cnt = 0; in mxge_encap_tso()
1867 rdma_count = 0; in mxge_encap_tso()
1872 * to 0 after a segment cut. in mxge_encap_tso()
1897 if (__predict_true(cum_len >= 0)) { in mxge_encap_tso()
1901 next_is_first = (cum_len_next == 0); in mxge_encap_tso()
1907 } else if (cum_len_next >= 0) { in mxge_encap_tso()
1910 cum_len_next = 0; in mxge_encap_tso()
1921 req->pad = 0; in mxge_encap_tso()
1934 if (cksum_offset != 0 && !pi->ip6) { in mxge_encap_tso()
1938 cksum_offset = 0; in mxge_encap_tso()
1956 if ((ss->sc->num_slices > 1) && tx->queue_active == 0) { in mxge_encap_tso()
2019 struct mxge_pkt_info pi = {0,0,0,0}; in mxge_encap()
2064 if (__predict_false(err != 0)) { in mxge_encap()
2082 cksum_offset = 0; in mxge_encap()
2083 pseudo_hdr_offset = 0; in mxge_encap()
2098 odd_flag = 0; in mxge_encap()
2104 cum_len = 0; in mxge_encap()
2107 for (i = 0; i < cnt; i++) { in mxge_encap()
2117 cksum_offset = 0; in mxge_encap()
2119 req->pad = 0; /* complete solid 16-byte block */ in mxge_encap()
2125 req->flags = 0; in mxge_encap()
2136 req->cksum_offset = 0; in mxge_encap()
2138 req->pad = 0; /* complete solid 16-byte block */ in mxge_encap()
2144 tx->req_list[0].rdma_count = cnt; in mxge_encap()
2145 #if 0 in mxge_encap()
2147 for (i = 0; i < cnt; i++) { in mxge_encap()
2148 printf("%d: addr: 0x%x 0x%x len:%d pso%d," in mxge_encap()
2149 "cso:%d, flags:0x%x, rdma:%d\n", in mxge_encap()
2162 if ((ss->sc->num_slices > 1) && tx->queue_active == 0) { in mxge_encap()
2187 for (slice = 0; slice < sc->num_slices; slice++) { in mxge_qflush()
2221 if (((ss->if_drv_flags & IFF_DRV_OACTIVE) == 0) in mxge_start_locked()
2252 } else if ((err = drbr_enqueue(ifp, tx->br, m)) != 0) { in mxge_transmit_locked()
2257 return (0); in mxge_transmit_locked()
2266 int err = 0; in mxge_transmit()
2292 ss = &sc->ss[0]; in mxge_start()
2312 src->addr_low = 0xffffffff; in mxge_submit_8rx()
2339 if (err != 0) { in mxge_get_buf_small()
2372 if (err != 0) { in mxge_get_buf_big()
2383 for (i = 0; i < rx->nbufs; i++) { in mxge_get_buf_big()
2400 csum = 0; in mxge_csum_generic()
2401 while (len > 0) { in mxge_csum_generic()
2406 csum = (csum >> 16) + (csum & 0xffff); in mxge_csum_generic()
2407 csum = (csum >> 16) + (csum & 0xffff); in mxge_csum_generic()
2440 csum = (csum >> 16) + (csum & 0xFFFF); in mxge_rx_csum6()
2441 csum = (csum >> 16) + (csum & 0xFFFF); in mxge_rx_csum6()
2444 c ^= 0xffff; in mxge_rx_csum6()
2474 if ((cap & IFCAP_RXCSUM) == 0) in mxge_rx_csum()
2482 c ^= 0xffff; in mxge_rx_csum()
2487 if ((cap & IFCAP_RXCSUM_IPV6) == 0) in mxge_rx_csum()
2517 (*csum) = ((*csum) >> 16) + ((*csum) & 0xFFFF); in mxge_vlan_tag_remove()
2518 (*csum) = ((*csum) >> 16) + ((*csum) & 0xFFFF); in mxge_vlan_tag_remove()
2605 (0 == mxge_rx_csum(m, csum))) { in mxge_rx_done_big()
2607 m->m_pkthdr.csum_data = 0xffff; in mxge_rx_done_big()
2612 if (lro && (0 == tcp_lro_rx(&ss->lc, m, 0))) in mxge_rx_done_big()
2673 (0 == mxge_rx_csum(m, csum))) { in mxge_rx_done_small()
2675 m->m_pkthdr.csum_data = 0xffff; in mxge_rx_done_small()
2680 if (lro && (0 == tcp_lro_rx(&ss->lc, m, csum))) in mxge_rx_done_small()
2692 int limit = 0; in mxge_clean_rx_done()
2698 while (rx_done->entry[rx_done->idx].length != 0) { in mxge_clean_rx_done()
2700 rx_done->entry[rx_done->idx].length = 0; in mxge_clean_rx_done()
2747 tx->info[idx].flag = 0; in mxge_tx_done()
2767 tx->queue_active = 0; in mxge_tx_done()
2777 {IFM_10G_CX4, 0x7f, "10GBASE-CX4 (module)"},
2780 {0, (1 << 5), "10GBASE-ER"},
2782 {0, (1 << 3), "10GBASE-SW"},
2783 {0, (1 << 2), "10GBASE-LW"},
2784 {0, (1 << 1), "10GBASE-EW"},
2785 {0, (1 << 0), "Reserved"}
2789 {IFM_10G_TWINAX, 0, "10GBASE-Twinax"},
2790 {0, (1 << 7), "Reserved"},
2794 {IFM_10G_TWINAX,(1 << 0), "10GBASE-Twinax"}
2802 0, NULL); in mxge_media_set()
2829 for (i = 0; i < 3; i++, ptr++) { in mxge_media_init()
2874 sc->need_media_probe = 0; in mxge_media_probe()
2903 cmd.data0 = 0; /* just fetch 1 byte, not all 256 */ in mxge_media_probe()
2919 for (ms = 0; (err == EBUSY) && (ms < 50); ms++) { in mxge_media_probe()
2930 if (cmd.data0 == mxge_media_types[0].bitmask) { in mxge_media_probe()
2933 mxge_media_types[0].name); in mxge_media_probe()
2934 if (sc->current_media != mxge_media_types[0].flag) { in mxge_media_probe()
2936 mxge_media_set(sc, mxge_media_types[0].flag); in mxge_media_probe()
2955 device_printf(sc->dev, "%s media 0x%x unknown\n", in mxge_media_probe()
2980 *sc->irq_deassert = 0; in mxge_intr()
2983 stats->valid = 0; in mxge_intr()
2985 stats->valid = 0; in mxge_intr()
2993 (rx_done->entry[rx_done->idx].length != 0)) { in mxge_intr()
3028 sc->link_state = 0; in mxge_intr()
3034 if (valid & 0x1) in mxge_intr()
3046 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) in mxge_init()
3059 for (i = 0; i <= ss->rx_big.mask; i++) { in mxge_free_slice_mbufs()
3068 for (i = 0; i <= ss->rx_small.mask; i++) { in mxge_free_slice_mbufs()
3081 for (i = 0; i <= ss->tx.mask; i++) { in mxge_free_slice_mbufs()
3082 ss->tx.info[i].flag = 0; in mxge_free_slice_mbufs()
3097 for (slice = 0; slice < sc->num_slices; slice++) in mxge_free_mbufs()
3128 for (i = 0; i <= ss->tx.mask; i++) { in mxge_free_slice_rings()
3140 for (i = 0; i <= ss->rx_small.mask; i++) { in mxge_free_slice_rings()
3154 for (i = 0; i <= ss->rx_big.mask; i++) { in mxge_free_slice_rings()
3172 for (slice = 0; slice < sc->num_slices; slice++) in mxge_free_rings()
3216 if (err != 0) { in mxge_alloc_slice_rings()
3224 0, /* boundary */ in mxge_alloc_slice_rings()
3234 if (err != 0) { in mxge_alloc_slice_rings()
3239 for (i = 0; i <= ss->rx_small.mask; i++) { in mxge_alloc_slice_rings()
3240 err = bus_dmamap_create(ss->rx_small.dmat, 0, in mxge_alloc_slice_rings()
3242 if (err != 0) { in mxge_alloc_slice_rings()
3248 err = bus_dmamap_create(ss->rx_small.dmat, 0, in mxge_alloc_slice_rings()
3250 if (err != 0) { in mxge_alloc_slice_rings()
3256 for (i = 0; i <= ss->rx_big.mask; i++) { in mxge_alloc_slice_rings()
3257 err = bus_dmamap_create(ss->rx_big.dmat, 0, in mxge_alloc_slice_rings()
3259 if (err != 0) { in mxge_alloc_slice_rings()
3265 err = bus_dmamap_create(ss->rx_big.dmat, 0, in mxge_alloc_slice_rings()
3267 if (err != 0) { in mxge_alloc_slice_rings()
3309 if (err != 0) { in mxge_alloc_slice_rings()
3317 for (i = 0; i <= ss->tx.mask; i++) { in mxge_alloc_slice_rings()
3318 err = bus_dmamap_create(ss->tx.dmat, 0, in mxge_alloc_slice_rings()
3320 if (err != 0) { in mxge_alloc_slice_rings()
3326 return 0; in mxge_alloc_slice_rings()
3341 if (err != 0) { in mxge_alloc_rings()
3351 for (slice = 0; slice < sc->num_slices; slice++) { in mxge_alloc_rings()
3355 if (err != 0) in mxge_alloc_rings()
3358 return 0; in mxge_alloc_rings()
3409 err = 0; in mxge_slice_open()
3430 if (err != 0) { in mxge_slice_open()
3437 for (i = 0; i <= ss->rx_small.mask; i++) { in mxge_slice_open()
3446 for (i = 0; i <= ss->rx_big.mask; i++) { in mxge_slice_open()
3447 ss->rx_big.shadow[i].addr_low = 0xffffffff; in mxge_slice_open()
3448 ss->rx_big.shadow[i].addr_high = 0xffffffff; in mxge_slice_open()
3454 for (i = 0; i <= ss->rx_big.mask; i += ss->rx_big.nbufs) { in mxge_slice_open()
3463 return 0; in mxge_slice_open()
3479 if (err != 0) { in mxge_open()
3492 if (err != 0) { in mxge_open()
3500 for (i = 0; i < sc->num_slices; i++) in mxge_open()
3506 if (err != 0) { in mxge_open()
3536 if (err != 0) { in mxge_open()
3542 for (slice = 0; slice < sc->num_slices; slice++) { in mxge_open()
3553 if (err != 0) { in mxge_open()
3562 sc->fw_multicast_support = 0; in mxge_open()
3567 if (err != 0) { in mxge_open()
3572 for (slice = 0; slice < sc->num_slices; slice++) { in mxge_open()
3574 if (err != 0) { in mxge_open()
3587 for (slice = 0; slice < sc->num_slices; slice++) { in mxge_open()
3592 if_setdrvflagbits(sc->ifp, IFF_DRV_RUNNING, 0); in mxge_open()
3593 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_OACTIVE); in mxge_open()
3595 return 0; in mxge_open()
3611 for (slice = 0; slice < sc->num_slices; slice++) { in mxge_close()
3615 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_RUNNING); in mxge_close()
3635 return 0; in mxge_close()
3646 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { in mxge_setup_cfg_space()
3647 lnk = pci_read_config(dev, reg + 0x12, 2); in mxge_setup_cfg_space()
3648 sc->link_width = (lnk >> 4) & 0x3f; in mxge_setup_cfg_space()
3650 if (sc->pectl == 0) { in mxge_setup_cfg_space()
3651 pectl = pci_read_config(dev, reg + 0x8, 2); in mxge_setup_cfg_space()
3652 pectl = (pectl & ~0x7000) | (5 << 12); in mxge_setup_cfg_space()
3653 pci_write_config(dev, reg + 0x8, pectl, 2); in mxge_setup_cfg_space()
3657 pci_write_config(dev, reg + 0x8, sc->pectl, 2); in mxge_setup_cfg_space()
3672 if (pci_find_cap(dev, PCIY_VENDOR, &vs) != 0) { in mxge_read_reboot()
3678 pci_write_config(dev, vs + 0x10, 0x3, 1); in mxge_read_reboot()
3680 pci_write_config(dev, vs + 0x18, 0xfffffff0, 4); in mxge_read_reboot()
3681 return (pci_read_config(dev, vs + 0x14, 4)); in mxge_read_reboot()
3705 if (cmd == 0xffff) { in mxge_watchdog_reset()
3713 if (cmd == 0xffff) { in mxge_watchdog_reset()
3717 if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) { in mxge_watchdog_reset()
3720 device_printf(sc->dev, "NIC rebooted, status = 0x%x\n", in mxge_watchdog_reset()
3731 sc->link_state = 0; in mxge_watchdog_reset()
3739 for (s = 0; s < num_tx_slices; s++) { in mxge_watchdog_reset()
3753 err = mxge_load_firmware(sc, 0); in mxge_watchdog_reset()
3762 for (s = 0; s < num_tx_slices; s++) { in mxge_watchdog_reset()
3772 err = 0; in mxge_watchdog_reset()
3778 sc->dying = 0; in mxge_watchdog_reset()
3813 int i, err = 0; in mxge_watchdog()
3817 for (i = 0; (i < sc->num_slices) && (err == 0); i++) { in mxge_watchdog()
3850 rv = 0; in mxge_get_counter()
3854 for (int s = 0; s < sc->num_slices; s++) in mxge_get_counter()
3858 for (int s = 0; s < sc->num_slices; s++) in mxge_get_counter()
3862 for (int s = 0; s < sc->num_slices; s++) in mxge_get_counter()
3866 for (int s = 0; s < sc->num_slices; s++) in mxge_get_counter()
3870 for (int s = 0; s < sc->num_slices; s++) in mxge_get_counter()
3874 for (int s = 0; s < sc->num_slices; s++) in mxge_get_counter()
3886 u_long pkts = 0; in mxge_tick()
3887 int err = 0; in mxge_tick()
3900 if (pkts == 0) { in mxge_tick()
3903 if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) { in mxge_tick()
3912 if (err == 0) in mxge_tick()
3928 int err = 0; in mxge_change_mtu()
3937 mxge_close(sc, 0); in mxge_change_mtu()
3939 if (err != 0) { in mxge_change_mtu()
3941 mxge_close(sc, 0); in mxge_change_mtu()
3958 ifmr->ifm_status |= sc->link_state ? IFM_ACTIVE : 0; in mxge_media_status()
3969 if (i2c->dev_addr != 0xA0 && in mxge_fetch_i2c()
3970 i2c->dev_addr != 0xA2) in mxge_fetch_i2c()
3975 for (i = 0; i < i2c->len; i++) { in mxge_fetch_i2c()
3976 i2c_args = i2c->dev_addr << 0x8; in mxge_fetch_i2c()
3978 cmd.data0 = 0; /* just fetch 1 byte, not all 256 */ in mxge_fetch_i2c()
3985 cmd.data0 = i2c_args & 0xff; in mxge_fetch_i2c()
3987 for (ms = 0; (err == EBUSY) && (ms < 50); ms++) { in mxge_fetch_i2c()
3988 cmd.data0 = i2c_args & 0xff; in mxge_fetch_i2c()
3997 return (0); in mxge_fetch_i2c()
4008 err = 0; in mxge_ioctl()
4032 mxge_close(sc, 0); in mxge_ioctl()
4055 if_setcapenablebit(ifp, 0, (IFCAP_TXCSUM|IFCAP_TSO4)); in mxge_ioctl()
4056 if_sethwassistbits(ifp, 0, (CSUM_TCP | CSUM_UDP)); in mxge_ioctl()
4058 if_setcapenablebit(ifp, IFCAP_TXCSUM, 0); in mxge_ioctl()
4059 if_sethwassistbits(ifp, (CSUM_TCP | CSUM_UDP), 0); in mxge_ioctl()
4064 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM); in mxge_ioctl()
4066 if_setcapenablebit(ifp, IFCAP_RXCSUM, 0); in mxge_ioctl()
4071 if_setcapenablebit(ifp, 0, IFCAP_TSO4); in mxge_ioctl()
4073 if_setcapenablebit(ifp, IFCAP_TSO4, 0); in mxge_ioctl()
4074 if_sethwassistbits(ifp, CSUM_TSO, 0); in mxge_ioctl()
4085 if_setcapenablebit(ifp, 0, in mxge_ioctl()
4087 if_sethwassistbits(ifp, 0, in mxge_ioctl()
4090 if_setcapenablebit(ifp, IFCAP_TXCSUM_IPV6, 0); in mxge_ioctl()
4092 CSUM_TCP_IPV6 | CSUM_UDP_IPV6, 0); in mxge_ioctl()
4097 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM_IPV6); in mxge_ioctl()
4099 if_setcapenablebit(ifp, IFCAP_RXCSUM_IPV6, 0); in mxge_ioctl()
4104 if_setcapenablebit(ifp, 0, IFCAP_TSO6); in mxge_ioctl()
4106 if_setcapenablebit(ifp, IFCAP_TSO6, 0); in mxge_ioctl()
4107 if_sethwassistbits(ifp, CSUM_TSO, 0); in mxge_ioctl()
4125 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); in mxge_ioctl()
4151 if (err != 0) in mxge_ioctl()
4160 if (err == 0) in mxge_ioctl()
4197 if (mxge_intr_coal_delay < 0 || mxge_intr_coal_delay > 10*1000) in mxge_fetch_tunables()
4199 if (mxge_ticks == 0) in mxge_fetch_tunables()
4226 for (i = 0; i < sc->num_slices; i++) { in mxge_free_slices()
4255 if (err != 0) { in mxge_alloc_slices()
4266 for (i = 0; i < sc->num_slices; i++) { in mxge_alloc_slices()
4275 if (err != 0) in mxge_alloc_slices()
4289 if (err != 0) in mxge_alloc_slices()
4299 return (0); in mxge_alloc_slices()
4319 if (mxge_max_slices == 0 || mxge_max_slices == 1 || mp_ncpus < 2) in mxge_slice_probe()
4333 status = mxge_load_firmware(sc, 0); in mxge_slice_probe()
4334 if (status != 0) { in mxge_slice_probe()
4341 memset(&cmd, 0, sizeof (cmd)); in mxge_slice_probe()
4343 if (status != 0) { in mxge_slice_probe()
4350 if (status != 0) { in mxge_slice_probe()
4359 if (status != 0) { in mxge_slice_probe()
4366 if (status != 0) { in mxge_slice_probe()
4395 (void) mxge_load_firmware(sc, 0); in mxge_slice_probe()
4415 if (err != 0) { in mxge_add_msix_irqs()
4436 for (i = 0; i < sc->num_slices; i++) { in mxge_add_msix_irqs()
4452 for (i = 0; i < sc->num_slices; i++) { in mxge_add_msix_irqs()
4456 if (err != 0) { in mxge_add_msix_irqs()
4468 for (i = 0; i < sc->num_slices; i++) in mxge_add_msix_irqs()
4472 return (0); in mxge_add_msix_irqs()
4475 for (i = 0; i < sc->num_slices; i++) { in mxge_add_msix_irqs()
4485 for (i = 0; i < sc->num_slices; i++) { in mxge_add_msix_irqs()
4510 if (count == 1 && pci_alloc_msi(sc->dev, &count) == 0) { in mxge_add_single_irq()
4513 rid = 0; in mxge_add_single_irq()
4528 mxge_intr, &sc->ss[0], &sc->ih); in mxge_add_single_irq()
4529 if (err != 0) { in mxge_add_single_irq()
4531 sc->legacy_irq ? 0 : 1, sc->irq_res); in mxge_add_single_irq()
4543 for (i = 0; i < sc->num_slices; i++) { in mxge_rem_msix_irqs()
4552 for (i = 0; i < sc->num_slices; i++) { in mxge_rem_msix_irqs()
4573 sc->legacy_irq ? 0 : 1, sc->irq_res); in mxge_rem_single_irq()
4597 if (0 && err == 0 && sc->num_slices > 1) { in mxge_add_irq()
4621 0, /* boundary */ in mxge_attach()
4628 0, /* flags */ in mxge_attach()
4632 if (err != 0) { in mxge_attach()
4649 callout_init_mtx(&sc->co_hdl, &sc->driver_mtx, 0); in mxge_attach()
4663 sc->sram_size = 2*1024*1024 - (2*(48*1024)+(32*1024)) - 0x100; in mxge_attach()
4680 if (err != 0) in mxge_attach()
4689 if (err != 0) in mxge_attach()
4693 if (err != 0) in mxge_attach()
4697 if (err != 0) in mxge_attach()
4702 if (err != 0) in mxge_attach()
4708 if (err != 0) in mxge_attach()
4711 err = mxge_reset(sc, 0); in mxge_attach()
4712 if (err != 0) in mxge_attach()
4716 if (err != 0) { in mxge_attach()
4722 if (err != 0) { in mxge_attach()
4732 if_setcapabilitiesbit(ifp, IFCAP_LRO, 0); in mxge_attach()
4736 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM, 0); in mxge_attach()
4741 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTSO, 0); in mxge_attach()
4745 if_setcapabilitiesbit(ifp, IFCAP_JUMBO_MTU, 0); in mxge_attach()
4751 if_sethwassistbits(ifp, CSUM_TCP_IPV6 | CSUM_UDP_IPV6, 0); in mxge_attach()
4755 if_setcapabilitiesbit(ifp, IFCAP_TSO6, 0); in mxge_attach()
4757 sizeof (sc->ss[0].scratch)); in mxge_attach()
4760 if (sc->lro_cnt == 0) in mxge_attach()
4761 if_setcapenablebit(ifp, 0, IFCAP_LRO); in mxge_attach()
4769 if_sethwtsomaxsegcount(ifp, sc->ss[0].tx.max_desc); in mxge_attach()
4772 ifmedia_init(&sc->media, 0, mxge_media_change, in mxge_attach()
4776 sc->dying = 0; in mxge_attach()
4788 return 0; in mxge_attach()
4830 mxge_close(sc, 0); in mxge_detach()
4840 mxge_dummy_rdma(sc, 0); in mxge_detach()
4854 return 0; in mxge_detach()
4860 return 0; in mxge_shutdown()