Lines Matching +full:0 +full:xa600
41 #define MACREG_REG_TSF_LOW 0xa600 /* TSF lo */
42 #define MACREG_REG_TSF_HIGH 0xa604 /* TSF hi */
43 #define MACREG_REG_CHIP_REV 0xa814 /* chip rev */
45 // Map to 0x80000000 (Bus control) on BAR0
46 #define MACREG_REG_H2A_INTERRUPT_EVENTS 0x00000C18 // (From host to ARM)
47 #define MACREG_REG_H2A_INTERRUPT_CAUSE 0x00000C1C // (From host to ARM)
48 #define MACREG_REG_H2A_INTERRUPT_MASK 0x00000C20 // (From host to ARM)
49 #define MACREG_REG_H2A_INTERRUPT_CLEAR_SEL 0x00000C24 // (From host to ARM)
50 #define MACREG_REG_H2A_INTERRUPT_STATUS_MASK 0x00000C28 // (From host to ARM)
52 #define MACREG_REG_A2H_INTERRUPT_EVENTS 0x00000C2C // (From ARM to host)
53 #define MACREG_REG_A2H_INTERRUPT_CAUSE 0x00000C30 // (From ARM to host)
54 #define MACREG_REG_A2H_INTERRUPT_MASK 0x00000C34 // (From ARM to host)
55 #define MACREG_REG_A2H_INTERRUPT_CLEAR_SEL 0x00000C38 // (From ARM to host)
56 #define MACREG_REG_A2H_INTERRUPT_STATUS_MASK 0x00000C3C // (From ARM to host)
58 // Map to 0x80000000 on BAR1
59 #define MACREG_REG_GEN_PTR 0x00000C10
60 #define MACREG_REG_INT_CODE 0x00000C14
61 #define MACREG_REG_SCRATCH 0x00000C40
62 #define MACREG_REG_FW_PRESENT 0x0000BFFC
64 #define MACREG_REG_PROMISCUOUS 0xA300
67 #define MACREG_A2HRIC_BIT_TX_DONE 0x00000001 // bit 0
68 #define MACREG_A2HRIC_BIT_RX_RDY 0x00000002 // bit 1
69 #define MACREG_A2HRIC_BIT_OPC_DONE 0x00000004 // bit 2
70 #define MACREG_A2HRIC_BIT_MAC_EVENT 0x00000008 // bit 3
71 #define MACREG_A2HRIC_BIT_RX_PROBLEM 0x00000010 // bit 4
73 #define MACREG_A2HRIC_BIT_RADIO_OFF 0x00000020 // bit 5
74 #define MACREG_A2HRIC_BIT_RADIO_ON 0x00000040 // bit 6
76 #define MACREG_A2HRIC_BIT_RADAR_DETECT 0x00000080 // bit 7
78 #define MACREG_A2HRIC_BIT_ICV_ERROR 0x00000100 // bit 8
79 #define MACREG_A2HRIC_BIT_MIC_ERROR 0x00000200 // bit 9
80 #define MACREG_A2HRIC_BIT_QUEUE_EMPTY 0x00004000
81 #define MACREG_A2HRIC_BIT_QUEUE_FULL 0x00000800
82 #define MACREG_A2HRIC_BIT_CHAN_SWITCH 0x00001000
83 #define MACREG_A2HRIC_BIT_TX_WATCHDOG 0x00002000
84 #define MACREG_A2HRIC_BIT_BA_WATCHDOG 0x00000400
85 #define MACREQ_A2HRIC_BIT_TX_ACK 0x00008000
102 #define MACREG_H2ARIC_BIT_PPA_READY 0x00000001 // bit 0
103 #define MACREG_H2ARIC_BIT_DOOR_BELL 0x00000002 // bit 1
107 #define MACREG_INT_CODE_CMD_FINISHED 0x00000005
120 #define NUM_HCCA_QUEUES 0
121 #define NUM_BA_QUEUES 0
122 #define NUM_MGMT_QUEUES 0
145 #define EAGLE_TXD_STATUS_IDLE 0x00000000
146 #define EAGLE_TXD_STATUS_USED 0x00000001
147 #define EAGLE_TXD_STATUS_OK 0x00000001
148 #define EAGLE_TXD_STATUS_OK_RETRY 0x00000002
149 #define EAGLE_TXD_STATUS_OK_MORE_RETRY 0x00000004
150 #define EAGLE_TXD_STATUS_MULTICAST_TX 0x00000008
151 #define EAGLE_TXD_STATUS_BROADCAST_TX 0x00000010
152 #define EAGLE_TXD_STATUS_FAILED_LINK_ERROR 0x00000020
153 #define EAGLE_TXD_STATUS_FAILED_EXCEED_LIMIT 0x00000040
155 #define EAGLE_TXD_STATUS_FAILED_AGING 0x00000080
156 #define EAGLE_TXD_STATUS_FW_OWNED 0x80000000
176 #define EAGLE_TXD_FORMAT 0x0001 /* frame format/rate */
177 #define EAGLE_TXD_FORMAT_LEGACY 0x0000 /* legacy rate frame */
178 #define EAGLE_TXD_FORMAT_HT 0x0001 /* HT rate frame */
179 #define EAGLE_TXD_GI 0x0002 /* guard interval */
180 #define EAGLE_TXD_GI_SHORT 0x0002 /* short guard interval */
181 #define EAGLE_TXD_GI_LONG 0x0000 /* long guard interval */
182 #define EAGLE_TXD_CHW 0x0004 /* channel width */
183 #define EAGLE_TXD_CHW_20 0x0000 /* 20MHz channel width */
184 #define EAGLE_TXD_CHW_40 0x0004 /* 40MHz channel width */
185 #define EAGLE_TXD_RATE 0x01f8 /* tx rate (legacy)/ MCS */
187 #define EAGLE_TXD_ADV 0x0600 /* advanced coding */
189 #define EAGLE_TXD_ADV_NONE 0x0000
190 #define EAGLE_TXD_ADV_LDPC 0x0200
191 #define EAGLE_TXD_ADV_RS 0x0400
193 #define EAGLE_TXD_ANTENNA 0x1800 /* antenna select */
195 #define EAGLE_TXD_EXTCHAN 0x6000 /* extension channel */
197 #define EAGLE_TXD_EXTCHAN_HI 0x0000 /* above */
198 #define EAGLE_TXD_EXTCHAN_LO 0x2000 /* below */
199 #define EAGLE_TXD_PREAMBLE 0x8000
200 #define EAGLE_TXD_PREAMBLE_SHORT 0x8000 /* short preamble */
201 #define EAGLE_TXD_PREAMBLE_LONG 0x0000 /* long preamble */
203 #define EAGLE_TXD_FIXED_RATE 0x0100 /* get tx rate from Format */
204 #define EAGLE_TXD_DONT_AGGR 0x0200 /* don't aggregate frame */
223 #define EAGLE_RXD_CTRL_DRIVER_OWN 0x00
224 #define EAGLE_RXD_CTRL_OS_OWN 0x04
225 #define EAGLE_RXD_CTRL_DMA_OWN 0x80
228 #define EAGLE_RXD_STATUS_IDLE 0x00
229 #define EAGLE_RXD_STATUS_OK 0x01
230 #define EAGLE_RXD_STATUS_MULTICAST_RX 0x02
231 #define EAGLE_RXD_STATUS_BROADCAST_RX 0x04
232 #define EAGLE_RXD_STATUS_FRAGMENT_RX 0x08
233 #define EAGLE_RXD_STATUS_GENERAL_DECRYPT_ERR 0xff
234 #define EAGLE_RXD_STATUS_DECRYPT_ERR_MASK 0x80
235 #define EAGLE_RXD_STATUS_TKIP_MIC_DECRYPT_ERR 0x02
236 #define EAGLE_RXD_STATUS_WEP_ICV_DECRYPT_ERR 0x04
237 #define EAGLE_RXD_STATUS_TKIP_ICV_DECRYPT_ERR 0x08
254 // The following mode signature has to be written to PCI scratch register#0
258 #define HostCmd_STA_MODE 0x5A
259 #define HostCmd_SOFTAP_MODE 0xA5
261 #define HostCmd_STA_FWRDY_SIGNATURE 0xF0F1F2F4
262 #define HostCmd_SOFTAP_FWRDY_SIGNATURE 0xF1F2F4A5
269 #define HostCmd_CMD_CODE_DNLD 0x0001
270 #define HostCmd_CMD_GET_HW_SPEC 0x0003
271 #define HostCmd_CMD_SET_HW_SPEC 0x0004
272 #define HostCmd_CMD_MAC_MULTICAST_ADR 0x0010
273 #define HostCmd_CMD_802_11_GET_STAT 0x0014
274 #define HostCmd_CMD_MAC_REG_ACCESS 0x0019
275 #define HostCmd_CMD_BBP_REG_ACCESS 0x001a
276 #define HostCmd_CMD_RF_REG_ACCESS 0x001b
277 #define HostCmd_CMD_802_11_RADIO_CONTROL 0x001c
278 #define HostCmd_CMD_802_11_RF_TX_POWER 0x001e
279 #define HostCmd_CMD_802_11_RF_ANTENNA 0x0020
280 #define HostCmd_CMD_SET_BEACON 0x0100
281 #define HostCmd_CMD_SET_AID 0x010d
282 #define HostCmd_CMD_SET_RF_CHANNEL 0x010a
283 #define HostCmd_CMD_SET_INFRA_MODE 0x010e
284 #define HostCmd_CMD_SET_G_PROTECT_FLAG 0x010f
285 #define HostCmd_CMD_802_11_RTS_THSD 0x0113
286 #define HostCmd_CMD_802_11_SET_SLOT 0x0114
288 #define HostCmd_CMD_802_11H_DETECT_RADAR 0x0120
289 #define HostCmd_CMD_SET_WMM_MODE 0x0123
290 #define HostCmd_CMD_HT_GUARD_INTERVAL 0x0124
291 #define HostCmd_CMD_SET_FIXED_RATE 0x0126
292 #define HostCmd_CMD_SET_LINKADAPT_CS_MODE 0x0129
293 #define HostCmd_CMD_SET_MAC_ADDR 0x0202
294 #define HostCmd_CMD_SET_RATE_ADAPT_MODE 0x0203
295 #define HostCmd_CMD_GET_WATCHDOG_BITMAP 0x0205
298 #define HostCmd_CMD_BSS_START 0x1100
299 #define HostCmd_CMD_SET_NEW_STN 0x1111
300 #define HostCmd_CMD_SET_KEEP_ALIVE 0x1112
301 #define HostCmd_CMD_SET_APMODE 0x1114
302 #define HostCmd_CMD_SET_SWITCH_CHANNEL 0x1121
308 #define HostCmd_CMD_UPDATE_ENCRYPTION 0x1122
313 #define HostCmd_CMD_BASTREAM 0x1125
314 #define HostCmd_CMD_SET_RIFS 0x1126
315 #define HostCmd_CMD_SET_N_PROTECT_FLAG 0x1131
316 #define HostCmd_CMD_SET_N_PROTECT_OPMODE 0x1132
317 #define HostCmd_CMD_SET_OPTIMIZATION_LEVEL 0x1133
318 #define HostCmd_CMD_GET_CALTABLE 0x1134
319 #define HostCmd_CMD_SET_MIMOPSHT 0x1135
320 #define HostCmd_CMD_GET_BEACON 0x1138
321 #define HostCmd_CMD_SET_REGION_CODE 0x1139
322 #define HostCmd_CMD_SET_POWERSAVESTATION 0x1140
323 #define HostCmd_CMD_SET_TIM 0x1141
324 #define HostCmd_CMD_GET_TIM 0x1142
325 #define HostCmd_CMD_GET_SEQNO 0x1143
326 #define HostCmd_CMD_DWDS_ENABLE 0x1144
327 #define HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE 0x1145
328 #define HostCmd_CMD_CFEND_ENABLE 0x1146
333 #define HostCmd_RESULT_OK 0x0000 // OK
334 #define HostCmd_RESULT_ERROR 0x0001 // Genenral error
335 #define HostCmd_RESULT_NOT_SUPPORT 0x0002 // Command is not valid
336 #define HostCmd_RESULT_PENDING 0x0003 // Command is pending (will be processed)
337 #define HostCmd_RESULT_BUSY 0x0004 // System is busy (command ignored)
338 #define HostCmd_RESULT_PARTIAL_DATA 0x0005 // Data buffer is not big enough
345 #define HostCmd_ACT_GEN_READ 0x0000
346 #define HostCmd_ACT_GEN_WRITE 0x0001
347 #define HostCmd_ACT_GEN_GET 0x0000
348 #define HostCmd_ACT_GEN_SET 0x0001
349 #define HostCmd_ACT_GEN_OFF 0x0000
350 #define HostCmd_ACT_GEN_ON 0x0001
352 #define HostCmd_ACT_DIFF_CHANNEL 0x0002
353 #define HostCmd_ACT_GEN_SET_LIST 0x0002
356 #define HostCmd_ACT_USE_FIXED_RATE 0x0001
357 #define HostCmd_ACT_NOT_USE_FIXED_RATE 0x0002
360 //#define HostCmd_ACT_ENABLE 0x0001 // Use MAC control for WEP on/off
361 //#define HostCmd_ACT_DISABLE 0x0000
362 #define HostCmd_ACT_ADD 0x0002
363 #define HostCmd_ACT_REMOVE 0x0004
364 #define HostCmd_ACT_USE_DEFAULT 0x0008
366 #define HostCmd_TYPE_WEP_40_BIT 0x0001 // 40 bit
367 #define HostCmd_TYPE_WEP_104_BIT 0x0002 // 104 bit
368 #define HostCmd_TYPE_WEP_128_BIT 0x0003 // 128 bit
369 #define HostCmd_TYPE_WEP_TX_KEY 0x0004 // TX WEP
373 #define HostCmd_WEP_KEY_INDEX_MASK 0x3fffffff
376 #define HostCmd_ACT_HALT 0x0001
377 #define HostCmd_ACT_RESTART 0x0002
380 #define HostCmd_TYPE_AUTO_PREAMBLE 0x0001
381 #define HostCmd_TYPE_SHORT_PREAMBLE 0x0002
382 #define HostCmd_TYPE_LONG_PREAMBLE 0x0003
385 #define HostCmd_TYPE_802_11A 0x0001
386 #define HostCmd_TYPE_802_11B 0x0002
389 #define HostCmd_ACT_TX_POWER_OPT_SET_HIGH 0x0003
390 #define HostCmd_ACT_TX_POWER_OPT_SET_MID 0x0002
391 #define HostCmd_ACT_TX_POWER_OPT_SET_LOW 0x0001
392 #define HostCmd_ACT_TX_POWER_OPT_SET_AUTO 0x0000
394 #define HostCmd_ACT_TX_POWER_LEVEL_MIN 0x000e // in dbm
395 #define HostCmd_ACT_TX_POWER_LEVEL_GAP 0x0001 // in dbm
397 #define HostCmd_ACT_SET_TX_AUTO 0x0000
398 #define HostCmd_ACT_SET_TX_FIX_RATE 0x0001
399 #define HostCmd_ACT_GET_TX_RATE 0x0002
401 #define HostCmd_ACT_SET_RX 0x0001
402 #define HostCmd_ACT_SET_TX 0x0002
403 #define HostCmd_ACT_SET_BOTH 0x0003
404 #define HostCmd_ACT_GET_RX 0x0004
405 #define HostCmd_ACT_GET_TX 0x0008
406 #define HostCmd_ACT_GET_BOTH 0x000c
408 #define TYPE_ANTENNA_DIVERSITY 0xffff
411 #define HostCmd_TYPE_CAM 0x0000
412 #define HostCmd_TYPE_MAX_PSP 0x0001
413 #define HostCmd_TYPE_FAST_PSP 0x0002
415 #define HostCmd_CMD_SET_EDCA_PARAMS 0x0115
451 #define SET_HW_SPEC_DISABLEMBSS 0x08
452 #define SET_HW_SPEC_HOSTFORM_BEACON 0x10
453 #define SET_HW_SPEC_HOSTFORM_PROBERESP 0x20
454 #define SET_HW_SPEC_HOST_POWERSAVE 0x40
455 #define SET_HW_SPEC_HOSTENCRDECR_MGMT 0x80
610 u_int32_t ApRFType; /* 0->B, 1->G, 2->Mixed, 3->A, 4->11J */
613 #define HostCmd_CAPINFO_DEFAULT 0x0000
614 #define HostCmd_CAPINFO_ESS 0x0001
615 #define HostCmd_CAPINFO_IBSS 0x0002
616 #define HostCmd_CAPINFO_CF_POLLABLE 0x0004
617 #define HostCmd_CAPINFO_CF_REQUEST 0x0008
618 #define HostCmd_CAPINFO_PRIVACY 0x0010
619 #define HostCmd_CAPINFO_SHORT_PREAMBLE 0x0020
620 #define HostCmd_CAPINFO_PBCC 0x0040
621 #define HostCmd_CAPINFO_CHANNEL_AGILITY 0x0080
622 #define HostCmd_CAPINFO_SHORT_SLOT 0x0400
623 #define HostCmd_CAPINFO_DSSS_OFDM 0x2000
663 /* bits 0-5 specify frequency band */
664 #define FREQ_BAND_2DOT4GHZ 0x0001
665 #define FREQ_BAND_4DOT9GHZ 0x0002 /* XXX not implemented */
666 #define FREQ_BAND_5GHZ 0x0004
667 #define FREQ_BAND_5DOT2GHZ 0x0008 /* XXX not implemented */
669 #define CH_AUTO_WIDTH 0x0000 /* XXX not used? */
670 #define CH_10_MHz_WIDTH 0x0040
671 #define CH_20_MHz_WIDTH 0x0080
672 #define CH_40_MHz_WIDTH 0x0100
674 #define EXT_CH_NONE 0x0000 /* no extension channel */
675 #define EXT_CH_ABOVE_CTRL_CH 0x0800 /* extension channel above */
676 #define EXT_CH_AUTO 0x1000 /* XXX not used? */
677 #define EXT_CH_BELOW_CTRL_CH 0x1800 /* extension channel below */
680 #define FIXED_RATE_WITH_AUTO_RATE_DROP 0
683 #define LEGACY_RATE_TYPE 0
686 #define RETRY_COUNT_VALID 0
691 uint32_t FixRateType; //0: legacy, 1: HT
692 uint32_t RetryCountValid; //0: retry count is not valid, 1: use retry count specified
703 uint32_t Action; //HostCmd_ACT_GEN_GET 0x0000
704 //HostCmd_ACT_GEN_SET 0x0001
705 //HostCmd_ACT_NOT_USE_FIXED_RATE 0x0002
724 #define GI_TYPE_LONG 0x0001
725 #define GI_TYPE_SHORT 0x0002
738 uint8_t Slot; // Slot=0 if regular, Slot=1 if short.
804 uint16_t Control; // @bit0: 1/0,on/off, @bit1: 1/0, long/short @bit2: 1/0,auto/fix
823 uint16_t AntennaMode; // Number of antennas or 0xffff(diversity)
844 #define WL_MAC_TYPE_PRIMARY_CLIENT 0
918 #define DR_DFS_DISABLE 0
974 uint32_t Action ; // 0 -> unset, 1 ->set
986 uint16_t Action; // 0->unset, 1->set
991 uint16_t Action; // 0->unset, 1->set
1001 uint16_t Action; //0 = get all, 0x1 =set CWMin/Max, 0x2 = set TXOP , 0x4 =set AIFSN
1003 uint32_t CWMax; // 0~15
1004 uint32_t CWMin; // 0~15
1018 #define ENCR_KEY_TYPE_ID_WEP 0x00 /* Key type is WEP */
1019 #define ENCR_KEY_TYPE_ID_TKIP 0x01 /* Key type is TKIP */
1020 #define ENCR_KEY_TYPE_ID_AES 0x02 /* Key type is AES-CCMP */
1023 #define ENCR_KEY_FLAG_INUSE 0x00000001 /* indicate key is in use */
1024 #define ENCR_KEY_FLAG_RXGROUPKEY 0x00000002 /* Group key for RX only */
1025 #define ENCR_KEY_FLAG_TXGROUPKEY 0x00000004 /* Group key for TX */
1026 #define ENCR_KEY_FLAG_PAIRWISE 0x00000008 /* pairwise */
1027 #define ENCR_KEY_FLAG_RXONLY 0x00000010 /* only used for RX */
1029 #define ENCR_KEY_FLAG_AUTHENTICATOR 0x00000020 /* Key is for Authenticator */
1030 #define ENCR_KEY_FLAG_TSC_VALID 0x00000040 /* Sequence counters valid */
1031 #define ENCR_KEY_FLAG_WEP_TXKEY 0x01000000 /* Tx key for WEP */
1032 #define ENCR_KEY_FLAG_MICKEY_VALID 0x02000000 /* Tx/Rx MIC keys are valid */
1172 #define BASTREAM_FLAG_DELAYED_TYPE 0x00
1173 #define BASTREAM_FLAG_IMMEDIATE_TYPE 0x01
1177 #define BASTREAM_FLAG_DIRECTION_UPSTREAM 0x00
1178 #define BASTREAM_FLAG_DIRECTION_DOWNSTREAM 0x02
1179 #define BASTREAM_FLAG_DIRECTION_DLP 0x04
1180 #define BASTREAM_FLAG_DIRECTION_BOTH 0x06
1216 uint8_t ResetSeqNo; /** 0 or 1**/
1353 uint32_t Enable; //0 -- Disbale. or 1 -- Enable.
1358 uint16_t Action; /* 0: Get. 1:Set */
1359 uint32_t Option; /* 0: default. 1:Aggressive */
1360 uint32_t Threshold; /* Range 0-200, default 8 */
1365 uint32_t Enable; /* 0 -- Disable. or 1 -- Enable */