Lines Matching +full:fis +full:- +full:based
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
42 #define IC_HC0 0x000001ff /* bits 0-8 = HC0 */
44 #define IC_HC1 (IC_HC0 << IC_HC_SHIFT) /* 9-17 = HC1 */
58 #define IC_MAIN_RSVD (0xfe000000) /* bits 31-25 */
59 #define IC_MAIN_RSVD_5 (0xfff10000) /* bits 31-19 */
60 #define IC_MAIN_RSVD_SOC (0xfffffec0) /* bits 31-9, 7-6 */
65 #define CHIP_SOC_HC0_MASK(num) (0xff >> ((4 - (num)) * 2))
87 #define HC_RQOP 0x4 /* Request Queue Out-Pointer */
88 #define HC_RQIP 0x8 /* Response Queue In-Pointer */
137 * during FIS reception.
139 #define EDMA_IE_LINKTXERR_FISTXABORTED (1 << 4) /* FIS Tx is aborted */
147 /* Non-fatal Errors */
149 #define EDMA_REQQIP 0x14 /* Request Queue In-Pointer */
150 #define EDMA_REQQOP 0x18 /* Request Queue Out-Pointer */
156 #define EDMA_RESQIP 0x20 /* Response Queue In-Pointer */
157 #define EDMA_RESQOP 0x24 /* Response Queue Out-Pointer */
254 /* Serial-ATA Registers */
321 #define SATA_SATAICFG 0x050 /* Serial-ATA Interface Configuration */
346 #define SATA_SATAICTL 0x344 /* Serial-ATA Interface Control */
354 #define SATA_SATAITC 0x348 /* Serial-ATA Interface Test Control */
355 #define SATA_SATAIS 0x34c /* Serial-ATA Interface Status */
357 #define SATA_FISC 0x360 /* FIS Configuration */
358 #define SATA_FISC_FISWAIT4RDYEN_B0 (1 << 0) /* Device to Host FIS */
359 #define SATA_FISC_FISWAIT4RDYEN_B1 (1 << 1) /* SDB FIS rcv with <N>bit 0 */
360 #define SATA_FISC_FISWAIT4RDYEN_B2 (1 << 2) /* DMA Activate FIS */
361 #define SATA_FISC_FISWAIT4RDYEN_B3 (1 << 3) /* DMA Setup FIS */
362 #define SATA_FISC_FISWAIT4RDYEN_B4 (1 << 4) /* Data FIS first DW */
363 #define SATA_FISC_FISWAIT4RDYEN_B5 (1 << 5) /* Data FIS entire FIS */
365 /* Device to Host FIS with <ERR> or <DF> */
366 #define SATA_FISC_FISWAIT4HOSTRDYEN_B1 (1 << 9) /* SDB FIS rcv with <N>bit */
367 #define SATA_FISC_FISWAIT4HOSTRDYEN_B2 (1 << 10) /* SDB FIS rcv with <ERR> */
368 #define SATA_FISC_FISWAIT4HOSTRDYEN_B3 (1 << 11) /* BIST Acivate FIS */
369 #define SATA_FISC_FISWAIT4HOSTRDYEN_B4 (1 << 12) /* PIO Setup FIS */
370 #define SATA_FISC_FISWAIT4HOSTRDYEN_B5 (1 << 13) /* Data FIS with Link error */
371 #define SATA_FISC_FISWAIT4HOSTRDYEN_B6 (1 << 14) /* Unrecognized FIS type */
372 #define SATA_FISC_FISWAIT4HOSTRDYEN_B7 (1 << 15) /* Any FIS */
375 #define SATA_FISIC 0x364 /* FIS Interrupt Cause */
376 #define SATA_FISIM 0x368 /* FIS Interrupt Mask */
377 #define SATA_FISDW0 0x370 /* FIS DW0 */
378 #define SATA_FISDW1 0x374 /* FIS DW1 */
379 #define SATA_FISDW2 0x378 /* FIS DW2 */
380 #define SATA_FISDW3 0x37c /* FIS DW3 */
381 #define SATA_FISDW4 0x380 /* FIS DW4 */
382 #define SATA_FISDW5 0x384 /* FIS DW5 */
383 #define SATA_FISDW6 0x388 /* FIS DW6 */
555 int fbs_enabled; /* FIS-based switching enabled */
573 int resetting; /* Hard-reset in progress. */
574 int resetpolldiv; /* Hard-reset poll divider. */
583 struct callout reset_timer; /* Hard-reset timeout */
585 struct mvs_device user[16]; /* User-specified settings */