Lines Matching full:fis

137 	 * during FIS reception.
139 #define EDMA_IE_LINKTXERR_FISTXABORTED   (1 << 4)	/* FIS Tx is aborted */
357 #define SATA_FISC			0x360	/* FIS Configuration */
358 #define SATA_FISC_FISWAIT4RDYEN_B0	 (1 << 0) /* Device to Host FIS */
359 #define SATA_FISC_FISWAIT4RDYEN_B1	 (1 << 1) /* SDB FIS rcv with <N>bit 0 */
360 #define SATA_FISC_FISWAIT4RDYEN_B2	 (1 << 2) /* DMA Activate FIS */
361 #define SATA_FISC_FISWAIT4RDYEN_B3	 (1 << 3) /* DMA Setup FIS */
362 #define SATA_FISC_FISWAIT4RDYEN_B4	 (1 << 4) /* Data FIS first DW */
363 #define SATA_FISC_FISWAIT4RDYEN_B5	 (1 << 5) /* Data FIS entire FIS */
365 				/* Device to Host FIS with <ERR> or <DF> */
366 #define SATA_FISC_FISWAIT4HOSTRDYEN_B1	 (1 << 9) /* SDB FIS rcv with <N>bit */
367 #define SATA_FISC_FISWAIT4HOSTRDYEN_B2	 (1 << 10) /* SDB FIS rcv with <ERR> */
368 #define SATA_FISC_FISWAIT4HOSTRDYEN_B3	 (1 << 11) /* BIST Acivate FIS */
369 #define SATA_FISC_FISWAIT4HOSTRDYEN_B4	 (1 << 12) /* PIO Setup FIS */
370 #define SATA_FISC_FISWAIT4HOSTRDYEN_B5	 (1 << 13) /* Data FIS with Link error */
371 #define SATA_FISC_FISWAIT4HOSTRDYEN_B6	 (1 << 14) /* Unrecognized FIS type */
372 #define SATA_FISC_FISWAIT4HOSTRDYEN_B7	 (1 << 15) /* Any FIS */
375 #define SATA_FISIC			0x364	/* FIS Interrupt Cause */
376 #define SATA_FISIM			0x368	/* FIS Interrupt Mask */
377 #define SATA_FISDW0			0x370	/* FIS DW0 */
378 #define SATA_FISDW1			0x374	/* FIS DW1 */
379 #define SATA_FISDW2			0x378	/* FIS DW2 */
380 #define SATA_FISDW3			0x37c	/* FIS DW3 */
381 #define SATA_FISDW4			0x380	/* FIS DW4 */
382 #define SATA_FISDW5			0x384	/* FIS DW5 */
383 #define SATA_FISDW6			0x388	/* FIS DW6 */
555 	int			fbs_enabled;	/* FIS-based switching enabled */