Lines Matching +full:0 +full:x10e
52 #define CMD_POLL_TOKEN 0xffff
55 HCR_IN_PARAM_OFFSET = 0x00,
56 HCR_IN_MODIFIER_OFFSET = 0x08,
57 HCR_OUT_PARAM_OFFSET = 0x0c,
58 HCR_TOKEN_OFFSET = 0x14,
59 HCR_STATUS_OFFSET = 0x18,
68 CMD_SYS_EN = 0x1,
69 CMD_SYS_DIS = 0x2,
70 CMD_MAP_FA = 0xfff,
71 CMD_UNMAP_FA = 0xffe,
72 CMD_RUN_FW = 0xff6,
73 CMD_MOD_STAT_CFG = 0x34,
74 CMD_QUERY_DEV_LIM = 0x3,
75 CMD_QUERY_FW = 0x4,
76 CMD_ENABLE_LAM = 0xff8,
77 CMD_DISABLE_LAM = 0xff7,
78 CMD_QUERY_DDR = 0x5,
79 CMD_QUERY_ADAPTER = 0x6,
80 CMD_INIT_HCA = 0x7,
81 CMD_CLOSE_HCA = 0x8,
82 CMD_INIT_IB = 0x9,
83 CMD_CLOSE_IB = 0xa,
84 CMD_QUERY_HCA = 0xb,
85 CMD_SET_IB = 0xc,
86 CMD_ACCESS_DDR = 0x2e,
87 CMD_MAP_ICM = 0xffa,
88 CMD_UNMAP_ICM = 0xff9,
89 CMD_MAP_ICM_AUX = 0xffc,
90 CMD_UNMAP_ICM_AUX = 0xffb,
91 CMD_SET_ICM_SIZE = 0xffd,
94 CMD_SW2HW_MPT = 0xd,
95 CMD_QUERY_MPT = 0xe,
96 CMD_HW2SW_MPT = 0xf,
97 CMD_READ_MTT = 0x10,
98 CMD_WRITE_MTT = 0x11,
99 CMD_SYNC_TPT = 0x2f,
102 CMD_MAP_EQ = 0x12,
103 CMD_SW2HW_EQ = 0x13,
104 CMD_HW2SW_EQ = 0x14,
105 CMD_QUERY_EQ = 0x15,
108 CMD_SW2HW_CQ = 0x16,
109 CMD_HW2SW_CQ = 0x17,
110 CMD_QUERY_CQ = 0x18,
111 CMD_RESIZE_CQ = 0x2c,
114 CMD_SW2HW_SRQ = 0x35,
115 CMD_HW2SW_SRQ = 0x36,
116 CMD_QUERY_SRQ = 0x37,
117 CMD_ARM_SRQ = 0x40,
120 CMD_RST2INIT_QPEE = 0x19,
121 CMD_INIT2RTR_QPEE = 0x1a,
122 CMD_RTR2RTS_QPEE = 0x1b,
123 CMD_RTS2RTS_QPEE = 0x1c,
124 CMD_SQERR2RTS_QPEE = 0x1d,
125 CMD_2ERR_QPEE = 0x1e,
126 CMD_RTS2SQD_QPEE = 0x1f,
127 CMD_SQD2SQD_QPEE = 0x38,
128 CMD_SQD2RTS_QPEE = 0x20,
129 CMD_ERR2RST_QPEE = 0x21,
130 CMD_QUERY_QPEE = 0x22,
131 CMD_INIT2INIT_QPEE = 0x2d,
132 CMD_SUSPEND_QPEE = 0x32,
133 CMD_UNSUSPEND_QPEE = 0x33,
135 CMD_CONF_SPECIAL_QP = 0x23,
136 CMD_MAD_IFC = 0x24,
139 CMD_READ_MGM = 0x25,
140 CMD_WRITE_MGM = 0x26,
141 CMD_MGID_HASH = 0x27,
144 CMD_DIAG_RPRT = 0x30,
145 CMD_NOP = 0x31,
148 CMD_QUERY_DEBUG_MSG = 0x2a,
149 CMD_SET_DEBUG_MSG = 0x2b,
157 #if 0
186 static int fw_cmd_doorbell = 0;
208 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]); in mthca_cmd_post_dbell()
210 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]); in mthca_cmd_post_dbell()
216 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]); in mthca_cmd_post_dbell()
225 __raw_writel((__force u32) 0, ptr + offs[7]); in mthca_cmd_post_dbell()
256 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4); in mthca_cmd_post_hcr()
257 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4); in mthca_cmd_post_hcr()
260 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4); in mthca_cmd_post_hcr()
267 (event ? (1 << HCA_E_BIT) : 0) | in mthca_cmd_post_hcr()
271 return 0; in mthca_cmd_post_hcr()
283 int err = 0; in mthca_cmd_post()
328 && trans_table[status] == 0)) in mthca_status_to_errno()
343 int err = 0; in mthca_cmd_poll()
350 out_param ? *out_param : 0, in mthca_cmd_poll()
352 op, CMD_POLL_TOKEN, 0); in mthca_cmd_poll()
398 context->result = 0; in mthca_cmd_event()
414 int err = 0; in mthca_cmd_wait()
420 BUG_ON(dev->cmd.free_head < 0); in mthca_cmd_wait()
429 out_param ? *out_param : 0, in mthca_cmd_wait()
473 return mthca_cmd_wait(dev, in_param, &out_param, 0, in mthca_cmd_box()
477 return mthca_cmd_poll(dev, in_param, &out_param, 0, in mthca_cmd_box()
490 return mthca_cmd_box(dev, in_param, 0, in_modifier, in mthca_cmd()
521 dev->cmd.flags = 0; in mthca_cmd_init()
523 dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE, in mthca_cmd_init()
532 MTHCA_MAILBOX_SIZE, 0); in mthca_cmd_init()
538 return 0; in mthca_cmd_init()
563 for (i = 0; i < dev->cmd.max_cmds; ++i) { in mthca_cmd_use_events()
569 dev->cmd.free_head = 0; in mthca_cmd_use_events()
584 return 0; in mthca_cmd_use_events()
596 for (i = 0; i < dev->cmd.max_cmds; ++i) in mthca_cmd_use_polling()
636 ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D); in mthca_SYS_EN()
641 (int) (out >> 6) & 0xf, (int) (out >> 4) & 3, in mthca_SYS_EN()
649 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C); in mthca_SYS_DIS()
659 int nent = 0; in mthca_map_cmd()
661 int err = 0; in mthca_map_cmd()
663 int ts = 0, tc = 0; in mthca_map_cmd()
669 memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE); in mthca_map_cmd()
689 for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) { in mthca_map_cmd()
704 err = mthca_cmd(dev, mailbox->dma, nent, 0, op, in mthca_map_cmd()
708 nent = 0; in mthca_map_cmd()
714 err = mthca_cmd(dev, mailbox->dma, nent, 0, op, in mthca_map_cmd()
742 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B); in mthca_UNMAP_FA()
747 return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A); in mthca_RUN_FW()
753 u16 max_off = 0; in mthca_setup_cmd_doorbells()
756 for (i = 0; i < 8; ++i) in mthca_setup_cmd_doorbells()
760 mthca_warn(dev, "Firmware doorbell region at 0x%016llx, " in mthca_setup_cmd_doorbells()
761 "length 0x%x crosses a page boundary\n", in mthca_setup_cmd_doorbells()
782 int err = 0; in mthca_QUERY_FW()
786 #define QUERY_FW_OUT_SIZE 0x100 in mthca_QUERY_FW()
787 #define QUERY_FW_VER_OFFSET 0x00 in mthca_QUERY_FW()
788 #define QUERY_FW_MAX_CMD_OFFSET 0x0f in mthca_QUERY_FW()
789 #define QUERY_FW_ERR_START_OFFSET 0x30 in mthca_QUERY_FW()
790 #define QUERY_FW_ERR_SIZE_OFFSET 0x38 in mthca_QUERY_FW()
792 #define QUERY_FW_CMD_DB_EN_OFFSET 0x10 in mthca_QUERY_FW()
793 #define QUERY_FW_CMD_DB_OFFSET 0x50 in mthca_QUERY_FW()
794 #define QUERY_FW_CMD_DB_BASE 0x60 in mthca_QUERY_FW()
796 #define QUERY_FW_START_OFFSET 0x20 in mthca_QUERY_FW()
797 #define QUERY_FW_END_OFFSET 0x28 in mthca_QUERY_FW()
799 #define QUERY_FW_SIZE_OFFSET 0x00 in mthca_QUERY_FW()
800 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 in mthca_QUERY_FW()
801 #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40 in mthca_QUERY_FW()
802 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48 in mthca_QUERY_FW()
809 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW, in mthca_QUERY_FW()
820 dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) | in mthca_QUERY_FW()
821 ((dev->fw_ver & 0xffff0000ull) >> 16) | in mthca_QUERY_FW()
822 ((dev->fw_ver & 0x0000ffffull) << 16); in mthca_QUERY_FW()
833 mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n", in mthca_QUERY_FW()
837 if (tmp & 0x1) { in mthca_QUERY_FW()
841 for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i) in mthca_QUERY_FW()
889 int err = 0; in mthca_ENABLE_LAM()
891 #define ENABLE_LAM_OUT_SIZE 0x100 in mthca_ENABLE_LAM()
892 #define ENABLE_LAM_START_OFFSET 0x00 in mthca_ENABLE_LAM()
893 #define ENABLE_LAM_END_OFFSET 0x08 in mthca_ENABLE_LAM()
894 #define ENABLE_LAM_INFO_OFFSET 0x13 in mthca_ENABLE_LAM()
897 #define ENABLE_LAM_INFO_ECC_MASK 0x3 in mthca_ENABLE_LAM()
904 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM, in mthca_ENABLE_LAM()
936 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C); in mthca_DISABLE_LAM()
944 int err = 0; in mthca_QUERY_DDR()
946 #define QUERY_DDR_OUT_SIZE 0x100 in mthca_QUERY_DDR()
947 #define QUERY_DDR_START_OFFSET 0x00 in mthca_QUERY_DDR()
948 #define QUERY_DDR_END_OFFSET 0x08 in mthca_QUERY_DDR()
949 #define QUERY_DDR_INFO_OFFSET 0x13 in mthca_QUERY_DDR()
952 #define QUERY_DDR_INFO_ECC_MASK 0x3 in mthca_QUERY_DDR()
959 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR, in mthca_QUERY_DDR()
999 #define QUERY_DEV_LIM_OUT_SIZE 0x100 in mthca_QUERY_DEV_LIM()
1000 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10 in mthca_QUERY_DEV_LIM()
1001 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11 in mthca_QUERY_DEV_LIM()
1002 #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12 in mthca_QUERY_DEV_LIM()
1003 #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13 in mthca_QUERY_DEV_LIM()
1004 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14 in mthca_QUERY_DEV_LIM()
1005 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15 in mthca_QUERY_DEV_LIM()
1006 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16 in mthca_QUERY_DEV_LIM()
1007 #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17 in mthca_QUERY_DEV_LIM()
1008 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19 in mthca_QUERY_DEV_LIM()
1009 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a in mthca_QUERY_DEV_LIM()
1010 #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b in mthca_QUERY_DEV_LIM()
1011 #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d in mthca_QUERY_DEV_LIM()
1012 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e in mthca_QUERY_DEV_LIM()
1013 #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f in mthca_QUERY_DEV_LIM()
1014 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20 in mthca_QUERY_DEV_LIM()
1015 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21 in mthca_QUERY_DEV_LIM()
1016 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22 in mthca_QUERY_DEV_LIM()
1017 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23 in mthca_QUERY_DEV_LIM()
1018 #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27 in mthca_QUERY_DEV_LIM()
1019 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29 in mthca_QUERY_DEV_LIM()
1020 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b in mthca_QUERY_DEV_LIM()
1021 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f in mthca_QUERY_DEV_LIM()
1022 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33 in mthca_QUERY_DEV_LIM()
1023 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35 in mthca_QUERY_DEV_LIM()
1024 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36 in mthca_QUERY_DEV_LIM()
1025 #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37 in mthca_QUERY_DEV_LIM()
1026 #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b in mthca_QUERY_DEV_LIM()
1027 #define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c in mthca_QUERY_DEV_LIM()
1028 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f in mthca_QUERY_DEV_LIM()
1029 #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44 in mthca_QUERY_DEV_LIM()
1030 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48 in mthca_QUERY_DEV_LIM()
1031 #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49 in mthca_QUERY_DEV_LIM()
1032 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b in mthca_QUERY_DEV_LIM()
1033 #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51 in mthca_QUERY_DEV_LIM()
1034 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52 in mthca_QUERY_DEV_LIM()
1035 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55 in mthca_QUERY_DEV_LIM()
1036 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56 in mthca_QUERY_DEV_LIM()
1037 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61 in mthca_QUERY_DEV_LIM()
1038 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62 in mthca_QUERY_DEV_LIM()
1039 #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63 in mthca_QUERY_DEV_LIM()
1040 #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64 in mthca_QUERY_DEV_LIM()
1041 #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65 in mthca_QUERY_DEV_LIM()
1042 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66 in mthca_QUERY_DEV_LIM()
1043 #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67 in mthca_QUERY_DEV_LIM()
1044 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80 in mthca_QUERY_DEV_LIM()
1045 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82 in mthca_QUERY_DEV_LIM()
1046 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84 in mthca_QUERY_DEV_LIM()
1047 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86 in mthca_QUERY_DEV_LIM()
1048 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88 in mthca_QUERY_DEV_LIM()
1049 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a in mthca_QUERY_DEV_LIM()
1050 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c in mthca_QUERY_DEV_LIM()
1051 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e in mthca_QUERY_DEV_LIM()
1052 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90 in mthca_QUERY_DEV_LIM()
1053 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92 in mthca_QUERY_DEV_LIM()
1054 #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96 in mthca_QUERY_DEV_LIM()
1055 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97 in mthca_QUERY_DEV_LIM()
1056 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98 in mthca_QUERY_DEV_LIM()
1057 #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f in mthca_QUERY_DEV_LIM()
1058 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0 in mthca_QUERY_DEV_LIM()
1065 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM, in mthca_QUERY_DEV_LIM()
1072 dev_lim->reserved_qps = 1 << (field & 0xf); in mthca_QUERY_DEV_LIM()
1074 dev_lim->max_qps = 1 << (field & 0x1f); in mthca_QUERY_DEV_LIM()
1078 dev_lim->max_srqs = 1 << (field & 0x1f); in mthca_QUERY_DEV_LIM()
1080 dev_lim->reserved_eecs = 1 << (field & 0xf); in mthca_QUERY_DEV_LIM()
1082 dev_lim->max_eecs = 1 << (field & 0x1f); in mthca_QUERY_DEV_LIM()
1086 dev_lim->reserved_cqs = 1 << (field & 0xf); in mthca_QUERY_DEV_LIM()
1088 dev_lim->max_cqs = 1 << (field & 0x1f); in mthca_QUERY_DEV_LIM()
1090 dev_lim->max_mpts = 1 << (field & 0x3f); in mthca_QUERY_DEV_LIM()
1092 dev_lim->reserved_eqs = 1 << (field & 0xf); in mthca_QUERY_DEV_LIM()
1094 dev_lim->max_eqs = 1 << (field & 0x7); in mthca_QUERY_DEV_LIM()
1104 dev_lim->reserved_mrws = 1 << (field & 0xf); in mthca_QUERY_DEV_LIM()
1106 dev_lim->max_mtt_seg = 1 << (field & 0x3f); in mthca_QUERY_DEV_LIM()
1108 dev_lim->max_requester_per_qp = 1 << (field & 0x3f); in mthca_QUERY_DEV_LIM()
1110 dev_lim->max_responder_per_qp = 1 << (field & 0x3f); in mthca_QUERY_DEV_LIM()
1112 dev_lim->max_rdma_global = 1 << (field & 0x3f); in mthca_QUERY_DEV_LIM()
1114 dev_lim->local_ca_ack_delay = field & 0x1f; in mthca_QUERY_DEV_LIM()
1117 dev_lim->max_port_width = field & 0xf; in mthca_QUERY_DEV_LIM()
1120 dev_lim->num_ports = field & 0xf; in mthca_QUERY_DEV_LIM()
1122 dev_lim->max_gids = 1 << (field & 0xf); in mthca_QUERY_DEV_LIM()
1126 dev_lim->max_pkeys = 1 << (field & 0xf); in mthca_QUERY_DEV_LIM()
1131 dev_lim->uar_size = 1 << ((field & 0x3f) + 20); in mthca_QUERY_DEV_LIM()
1143 dev_lim->reserved_mgms = field & 0xf; in mthca_QUERY_DEV_LIM()
1149 dev_lim->max_pds = 1 << (field & 0x3f); in mthca_QUERY_DEV_LIM()
1153 dev_lim->max_rdds = 1 << (field & 0x3f); in mthca_QUERY_DEV_LIM()
1186 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f); in mthca_QUERY_DEV_LIM()
1213 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f); in mthca_QUERY_DEV_LIM()
1245 #define VSD_OFFSET_SIG1 0x00 in get_board_id()
1246 #define VSD_OFFSET_SIG2 0xde in get_board_id()
1247 #define VSD_OFFSET_MLX_BOARD_ID 0xd0 in get_board_id()
1248 #define VSD_OFFSET_TS_BOARD_ID 0x20 in get_board_id()
1250 #define VSD_SIGNATURE_TOPSPIN 0x5ad in get_board_id()
1252 memset(board_id, 0, MTHCA_BOARD_ID_LEN); in get_board_id()
1263 for (i = 0; i < 4; ++i) in get_board_id()
1276 #define QUERY_ADAPTER_OUT_SIZE 0x100 in mthca_QUERY_ADAPTER()
1277 #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00 in mthca_QUERY_ADAPTER()
1278 #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04 in mthca_QUERY_ADAPTER()
1279 #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08 in mthca_QUERY_ADAPTER()
1280 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 in mthca_QUERY_ADAPTER()
1281 #define QUERY_ADAPTER_VSD_OFFSET 0x20 in mthca_QUERY_ADAPTER()
1288 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER, in mthca_QUERY_ADAPTER()
1319 #define INIT_HCA_IN_SIZE 0x200 in mthca_INIT_HCA()
1320 #define INIT_HCA_FLAGS1_OFFSET 0x00c in mthca_INIT_HCA()
1321 #define INIT_HCA_FLAGS2_OFFSET 0x014 in mthca_INIT_HCA()
1322 #define INIT_HCA_QPC_OFFSET 0x020 in mthca_INIT_HCA()
1323 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) in mthca_INIT_HCA()
1324 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) in mthca_INIT_HCA()
1325 #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20) in mthca_INIT_HCA()
1326 #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27) in mthca_INIT_HCA()
1327 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) in mthca_INIT_HCA()
1328 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) in mthca_INIT_HCA()
1329 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) in mthca_INIT_HCA()
1330 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) in mthca_INIT_HCA()
1331 #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) in mthca_INIT_HCA()
1332 #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) in mthca_INIT_HCA()
1333 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) in mthca_INIT_HCA()
1334 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) in mthca_INIT_HCA()
1335 #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) in mthca_INIT_HCA()
1336 #define INIT_HCA_UDAV_OFFSET 0x0b0 in mthca_INIT_HCA()
1337 #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0) in mthca_INIT_HCA()
1338 #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4) in mthca_INIT_HCA()
1339 #define INIT_HCA_MCAST_OFFSET 0x0c0 in mthca_INIT_HCA()
1340 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) in mthca_INIT_HCA()
1341 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) in mthca_INIT_HCA()
1342 #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) in mthca_INIT_HCA()
1343 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) in mthca_INIT_HCA()
1344 #define INIT_HCA_TPT_OFFSET 0x0f0 in mthca_INIT_HCA()
1345 #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) in mthca_INIT_HCA()
1346 #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09) in mthca_INIT_HCA()
1347 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) in mthca_INIT_HCA()
1348 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) in mthca_INIT_HCA()
1349 #define INIT_HCA_UAR_OFFSET 0x120 in mthca_INIT_HCA()
1350 #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00) in mthca_INIT_HCA()
1351 #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09) in mthca_INIT_HCA()
1352 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) in mthca_INIT_HCA()
1353 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) in mthca_INIT_HCA()
1354 #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10) in mthca_INIT_HCA()
1355 #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18) in mthca_INIT_HCA()
1362 memset(inbox, 0, INIT_HCA_IN_SIZE); in mthca_INIT_HCA()
1365 MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET); in mthca_INIT_HCA()
1381 /* We leave wqe_quota, responder_exu, etc as 0 (default) */ in mthca_INIT_HCA()
1430 err = mthca_cmd(dev, mailbox->dma, 0, 0, in mthca_INIT_HCA()
1447 #define INIT_IB_FLAGS_OFFSET 0x00 in mthca_INIT_IB()
1454 #define INIT_IB_MAX_GID_OFFSET 0x06 in mthca_INIT_IB()
1455 #define INIT_IB_MAX_PKEY_OFFSET 0x0a in mthca_INIT_IB()
1456 #define INIT_IB_GUID0_OFFSET 0x10 in mthca_INIT_IB()
1457 #define INIT_IB_NODE_GUID_OFFSET 0x18 in mthca_INIT_IB()
1458 #define INIT_IB_SI_GUID_OFFSET 0x20 in mthca_INIT_IB()
1465 memset(inbox, 0, INIT_IB_IN_SIZE); in mthca_INIT_IB()
1467 flags = 0; in mthca_INIT_IB()
1468 flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0; in mthca_INIT_IB()
1469 flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0; in mthca_INIT_IB()
1470 flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0; in mthca_INIT_IB()
1482 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB, in mthca_INIT_IB()
1491 return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A); in mthca_CLOSE_IB()
1496 return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, CMD_TIME_CLASS_C); in mthca_CLOSE_HCA()
1505 u32 flags = 0; in mthca_SET_IB()
1507 #define SET_IB_IN_SIZE 0x40 in mthca_SET_IB()
1508 #define SET_IB_FLAGS_OFFSET 0x00 in mthca_SET_IB()
1510 #define SET_IB_FLAG_RQK (1 << 0) in mthca_SET_IB()
1511 #define SET_IB_CAP_MASK_OFFSET 0x04 in mthca_SET_IB()
1512 #define SET_IB_SI_GUID_OFFSET 0x08 in mthca_SET_IB()
1519 memset(inbox, 0, SET_IB_IN_SIZE); in mthca_SET_IB()
1521 flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0; in mthca_SET_IB()
1522 flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0; in mthca_SET_IB()
1528 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB, in mthca_SET_IB()
1551 inbox[0] = cpu_to_be64(virt); in mthca_MAP_ICM_page()
1554 err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM, in mthca_MAP_ICM_page()
1571 return mthca_cmd(dev, virt, page_count, 0, in mthca_UNMAP_ICM()
1582 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B); in mthca_UNMAP_ICM_AUX()
1587 int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, in mthca_SET_ICM_SIZE()
1588 0, CMD_SET_ICM_SIZE, CMD_TIME_CLASS_A); in mthca_SET_ICM_SIZE()
1602 return 0; in mthca_SET_ICM_SIZE()
1608 return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT, in mthca_SW2HW_MPT()
1615 return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index, in mthca_HW2SW_MPT()
1623 return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT, in mthca_WRITE_MTT()
1629 return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B); in mthca_SYNC_TPT()
1639 0, CMD_MAP_EQ, CMD_TIME_CLASS_B); in mthca_MAP_EQ()
1645 return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ, in mthca_SW2HW_EQ()
1652 return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0, in mthca_HW2SW_EQ()
1660 return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ, in mthca_SW2HW_CQ()
1667 return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0, in mthca_HW2SW_CQ()
1678 #define RESIZE_CQ_IN_SIZE 0x40 in mthca_RESIZE_CQ()
1679 #define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c in mthca_RESIZE_CQ()
1680 #define RESIZE_CQ_LKEY_OFFSET 0x1c in mthca_RESIZE_CQ()
1687 memset(inbox, 0, RESIZE_CQ_IN_SIZE); in mthca_RESIZE_CQ()
1690 * MRs for CQs always start at virtual address 0. in mthca_RESIZE_CQ()
1705 return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ, in mthca_SW2HW_SRQ()
1712 return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0, in mthca_HW2SW_SRQ()
1720 return mthca_cmd_box(dev, 0, mailbox->dma, num, 0, in mthca_QUERY_SRQ()
1726 return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ, in mthca_ARM_SRQ()
1774 u8 op_mod = 0; in mthca_MODIFY_QP()
1775 int my_mailbox = 0; in mthca_MODIFY_QP()
1791 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, in mthca_MODIFY_QP()
1795 if (0 && mailbox) { in mthca_MODIFY_QP()
1799 for (i = 0; i < 0x100 / 4; ++i) { in mthca_MODIFY_QP()
1800 if (i % 8 == 0) in mthca_MODIFY_QP()
1804 if ((i + 1) % 8 == 0) in mthca_MODIFY_QP()
1812 if (0) { in mthca_MODIFY_QP()
1816 for (i = 0; i < 0x100 / 4; ++i) { in mthca_MODIFY_QP()
1817 if (i % 8 == 0) in mthca_MODIFY_QP()
1821 if ((i + 1) % 8 == 0) in mthca_MODIFY_QP()
1836 return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0, in mthca_QUERY_QP()
1846 op_mod = 0; in mthca_CONF_SPECIAL_QP()
1861 return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP, in mthca_CONF_SPECIAL_QP()
1873 u8 op_modifier = 0; in mthca_MAD_IFC()
1875 #define MAD_IFC_BOX_SIZE 0x400 in mthca_MAD_IFC()
1876 #define MAD_IFC_MY_QPN_OFFSET 0x100 in mthca_MAD_IFC()
1877 #define MAD_IFC_RQPN_OFFSET 0x108 in mthca_MAD_IFC()
1878 #define MAD_IFC_SL_OFFSET 0x10c in mthca_MAD_IFC()
1879 #define MAD_IFC_G_PATH_OFFSET 0x10d in mthca_MAD_IFC()
1880 #define MAD_IFC_RLID_OFFSET 0x10e in mthca_MAD_IFC()
1881 #define MAD_IFC_PKEY_OFFSET 0x112 in mthca_MAD_IFC()
1882 #define MAD_IFC_GRH_OFFSET 0x140 in mthca_MAD_IFC()
1902 op_modifier |= 0x1; in mthca_MAD_IFC()
1904 op_modifier |= 0x2; in mthca_MAD_IFC()
1909 memset(inbox + 256, 0, 256); in mthca_MAD_IFC()
1918 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0); in mthca_MAD_IFC()
1927 op_modifier |= 0x4; in mthca_MAD_IFC()
1947 return mthca_cmd_box(dev, 0, mailbox->dma, index, 0, in mthca_READ_MGM()
1954 return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM, in mthca_WRITE_MGM()
1964 err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH, in mthca_MGID_HASH()
1973 return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100)); in mthca_NOP()