Lines Matching refs:BIT_9

182 #define BIT_9		(1 << 9)  macro
285 #define PCI_BURST_DIS		BIT_9	/* Burst Disable */
299 #define PCI_PATCH_DIR_1	BIT_9
364 #define	PCI_GAT_GPHY_N_REC_PACKET	BIT_9	/* GPHY Not Received Packet */
396 #define PEX_DC_EN_PHANTOM	BIT_9	/* Enable Phantom Functions */
794 #define Y2_LED_STAT_ON	BIT_9	/* Status LED On  (YUKON-2 only) */
837 #define Y2_IS_CHK_TXS2	BIT_9	/* Descriptor error TXS 2 */
872 #define Y2_IS_TCP_TXS2	BIT_9	/* TCP length mismatch sync Tx queue IRQ */
1006 #define	GLB_GPIO_RAND_BIT_1	BIT_9	/* Random Bit 1 */
1057 #define RI_CLR_RD_PERR	BIT_9	/* Clear IRQ RAM Read  Parity Err */
1106 #define BMU_STOP		BIT_9	/* Stop  Rx/Tx Queue */
1228 #define WOL_CTL_ENA_PME_ON_MAGIC_PKT	BIT_9
1349 #define PHY_M_AN_100_T4		BIT_9	/* Not cap. 100Base-T4 (always 0) */
1373 #define PHY_M_1000C_AFD		BIT_9	/* Advertise Full Duplex */
1415 #define PHY_M_PC_DIS_SCRAMB	BIT_9	/* Disable Scrambler */
1452 #define PHY_M_IS_SYMB_ERROR	BIT_9	/* Symbol Error */
1562 #define PHY_M_DIS_AUT_MED	BIT_9	/* Disable Aut. Medium Reg. Selection */
1618 #define PHY_M_FIB_SIGD_POL	BIT_9	/* SIGDET Polarity */
1817 #define	GM_GPSR_EXC_COL		BIT_9	/* Excessive Collisions Occurred */
1830 #define GM_GPCR_LOOP_ENA	BIT_9	/* Enable MAC Loopback Mode */
1883 #define GM_SMOD_VLAN_ENA	BIT_9	/* Enable VLAN  (Max. Frame Len) */
1913 #define GMR_FS_BC		BIT_9	/* Broadcast Packet */
1971 #define GMF_RP_TST_OFF		BIT_9	/* Read Pointer Test Off */
2035 #define	Y2_ASF_HCU_CCSR_AHB_RST		BIT_9	/* Reset AHB bridge */
2069 #define GMC_BYP_RETR_ON	BIT_9	/* Bypass MAC retransmit FIFO On */
2100 #define GPC_PHYADDR_1	BIT_9	/* Bit 1 of Phy Addr */