Lines Matching refs:BIT_8

183 #define BIT_8		(1 << 8)  macro
286 #define PCI_DIS_PCI_CLK		BIT_8	/* Disable PCI clock driving */
300 #define PCI_PATCH_DIR_0	BIT_8
365 #define	PCI_GAT_INT_FIFO_EMPTY		BIT_8	/* Internal FIFO Empty */
388 #define	PCI_CF1_ENA_CFG_LDR_DONE	BIT_8	/* Enable core level Config loader done */
397 #define PEX_DC_EN_EXT_TAG	BIT_8	/* Enable Extended Tag Field */
795 #define Y2_LED_STAT_OFF	BIT_8	/* Status LED Off (YUKON-2 only) */
838 #define Y2_IS_CHK_TXA2	BIT_8	/* Descriptor error TXA 2 */
873 #define Y2_IS_TCP_TXA2	BIT_8	/* TCP length mismatch async Tx queue IRQ */
1058 #define RI_CLR_WR_PERR	BIT_8	/* Clear IRQ RAM Write Parity Err */
1107 #define BMU_START		BIT_8	/* Start Rx/Tx Queue */
1229 #define WOL_CTL_DIS_PME_ON_MAGIC_PKT	BIT_8
1350 #define PHY_M_AN_100_FD		BIT_8	/* Advertise 100Base-TX Full Duplex */
1357 #define PHY_M_AN_ASP_X		BIT_8	/* Asymmetric Pause */
1374 #define PHY_M_1000C_AHD		BIT_8	/* Advertise Half Duplex */
1416 #define PHY_M_PC_DIS_FEFI	BIT_8	/* Disable Far End Fault Indic. (FEFI) */
1453 #define PHY_M_IS_FALSE_CARR	BIT_8	/* False Carrier */
1475 #define PHY_M_EC_DOWN_S_ENA	BIT_8	/* Downshift Enable (88E1111 only) */
1818 #define	GM_GPSR_LAT_COL		BIT_8	/* Late Collisions Occurred */
1831 #define GM_GPCR_PART_ENA	BIT_8	/* Enable Partition Mode */
1884 #define GM_SMOD_JUMBO_ENA	BIT_8	/* Enable Jumbo (Max. Frame Len) */
1914 #define GMR_FS_RX_OK		BIT_8	/* Receive OK (Good Packet) */
1972 #define GMF_RP_STEP		BIT_8	/* Read Pointer Step/Increment */
2036 #define	Y2_ASF_HCU_CCSR_CPU_RST_MODE	BIT_8	/* CPU Reset Mode */
2070 #define GMC_BYP_RETR_OFF	BIT_8	/* Bypass MAC retransmit FIFO Off */
2101 #define GPC_PHYADDR_0	BIT_8	/* Bit 0 of Phy Addr */