Lines Matching refs:BIT_15

176 #define BIT_15		(1 << 15)  macro
279 #define PCI_PEX_LEGNAT		BIT_15	/* PEX PM legacy/native mode (YUKON-2) */
332 #define	PCI_FORCE_ASPM_REQUEST	BIT_15	/* Force ASPM Request (A1 only) */
788 #define	Y2_HW_WOL_ON	BIT_15	/* HW WOL On  (Yukon-EC Ultra A1 only) */
1000 #define	GLB_GPIO_INT_RST_D3_DIS	BIT_15	/* Disable Internal Reset After D3 to D0 */
1099 #define BMU_ENA_RX_RSS_HASH	BIT_15	/* Enable  Rx RSS Hash */
1222 #define WOL_CTL_LINK_CHG_OCC		BIT_15
1344 #define PHY_M_AN_NXT_PG		BIT_15	/* Request Next Page */
1400 #define PHY_M_PC_DIS_LINK_P	BIT_15	/* Disable Link Pulses */
1410 #define PHY_M_PC_ENA_DTE_DT	BIT_15	/* Enable Data Terminal Equ. (DTE) Detect */
1422 #define PHY_M_PS_SPEED_1000	BIT_15	/*	10 = 1000 Mbps */
1441 #define PHY_M_PS_DTE_DETECT	BIT_15	/* Data Terminal Equipment (DTE) Detected */
1446 #define PHY_M_IS_AN_ERROR	BIT_15	/* Auto-Negotiation Error */
1466 #define PHY_M_EC_ENA_BC_EXT	BIT_15	/* Enable Block Carr. Ext. (88E1111 only) */
1499 #define PHY_M_LEDC_DIS_LED	BIT_15	/* Disable LED */
1556 #define PHY_M_FC_AUTO_SEL	BIT_15	/* Fiber/Copper Auto Sel. Dis. */
1569 #define PHY_M_CABD_ENA_TEST	BIT_15	/* Enable Test (Page 0) */
1570 #define PHY_M_CABD_DIS_WAIT	BIT_15	/* Disable Waiting Period (Page 1) */
1811 #define GM_GPSR_SPEED		BIT_15	/* Port Speed (1 = 100 Mbps) */
1825 #define GM_GPCR_RMII_PH_ENA	BIT_15	/* Enable RMII for PHY (Yukon-FE only) */
1846 #define GM_TXCR_FORCE_JAM	BIT_15	/* Force Jam / Flow-Control */
1857 #define GM_RXCR_UCF_ENA		BIT_15	/* Enable Unicast filtering */
2063 #define GMC_SEC_RST	BIT_15	/* MAC SEC RST */
2094 #define GPC_ANEG_2	BIT_15	/* ANEG[2] */