Lines Matching full:wol
752 #define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */
753 #define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */
754 #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */
755 #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */
756 #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */
757 #define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */
758 #define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */
759 #define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */
761 /* WOL Pattern Length Registers (YUKON only) */
763 #define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */
764 #define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */
766 /* WOL Pattern Counter Registers (YUKON only) */
768 #define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */
769 #define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */
774 #define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */
775 #define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */
788 #define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */
789 #define Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */
1221 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1247 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
1250 /* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */