Lines Matching full:gphy
333 #define PCI_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */
352 #define PCI_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */
361 #define PCI_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */
364 #define PCI_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */
373 #define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */
741 /* GMAC and GPHY Control Registers (YUKON only) */
743 #define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */
1700 #define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */
1903 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
2080 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
2102 #define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */
2103 #define GPC_RST_SET BIT_0 /* Set GPHY Reset */
2173 /* GPHY address (bits 15..11 of SMI control reg) */