Lines Matching full:gmac
624 /* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
625 #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */
626 #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
627 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */
628 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
629 #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */
634 #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
635 #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
636 #define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
637 #define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
648 /* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
649 #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */
650 #define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
651 #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */
653 #define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
654 #define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */
655 #define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
656 #define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
657 #define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
658 #define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
741 /* GMAC and GPHY Control Registers (YUKON only) */
742 #define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */
744 #define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */
745 #define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */
779 #define BASE_GMAC_1 0x2800 /* GMAC 1 registers */
780 #define BASE_GMAC_2 0x3800 /* GMAC 2 registers */
1256 * Marvel-PHY Registers, indirect addressed over GMAC
1655 * GMAC registers
1657 * The GMAC registers are 16 or 32 bits wide.
1801 * GMAC Bit Definitions
1936 /* Rx GMAC FIFO Flush Mask (default) */
1939 /* Receive and Transmit GMAC FIFO Registers (YUKON only) */
1941 /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */
1942 /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */
1943 /* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
1944 /* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
1945 /* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
1946 /* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
1947 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1948 /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
1949 /* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
1950 /* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */
1951 /* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
1952 /* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
1953 /* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
1954 /* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
1956 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1979 #define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */
1980 #define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
1982 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
2001 #define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */
2002 #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */
2062 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
2077 #define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */
2078 #define GMC_RST_SET BIT_0 /* Set GMAC Reset */
2105 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
2106 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
2116 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
2117 #define GMLC_RST_CLR BIT_1 /* Clear GMAC Link Reset */
2118 #define GMLC_RST_SET BIT_0 /* Set GMAC Link Reset */