Lines Matching +full:0 +full:x65000000
102 #define VENDORID_SK 0x1148
107 #define VENDORID_MARVELL 0x11AB
112 #define VENDORID_DLINK 0x1186
117 #define DEVICEID_SK_YUKON2 0x9000
118 #define DEVICEID_SK_YUKON2_EXPR 0x9e00
123 #define DEVICEID_MRVL_8021CU 0x4340
124 #define DEVICEID_MRVL_8022CU 0x4341
125 #define DEVICEID_MRVL_8061CU 0x4342
126 #define DEVICEID_MRVL_8062CU 0x4343
127 #define DEVICEID_MRVL_8021X 0x4344
128 #define DEVICEID_MRVL_8022X 0x4345
129 #define DEVICEID_MRVL_8061X 0x4346
130 #define DEVICEID_MRVL_8062X 0x4347
131 #define DEVICEID_MRVL_8035 0x4350
132 #define DEVICEID_MRVL_8036 0x4351
133 #define DEVICEID_MRVL_8038 0x4352
134 #define DEVICEID_MRVL_8039 0x4353
135 #define DEVICEID_MRVL_8040 0x4354
136 #define DEVICEID_MRVL_8040T 0x4355
137 #define DEVICEID_MRVL_8042 0x4357
138 #define DEVICEID_MRVL_8048 0x435A
139 #define DEVICEID_MRVL_4360 0x4360
140 #define DEVICEID_MRVL_4361 0x4361
141 #define DEVICEID_MRVL_4362 0x4362
142 #define DEVICEID_MRVL_4363 0x4363
143 #define DEVICEID_MRVL_4364 0x4364
144 #define DEVICEID_MRVL_4365 0x4365
145 #define DEVICEID_MRVL_436A 0x436A
146 #define DEVICEID_MRVL_436B 0x436B
147 #define DEVICEID_MRVL_436C 0x436C
148 #define DEVICEID_MRVL_436D 0x436D
149 #define DEVICEID_MRVL_4370 0x4370
150 #define DEVICEID_MRVL_4380 0x4380
151 #define DEVICEID_MRVL_4381 0x4381
156 #define DEVICEID_DLINK_DGE550SX 0x4001
157 #define DEVICEID_DLINK_DGE560SX 0x4002
158 #define DEVICEID_DLINK_DGE560T 0x4b00
191 #define BIT_0 (1 << 0)
224 #define SHIFT0(x) ((x) << 0)
229 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
230 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
231 #define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
232 #define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
233 #define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */
234 #define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */
235 #define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */
236 #define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */
237 #define PCI_CFG_REG_0 0x90 /* 32 bit Config Register 0 */
238 #define PCI_CFG_REG_1 0x94 /* 32 bit Config Register 1 */
241 #define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */
242 #define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */
243 #define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */
244 #define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */
245 #define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */
246 #define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */
247 #define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */
248 #define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */
249 #define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */
252 #define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */
253 #define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */
254 #define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */
255 #define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */
256 #define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */
257 #define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */
258 #define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */
259 #define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */
272 /* 0 = Disable addr. dec */
274 #define PCI_PAGE_16 (0L<<20)/* 16 k pages */
287 #define PCI_SKEW_DAS (0xfL<<4)/* Bit 7.. 4: Skew Ctrl, DAS Ext */
288 #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */
292 #define PCI_VPD_WR_THR (0xff<<24) /* Bit 31..24: VPD Write Threshold */
293 #define PCI_DEV_SEL (0x7f<<17) /* Bit 23..17: EEPROM Device Select */
294 #define PCI_VPD_ROM_SZ (0x07<<14) /* Bit 16..14: VPD ROM Size */
296 #define PCI_PATCH_DIR (0x0f<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */
301 #define PCI_EXT_PATCHS (0x0f<<4) /* Bit 7.. 4: Extended Patches 3..0 */
315 #define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */
317 #define PCI_OS_DLLR_MSK (0x0f<<20) /* Bit 23..20: DLL Row Counters Values */
318 #define PCI_OS_DLLC_MSK (0x0f<<16) /* Bit 19..16: DLL Col. Counters Values */
322 #define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */
331 #define PCI_TIMER_VALUE_MSK (0xff<<16) /* Bit 23..16: Timer Value Mask */
362 /* Bit 10.. 0: Mask for Gate Clock */
411 #define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */
412 #define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */
429 * Bank 0
431 #define B0_RAP 0x0000 /* 8 bit Register Address Port */
432 #define B0_CTST 0x0004 /* 16 bit Control/Status register */
433 #define B0_LED 0x0006 /* 8 Bit LED register */
434 #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */
435 #define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */
436 #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
437 #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */
438 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
439 #define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */
442 #define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */
443 #define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */
444 #define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */
445 #define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */
446 #define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */
458 #define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */
459 #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */
460 #define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */
461 #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */
462 #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */
463 #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */
464 #define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */
465 #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */
466 #define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */
467 #define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */
468 #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */
469 #define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */
470 #define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */
471 #define B2_TI_VAL 0x0134 /* 32 bit Timer Value */
472 #define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */
473 #define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */
474 #define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/
475 #define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */
476 #define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */
477 #define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */
478 #define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */
479 #define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */
480 #define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */
481 #define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */
482 #define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */
483 #define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */
484 #define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */
485 #define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */
486 #define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */
488 #define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */
489 #define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */
495 #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */
496 #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */
497 #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */
504 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
508 #define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */
509 #define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */
510 #define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */
511 #define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */
512 #define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */
513 #define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */
514 #define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */
515 #define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */
516 #define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */
517 #define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */
518 #define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/
519 #define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/
520 #define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */
521 #define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */
522 #define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */
528 #define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/
529 #define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */
530 #define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */
531 #define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */
532 #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
533 #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */
534 #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */
539 #define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */
541 #define KEY_IDX_0 0 /* offset for location of KEY 0 */
545 /* 0x0280 - 0x0292: MAC 2 */
547 ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex))
553 #define B8_Q_REGS 0x0400
556 #define Q_D 0x00 /* 8*32 bit Current Descriptor */
557 #define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */
558 #define Q_DONE 0x24 /* 16 bit Done Index */
559 #define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */
560 #define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */
561 #define Q_BC 0x30 /* 32 bit Current Byte Counter */
562 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */
563 #define Q_F 0x38 /* 32 bit Flag Register */
564 #define Q_T1 0x3c /* 32 bit Test Register 1 */
565 #define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */
566 #define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */
567 #define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */
568 #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */
569 #define Q_WM 0x40 /* 16 bit FIFO Watermark */
570 #define Q_AL 0x42 /* 8 bit FIFO Alignment */
571 #define Q_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */
572 #define Q_RSL 0x46 /* 8 bit FIFO Read Shadow Level */
573 #define Q_RP 0x48 /* 8 bit FIFO Read Pointer */
574 #define Q_RL 0x4a /* 8 bit FIFO Read Level */
575 #define Q_WP 0x4c /* 8 bit FIFO Write Pointer */
576 #define Q_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */
577 #define Q_WL 0x4e /* 8 bit FIFO Write Level */
578 #define Q_WSL 0x4f /* 8 bit FIFO Write Shadow Level */
583 #define Y2_B8_PREF_REGS 0x0450
585 #define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */
586 #define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */
587 #define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */
588 #define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/
589 #define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */
590 #define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */
591 #define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */
592 #define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */
593 #define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */
594 #define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */
596 #define PREF_UNIT_MASK_IDX 0x0fff
604 #define B16_RAM_REGS 0x0800
607 #define RB_START 0x00 /* 32 bit RAM Buffer Start Address */
608 #define RB_END 0x04 /* 32 bit RAM Buffer End Address */
609 #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */
610 #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */
611 #define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */
612 #define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */
613 #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */
614 #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */
615 #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */
616 #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */
617 #define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */
618 #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */
619 #define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */
625 #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */
626 #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
627 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */
628 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
629 #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */
630 #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */
631 #define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
632 #define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
633 #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */
634 #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
635 #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
636 #define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
637 #define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
642 /* 0x0c80 - 0x0cbf: MAC 2 */
643 /* 0x0cc0 - 0x0cff: reserved */
649 #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */
650 #define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
651 #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */
652 #define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */
653 #define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
654 #define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */
655 #define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
656 #define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
657 #define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
658 #define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
663 /* 0x0d80 - 0x0dbf: MAC 2 */
664 /* 0x0daa - 0x0dff: reserved */
670 #define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */
671 #define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */
672 #define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */
673 #define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */
675 #define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */
676 #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */
677 #define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */
679 #define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */
680 #define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */
681 #define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */
682 #define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */
684 #define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */
685 #define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */
686 #define B28_Y2_CPU_WDOG 0x0e48 /* 32 bit Watchdog Register */
687 #define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */
688 #define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */
689 #define B28_Y2_ASF_HCU_CCSR 0x0e68 /* 32 bit ASF HCU CCSR (Yukon EX) */
690 #define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */
691 #define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */
692 #define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */
693 #define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */
694 #define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */
701 #define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */
702 #define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */
703 #define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */
704 #define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */
705 #define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */
706 #define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */
707 #define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */
708 #define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */
709 #define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */
710 #define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */
712 #define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */
713 #define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */
714 #define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */
715 #define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */
716 #define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */
717 #define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */
718 #define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */
720 #define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */
721 #define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */
722 #define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */
723 #define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */
724 #define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */
725 #define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */
726 #define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */
727 #define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */
728 #define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */
729 #define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */
730 #define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */
731 #define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */
733 #define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */
734 #define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */
735 #define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */
736 #define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */
742 #define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */
743 #define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */
744 #define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */
745 #define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */
746 #define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */
750 #define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */
752 #define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */
753 #define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */
754 #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */
755 #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */
756 #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */
757 #define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */
758 #define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */
759 #define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */
763 #define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */
764 #define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */
768 #define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */
769 #define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */
774 #define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */
775 #define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */
778 #define Y2_CFG_SPC 0x1c00
779 #define BASE_GMAC_1 0x2800 /* GMAC 1 registers */
780 #define BASE_GMAC_2 0x3800 /* GMAC 2 registers */
848 #define Y2_IS_L1_MASK 0x0000001f /* IRQ Mask for port 1 */
850 #define Y2_IS_L2_MASK 0x00001f00 /* IRQ Mask for port 2 */
852 #define Y2_IS_ALL_MSK 0xef001f1f /* All Interrupt bits */
891 #define CFG_CHIP_R_MSK (0x0f<<4) /* Bit 7.. 4: Chip Revision */
893 #define CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
896 #define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */
897 #define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */
898 #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
899 #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
900 #define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
901 #define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */
902 #define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */
903 #define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
904 #define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */
905 #define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */
906 #define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */
907 #define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */
908 #define CHIP_ID_YUKON_UNKNOWN 0xbb
909 #define CHIP_ID_YUKON_OPT 0xbc /* Chip ID for YUKON-2 Optima */
911 #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */
916 #define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */
923 #define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */
928 #define CHIP_REV_YU_SU_A0 0 /* Chip Rev. for Yukon-2 SUPR A0 */
933 #define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */
937 #define Y2_STATUS_LNK1_INAC BIT_3 /* Status Link 1 inactiv (0 = activ) */
943 #define CFG_LED_MODE_MSK (0x07<<2) /* Bit 4.. 2: LED Mode Mask */
951 #define B2_E3_RES_MASK 0x0f
955 #define Y2_CLK_DIV_VAL_MSK (0xff<<16) /* Bit 23..16: Clock Divisor Value */
958 #define Y2_CLK_DIV_VAL2_MSK (0x07<<21) /* Bit 23..21: Clock Divisor Value */
959 #define Y2_CLK_SELECT2_MSK (0x1f<<16) /* Bit 20..16: Clock Select */
980 #define DPT_MSK 0x00ffffff /* Bit 23.. 0: Desc Poll Timer Bits */
998 #define GLB_GPIO_CLK_DBG_MSK 0x3c000000 /* Clock Debug */
1003 #define GLB_GPIO_TEST_SEL_MSK 0x00001800 /* Testmode Select */
1010 #define I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */
1011 #define I2C_DEV_SEL (0x7f<<9) /* Bit 15.. 9: I2C Device Select */
1014 #define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */
1041 #define BSC_SRC BIT_0 /* Blink Source, 0=Off / 1=On */
1049 #define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */
1053 #define RAM_ADR_RAN 0x0007ffff /* Bit 18.. 0: RAM Address Range */
1069 #define TXA_MAX_VAL 0x00ffffff/* Bit 23.. 0: Max TXA Timer/Cnt Val */
1093 #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */
1126 /* Bit 10..0: same as for Rx */
1136 #define F_FIFO_LEVEL (0x1f<<16)
1138 #define F_WATER_MARK 0x0007ff/* Bit 10.. 0: Watermark */
1158 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
1188 #define MSK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */
1189 #define MSK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */
1190 #define MSK_ECU_AE_THR 0x0070 /* Almost Empty Threshold */
1191 #define MSK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */
1192 #define MSK_ECU_JUMBO_WM 0x01
1194 #define MSK_BMU_RX_WM 0x600 /* BMU Rx Watermark */
1195 #define MSK_BMU_TX_WM 0x600 /* BMU Tx Watermark */
1196 /* performance sensitive drivers should set this define to 0x80 */
1197 #define MSK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */
1200 #define Q_R1 0x0000 /* Receive Queue 1 */
1201 #define Q_R2 0x0080 /* Receive Queue 2 */
1202 #define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */
1203 #define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */
1204 #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */
1205 #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */
1207 #define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */
1208 #define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */
1209 #define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */
1210 #define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */
1252 #define WOL_PATT_MATCH_PME_ALL 0x7f
1258 #define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */
1259 #define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */
1260 #define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
1261 #define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
1262 #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
1263 #define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
1264 #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
1265 #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */
1266 #define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
1268 #define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
1269 #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
1270 /* 0x0b - 0x0e: reserved */
1271 #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
1272 #define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */
1273 #define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */
1274 #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */
1275 #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */
1276 #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */
1277 #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */
1278 #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */
1279 #define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */
1280 #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */
1281 #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */
1282 #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1283 #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */
1284 #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */
1285 #define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */
1286 #define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */
1289 #define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */
1290 #define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */
1291 #define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */
1292 #define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */
1293 #define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */
1308 #define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */
1317 #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */
1319 #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */
1320 #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */
1321 #define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */
1324 #define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */
1326 #define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1011) */
1327 #define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */
1328 #define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */
1329 #define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */
1330 #define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */
1331 #define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */
1340 #define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */
1349 #define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */
1354 #define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */
1363 #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */
1395 #define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */
1424 #define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */
1442 #define PHY_M_PS_RES_SPEED BIT_14 /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1489 /* 01X=0; 110=2.5; 111=25 (MHz) */
1517 #define PULS_NO_STR 0 /* no pulse stretching */
1528 #define BLINK_42MS 0 /* 42 ms */
1541 #define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */
1543 #define MO_LED_NORM 0
1553 #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */
1566 #define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1569 #define PHY_M_CABD_ENA_TEST BIT_15 /* Enable Test (Page 0) */
1573 #define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */
1575 #define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */
1578 #define CABD_STAT_NORMAL 0
1585 #define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */
1586 #define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */
1587 #define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */
1593 #define LED_PAR_CTRL_COLX 0x00
1594 #define LED_PAR_CTRL_ERROR 0x01
1595 #define LED_PAR_CTRL_DUPLEX 0x02
1596 #define LED_PAR_CTRL_DP_COL 0x03
1597 #define LED_PAR_CTRL_SPEED 0x04
1598 #define LED_PAR_CTRL_LINK 0x05
1599 #define LED_PAR_CTRL_TX 0x06
1600 #define LED_PAR_CTRL_RX 0x07
1601 #define LED_PAR_CTRL_ACT 0x08
1602 #define LED_PAR_CTRL_LNK_RX 0x09
1603 #define LED_PAR_CTRL_LNK_AC 0x0a
1604 #define LED_PAR_CTRL_ACT_BL 0x0b
1605 #define LED_PAR_CTRL_TX_BL 0x0c
1606 #define LED_PAR_CTRL_RX_BL 0x0d
1607 #define LED_PAR_CTRL_COL_BL 0x0e
1608 #define LED_PAR_CTRL_INACT 0x0f
1629 #define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */
1630 #define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */
1631 #define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1632 #define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1640 #define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */
1641 #define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1642 #define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1643 #define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1644 #define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1645 #define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1665 #define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */
1666 #define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */
1667 #define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */
1668 #define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */
1669 #define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */
1670 #define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */
1671 #define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */
1674 #define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */
1675 #define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */
1676 #define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */
1677 #define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */
1678 #define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */
1679 #define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */
1682 #define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */
1683 #define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */
1684 #define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */
1685 #define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */
1688 #define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */
1689 #define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */
1690 #define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */
1693 #define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */
1694 #define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */
1695 #define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1698 #define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */
1699 #define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */
1700 #define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */
1703 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1711 (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */
1850 #define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */
1854 #define TX_COL_DEF 0x04
1864 #define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */
1865 #define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */
1866 #define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */
1874 #define TX_JAM_LEN_DEF 0x03
1875 #define TX_JAM_IPG_DEF 0x0b
1876 #define TX_IPG_JAM_DEF 0x1c
1877 #define TX_BOF_LIM_DEF 0x04
1880 #define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */
1885 #define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */
1890 #define DATA_BLIND_DEF 0x04
1891 #define IPG_DATA_DEF 0x1e
1894 #define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */
1895 #define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */
1896 #define GM_SMI_CT_OP_RD BIT_5 /* OpCode Read (0=Write)*/
1908 #define GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */
1996 /* Bits 3..0: same as for RX_GMF_CTRL_T */
2001 #define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */
2002 #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */
2026 #define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */
2046 #define Y2_ASF_HCU_CCSR_ASF_RESET 0
2089 #define GPC_HWCFG_M_0 BIT_20 /* HWCFG_MODE[0] */
2090 #define GPC_ANEG_0 BIT_19 /* ANEG[0] */
2101 #define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */
2120 #define MSK_PORT_A 0
2125 bus_write_4((sc)->msk_res[0], (reg), (val))
2127 bus_write_2((sc)->msk_res[0], (reg), (val))
2129 bus_write_1((sc)->msk_res[0], (reg), (val))
2132 bus_read_4((sc)->msk_res[0], (reg))
2134 bus_read_2((sc)->msk_res[0], (reg))
2136 bus_read_1((sc)->msk_res[0], (reg))
2139 bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2141 bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2143 bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2146 bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2148 bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2150 bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2174 #define PHY_ADDR_MARV 0
2176 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL)
2201 #define STLE_TXA1_MSKL 0x00000fff
2202 #define STLE_TXA1_SHIFTL 0
2205 #define STLE_TXS1_MSKL 0x00fff000
2209 #define STLE_TXA2_MSKL 0xff000000
2211 #define STLE_TXA2_MSKH 0x000f
2216 #define STLE_TXS2_MSKL 0x00000000
2217 #define STLE_TXS2_SHIFTL 0
2218 #define STLE_TXS2_MSKH 0xfff0
2222 #define HW_OWNER 0x80000000
2223 #define SW_OWNER 0x00000000
2225 #define PU_PUTIDX_VALID 0x10000000
2228 #define UDPTCP 0x00010000
2229 #define CALSUM 0x00020000
2230 #define WR_SUM 0x00040000
2231 #define INIT_SUM 0x00080000
2232 #define LOCK_SUM 0x00100000
2233 #define INS_VLAN 0x00200000
2234 #define FRC_STAT 0x00400000
2235 #define EOP 0x00800000
2237 #define TX_LOCK 0x01000000
2238 #define BUF_SEND 0x02000000
2239 #define PACKET_SEND 0x04000000
2241 #define NO_WARNING 0x40000000
2242 #define NO_UPDATE 0x80000000
2245 #define OP_TCPWRITE 0x11000000
2246 #define OP_TCPSTART 0x12000000
2247 #define OP_TCPINIT 0x14000000
2248 #define OP_TCPLCK 0x18000000
2254 #define OP_ADDR64 0x21000000
2255 #define OP_VLAN 0x22000000
2257 #define OP_LRGLEN 0x24000000
2259 #define OP_MSS 0x28000000
2261 #define OP_BUFFER 0x40000000
2262 #define OP_PACKET 0x41000000
2263 #define OP_LARGESEND 0x43000000
2266 #define OP_RXSTAT 0x60000000
2267 #define OP_RXTIMESTAMP 0x61000000
2268 #define OP_RXVLAN 0x62000000
2269 #define OP_RXCHKS 0x64000000
2272 #define OP_RSS_HASH 0x65000000
2273 #define OP_TXINDEXLE 0x68000000
2276 #define OP_PUTIDX 0x70000000
2278 #define STLE_OP_MASK 0xff000000
2279 #define STLE_CSS_MASK 0x00ff0000
2280 #define STLE_LEN_MASK 0x0000ffff
2283 #define CSS_TCPUDP_CSUM_OK 0x00800000
2284 #define CSS_UDP 0x00400000
2285 #define CSS_TCP 0x00200000
2286 #define CSS_IPFRAG 0x00100000
2287 #define CSS_IPV6 0x00080000
2288 #define CSS_IPV4_CSUM_OK 0x00040000
2289 #define CSS_IPV4 0x00020000
2290 #define CSS_PORT 0x00010000
2295 #define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */
2309 #define BMU_CHECK (0x55<<16) /* Default BMU check */
2310 #define BMU_TCP_CHECK (0x56<<16) /* Descr with TCP ext */
2311 #define BMU_UDP_CHECK (0x57<<16) /* Descr with UDP ext (YUKON only) */
2312 #define BMU_BBC 0xffff /* Bit 15.. 0: Buffer Byte Counter */
2326 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
2436 #define MSK_PCI_BUS 0
2562 #define MSK_FLAG_MSI 0x0001
2563 #define MSK_FLAG_FASTETHER 0x0004
2564 #define MSK_FLAG_JUMBO 0x0008
2565 #define MSK_FLAG_JUMBO_NOCSUM 0x0010
2566 #define MSK_FLAG_RAMBUF 0x0020
2567 #define MSK_FLAG_DESCV2 0x0040
2568 #define MSK_FLAG_AUTOTX_CSUM 0x0080
2569 #define MSK_FLAG_NOHWVLAN 0x0100
2570 #define MSK_FLAG_NORXCHK 0x0200
2571 #define MSK_FLAG_NORX_CSUM 0x0400
2572 #define MSK_FLAG_SUSPEND 0x2000
2573 #define MSK_FLAG_DETACH 0x4000
2574 #define MSK_FLAG_LINK 0x8000
2591 #define MSK_PHY_POWERDOWN 0