3437 		CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);  in msk_handle_hwerr()
3442 		CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);  in msk_handle_hwerr()
3932 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);  in msk_init_locked()
3933 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);  in msk_init_locked()
3934 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);  in msk_init_locked()
3935 	CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);  in msk_init_locked()
3940 			CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL),  in msk_init_locked()
3950 			CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F),  in msk_init_locked()
3956 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);  in msk_init_locked()
3957 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);  in msk_init_locked()
3958 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);  in msk_init_locked()
3959 	CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);  in msk_init_locked()
3963                 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);  in msk_init_locked()
3977 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg);  in msk_init_locked()
4151 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);  in msk_stop()
4152 	val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));  in msk_stop()
4155 			CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),  in msk_stop()
4157 			val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));  in msk_stop()
4176 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),  in msk_stop()
4212 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),  in msk_stop()