Lines Matching +full:0 +full:x01010000
78 #define MRSAS_TBOLT 0x005b
79 #define MRSAS_INVADER 0x005d
80 #define MRSAS_FURY 0x005f
81 #define MRSAS_INTRUDER 0x00ce
82 #define MRSAS_INTRUDER_24 0x00cf
83 #define MRSAS_CUTLASS_52 0x0052
84 #define MRSAS_CUTLASS_53 0x0053
86 #define MRSAS_VENTURA 0x0014
87 #define MRSAS_CRUSADER 0x0015
88 #define MRSAS_HARPOON 0x0016
89 #define MRSAS_TOMCAT 0x0017
90 #define MRSAS_VENTURA_4PORT 0x001B
91 #define MRSAS_CRUSADER_4PORT 0x001C
92 #define MRSAS_AERO_10E0 0x10E0
93 #define MRSAS_AERO_10E1 0x10E1
94 #define MRSAS_AERO_10E2 0x10E2
95 #define MRSAS_AERO_10E3 0x10E3
96 #define MRSAS_AERO_10E4 0x10E4
97 #define MRSAS_AERO_10E5 0x10E5
98 #define MRSAS_AERO_10E6 0x10E6
99 #define MRSAS_AERO_10E7 0x10E7
104 #define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF
105 #define MRSAS_FWSTATE_SGE_MASK 0x00FF0000
120 #define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF
121 #define MRSAS_DEFAULT_TIMEOUT 0x14 /* Temporarily set */
122 #define DONE 0
131 #define MR_STREAM_BITMAP 0x76543210
134 #define ZERO_LAST_STREAM 0x0fffffff
146 #define MRSAS_INFO (1 << 0)
158 } while (0)
160 #define le32_to_cpus(x) do { *((u_int32_t *)(x)) = le32toh((*(u_int32_t *)x)); } while (0)
161 #define le16_to_cpus(x) do { *((u_int16_t *)(x)) = le16toh((*(u_int16_t *)x)); } while (0)
165 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
190 u_int8_t priority; /* 0x1D MR_PRIORITY_RANGE */
191 u_int8_t numSGEExt; /* 0x1E 1M IO support */
192 u_int8_t resvd2; /* 0x1F */
197 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
271 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
272 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
273 #define MPI2_VERSION_MAJOR (0x02)
274 #define MPI2_VERSION_MINOR (0x00)
275 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
277 #define MPI2_VERSION_MINOR_MASK (0x00FF)
278 #define MPI2_VERSION_MINOR_SHIFT (0)
281 #define MPI2_HEADER_VERSION_UNIT (0x10)
282 #define MPI2_HEADER_VERSION_DEV (0x00)
283 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
285 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
286 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
288 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
289 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
290 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
291 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
292 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
293 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
294 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
295 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
296 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
297 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03)
298 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06)
299 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
300 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
301 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
302 #define MPI2_SCSIIO_CONTROL_READ (0x02000000)
303 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
304 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
305 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
306 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
307 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
308 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
309 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
310 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
311 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
312 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
313 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
314 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
343 u_int8_t CDB[20]; /* 0x00 */
344 u_int32_t PrimaryReferenceTag; /* 0x14 */
345 u_int16_t PrimaryApplicationTag;/* 0x18 */
346 u_int16_t PrimaryApplicationTagMask; /* 0x1A */
347 u_int32_t TransferLength; /* 0x1C */
412 u_int16_t DevHandle; /*0x00 */
413 u_int8_t ChainOffset; /*0x02 */
414 u_int8_t Function; /*0x03 */
415 u_int8_t Reserved1; /*0x04 */
416 u_int8_t TaskType; /*0x05 */
417 u_int8_t Reserved2; /*0x06 */
418 u_int8_t MsgFlags; /*0x07 */
419 u_int8_t VP_ID; /*0x08 */
420 u_int8_t VF_ID; /*0x09 */
421 u_int16_t Reserved3; /*0x0A */
422 u_int8_t LUN[8]; /*0x0C */
423 u_int32_t Reserved4[7]; /*0x14 */
424 u_int16_t TaskMID; /*0x30 */
425 u_int16_t Reserved5; /*0x32 */
430 u_int16_t DevHandle; /*0x00 */
431 u_int8_t MsgLength; /*0x02 */
432 u_int8_t Function; /*0x03 */
433 u_int8_t ResponseCode; /*0x04 */
434 u_int8_t TaskType; /*0x05 */
435 u_int8_t Reserved1; /*0x06 */
436 u_int8_t MsgFlags; /*0x07 */
437 u_int8_t VP_ID; /*0x08 */
438 u_int8_t VF_ID; /*0x09 */
439 u_int16_t Reserved2; /*0x0A */
440 u_int16_t Reserved3; /*0x0C */
441 u_int16_t IOCStatus; /*0x0E */
442 u_int32_t IOCLogInfo; /*0x10 */
443 u_int32_t TerminationCount; /*0x14 */
444 u_int32_t ResponseInfo; /*0x18 */
477 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
478 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
479 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
480 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
481 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
482 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
483 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
484 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09)
485 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A)
488 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
489 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
490 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
491 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05)
492 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
493 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
494 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A)
495 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
502 u_int16_t DevHandle; /* 0x00 */
503 u_int8_t ChainOffset; /* 0x02 */
504 u_int8_t Function; /* 0x03 */
505 u_int16_t Reserved1; /* 0x04 */
506 u_int8_t Reserved2; /* 0x06 */
507 u_int8_t MsgFlags; /* 0x07 */
508 u_int8_t VP_ID; /* 0x08 */
509 u_int8_t VF_ID; /* 0x09 */
510 u_int16_t Reserved3; /* 0x0A */
511 u_int32_t SenseBufferLowAddress;/* 0x0C */
512 u_int16_t SGLFlags; /* 0x10 */
513 u_int8_t SenseBufferLength; /* 0x12 */
514 u_int8_t Reserved4; /* 0x13 */
515 u_int8_t SGLOffset0; /* 0x14 */
516 u_int8_t SGLOffset1; /* 0x15 */
517 u_int8_t SGLOffset2; /* 0x16 */
518 u_int8_t SGLOffset3; /* 0x17 */
519 u_int32_t SkipCount; /* 0x18 */
520 u_int32_t DataLength; /* 0x1C */
521 u_int32_t BidirectionalDataLength; /* 0x20 */
522 u_int16_t IoFlags; /* 0x24 */
523 u_int16_t EEDPFlags; /* 0x26 */
524 u_int32_t EEDPBlockSize; /* 0x28 */
525 u_int32_t SecondaryReferenceTag;/* 0x2C */
526 u_int16_t SecondaryApplicationTag; /* 0x30 */
527 u_int16_t ApplicationTagTranslationMask; /* 0x32 */
528 u_int8_t LUN[8]; /* 0x34 */
529 u_int32_t Control; /* 0x3C */
530 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
531 RAID_CONTEXT_UNION RaidContext; /* 0x60 */
532 MPI2_SGE_IO_UNION SGL; /* 0x80 */
547 u_int8_t RequestFlags; /* 0x00 */
548 u_int8_t MSIxIndex; /* 0x01 */
549 u_int16_t SMID; /* 0x02 */
550 u_int16_t LMID; /* 0x04 */
551 u_int16_t DescriptorTypeDependent; /* 0x06 */
559 u_int8_t RequestFlags; /* 0x00 */
560 u_int8_t MSIxIndex; /* 0x01 */
561 u_int16_t SMID; /* 0x02 */
562 u_int16_t LMID; /* 0x04 */
563 u_int16_t Reserved1; /* 0x06 */
571 u_int8_t RequestFlags; /* 0x00 */
572 u_int8_t MSIxIndex; /* 0x01 */
573 u_int16_t SMID; /* 0x02 */
574 u_int16_t LMID; /* 0x04 */
575 u_int16_t DevHandle; /* 0x06 */
583 u_int8_t RequestFlags; /* 0x00 */
584 u_int8_t MSIxIndex; /* 0x01 */
585 u_int16_t SMID; /* 0x02 */
586 u_int16_t LMID; /* 0x04 */
587 u_int16_t IoIndex; /* 0x06 */
595 u_int8_t RequestFlags; /* 0x00 */
596 u_int8_t MSIxIndex; /* 0x01 */
597 u_int16_t SMID; /* 0x02 */
598 u_int16_t LMID; /* 0x04 */
599 u_int16_t Reserved; /* 0x06 */
624 u_int8_t ReplyFlags; /* 0x00 */
625 u_int8_t MSIxIndex; /* 0x01 */
626 u_int16_t DescriptorTypeDependent1; /* 0x02 */
627 u_int32_t DescriptorTypeDependent2; /* 0x04 */
633 u_int8_t ReplyFlags; /* 0x00 */
634 u_int8_t MSIxIndex; /* 0x01 */
635 u_int16_t SMID; /* 0x02 */
636 u_int32_t ReplyFrameAddress; /* 0x04 */
642 u_int8_t ReplyFlags; /* 0x00 */
643 u_int8_t MSIxIndex; /* 0x01 */
644 u_int16_t SMID; /* 0x02 */
645 u_int16_t TaskTag; /* 0x04 */
646 u_int16_t Reserved1; /* 0x06 */
654 u_int8_t ReplyFlags; /* 0x00 */
655 u_int8_t MSIxIndex; /* 0x01 */
656 u_int16_t SMID; /* 0x02 */
657 u_int8_t SequenceNumber; /* 0x04 */
658 u_int8_t Reserved1; /* 0x05 */
659 u_int16_t IoIndex; /* 0x06 */
667 u_int8_t ReplyFlags; /* 0x00 */
668 u_int8_t MSIxIndex; /* 0x01 */
669 u_int8_t VP_ID; /* 0x02 */
670 u_int8_t Flags; /* 0x03 */
671 u_int16_t InitiatorDevHandle; /* 0x04 */
672 u_int16_t IoIndex; /* 0x06 */
680 u_int8_t ReplyFlags; /* 0x00 */
681 u_int8_t MSIxIndex; /* 0x01 */
682 u_int16_t SMID; /* 0x02 */
683 u_int32_t Reserved; /* 0x04 */
719 u_int8_t WhoInit; /* 0x00 */
720 u_int8_t Reserved1; /* 0x01 */
721 u_int8_t ChainOffset; /* 0x02 */
722 u_int8_t Function; /* 0x03 */
723 u_int16_t Reserved2; /* 0x04 */
724 u_int8_t Reserved3; /* 0x06 */
725 u_int8_t MsgFlags; /* 0x07 */
726 u_int8_t VP_ID; /* 0x08 */
727 u_int8_t VF_ID; /* 0x09 */
728 u_int16_t Reserved4; /* 0x0A */
729 u_int16_t MsgVersion; /* 0x0C */
730 u_int16_t HeaderVersion; /* 0x0E */
731 u_int32_t Reserved5; /* 0x10 */
732 u_int16_t Reserved6; /* 0x14 */
733 u_int8_t HostPageSize; /* 0x16 */
734 u_int8_t HostMSIxVectors; /* 0x17 */
735 u_int16_t Reserved8; /* 0x18 */
736 u_int16_t SystemRequestFrameSize; /* 0x1A */
737 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */
738 u_int16_t ReplyFreeQueueDepth; /* 0x1E */
739 u_int32_t SenseBufferAddressHigh; /* 0x20 */
740 u_int32_t SystemReplyAddressHigh; /* 0x24 */
741 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */
742 u_int64_t ReplyDescriptorPostQueueAddress; /* 0x30 */
743 u_int64_t ReplyFreeQueueAddress;/* 0x38 */
744 u_int64_t TimeStamp; /* 0x40 */
751 #define MR_PD_INVALID 0xFFFF
752 #define MR_DEVHANDLE_INVALID 0xFFFF
775 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
776 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102
777 #define MR_DCMD_PD_MFI_TASK_MGMT 0x0200e100
779 #define MR_DCMD_PD_GET_INFO 0x02020000
791 #define VD_EXT_DEBUG 0
921 u_int8_t reserved3[0x80 - 0x38];
949 * FW will populate the array like this. [0xFF, 0xFF, 0xFF, 0xFF,
950 * 0x0,.....]. This is to help reduce the entire strcture size if
1088 /* span[7:5], arm[4:0] */
1154 RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0, /* MR_DEV_HANDLE_INFO data */
1223 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1224 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1225 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1226 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1227 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1228 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1229 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1232 #define MPI2_SGE_FLAGS_SHIFT (0x02)
1233 #define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0)
1234 #define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00)
1235 #define IEEE_SGE_FLAGS_FORMAT_PQI (0x01)
1236 #define IEEE_SGE_FLAGS_FORMAT_NVME (0x02)
1237 #define IEEE_SGE_FLAGS_FORMAT_AHCI (0x03)
1239 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1240 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1241 #define MPI26_IEEE_SGE_FLAGS_NSF_PQI (0x04)
1242 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1243 #define MPI26_IEEE_SGE_FLAGS_NSF_AHCI_PRDT (0x0C)
1244 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1265 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF
1266 #define MR_MIN_MAP_SIZE 0x10000
1333 #define MFI_STATE_MASK 0xF0000000
1334 #define MFI_STATE_UNDEFINED 0x00000000
1335 #define MFI_STATE_BB_INIT 0x10000000
1336 #define MFI_STATE_FW_INIT 0x40000000
1337 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
1338 #define MFI_STATE_FW_INIT_2 0x70000000
1339 #define MFI_STATE_DEVICE_SCAN 0x80000000
1340 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
1341 #define MFI_STATE_FLUSH_CACHE 0xA0000000
1342 #define MFI_STATE_READY 0xB0000000
1343 #define MFI_STATE_OPERATIONAL 0xC0000000
1344 #define MFI_STATE_FAULT 0xF0000000
1345 #define MFI_RESET_REQUIRED 0x00000001
1346 #define MFI_RESET_ADAPTER 0x00000002
1361 #define WRITE_SEQUENCE_OFFSET (0x0000000FC)
1362 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8)
1363 #define DIAG_WRITE_ENABLE (0x00000080)
1364 #define DIAG_RESET_ADAPTER (0x00000004)
1366 #define MFI_ADP_RESET 0x00000040
1367 #define MFI_INIT_ABORT 0x00000001
1368 #define MFI_INIT_READY 0x00000002
1369 #define MFI_INIT_MFIMODE 0x00000004
1370 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
1371 #define MFI_INIT_HOTPLUG 0x00000010
1372 #define MFI_STOP_ADP 0x00000020
1380 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
1381 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
1382 #define MFI_FRAME_SGL32 0x0000
1383 #define MFI_FRAME_SGL64 0x0002
1384 #define MFI_FRAME_SENSE32 0x0000
1385 #define MFI_FRAME_SENSE64 0x0004
1386 #define MFI_FRAME_DIR_NONE 0x0000
1387 #define MFI_FRAME_DIR_WRITE 0x0008
1388 #define MFI_FRAME_DIR_READ 0x0010
1389 #define MFI_FRAME_DIR_BOTH 0x0018
1390 #define MFI_FRAME_IEEE 0x0020
1395 #define MFI_CMD_STATUS_POLL_MODE 0xFF
1400 #define MFI_CMD_INIT 0x00
1401 #define MFI_CMD_LD_READ 0x01
1402 #define MFI_CMD_LD_WRITE 0x02
1403 #define MFI_CMD_LD_SCSI_IO 0x03
1404 #define MFI_CMD_PD_SCSI_IO 0x04
1405 #define MFI_CMD_DCMD 0x05
1406 #define MFI_CMD_ABORT 0x06
1407 #define MFI_CMD_SMP 0x07
1408 #define MFI_CMD_STP 0x08
1409 #define MFI_CMD_INVALID 0xff
1411 #define MR_DCMD_CTRL_GET_INFO 0x01010000
1412 #define MR_DCMD_LD_GET_LIST 0x03010000
1413 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
1414 #define MR_FLUSH_CTRL_CACHE 0x01
1415 #define MR_FLUSH_DISK_CACHE 0x02
1417 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
1418 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
1419 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
1421 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
1422 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
1423 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
1424 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
1426 #define MR_DCMD_CLUSTER 0x08000000
1427 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
1428 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
1429 #define MR_DCMD_PD_LIST_QUERY 0x02010100
1431 #define MR_DCMD_CTRL_MISC_CPX 0x0100e200
1432 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201
1433 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202
1434 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203
1437 #define MR_CPX_DIR_READ 0
1440 #define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200
1442 #define MR_EVT_CFG_CLEARED 0x0004
1444 #define MR_EVT_LD_STATE_CHANGE 0x0051
1445 #define MR_EVT_PD_INSERTED 0x005b
1446 #define MR_EVT_PD_REMOVED 0x0070
1447 #define MR_EVT_LD_CREATED 0x008a
1448 #define MR_EVT_LD_DELETED 0x008b
1449 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
1450 #define MR_EVT_LD_OFFLINE 0x00fc
1451 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
1452 #define MR_EVT_CTRL_PERF_COLLECTION 0x017e
1458 MFI_STAT_OK = 0x00,
1459 MFI_STAT_INVALID_CMD = 0x01,
1460 MFI_STAT_INVALID_DCMD = 0x02,
1461 MFI_STAT_INVALID_PARAMETER = 0x03,
1462 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
1463 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
1464 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
1465 MFI_STAT_APP_IN_USE = 0x07,
1466 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
1467 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
1468 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
1469 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
1470 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
1471 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
1472 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
1473 MFI_STAT_FLASH_BUSY = 0x0f,
1474 MFI_STAT_FLASH_ERROR = 0x10,
1475 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
1476 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
1477 MFI_STAT_FLASH_NOT_OPEN = 0x13,
1478 MFI_STAT_FLASH_NOT_STARTED = 0x14,
1479 MFI_STAT_FLUSH_FAILED = 0x15,
1480 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
1481 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
1482 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
1483 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
1484 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
1485 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
1486 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
1487 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
1488 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
1489 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
1490 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
1491 MFI_STAT_MFC_HW_ERROR = 0x21,
1492 MFI_STAT_NO_HW_PRESENT = 0x22,
1493 MFI_STAT_NOT_FOUND = 0x23,
1494 MFI_STAT_NOT_IN_ENCL = 0x24,
1495 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
1496 MFI_STAT_PD_TYPE_WRONG = 0x26,
1497 MFI_STAT_PR_DISABLED = 0x27,
1498 MFI_STAT_ROW_INDEX_INVALID = 0x28,
1499 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
1500 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
1501 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
1502 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
1503 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
1504 MFI_STAT_SCSI_IO_FAILED = 0x2e,
1505 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
1506 MFI_STAT_SHUTDOWN_FAILED = 0x30,
1507 MFI_STAT_TIME_NOT_SET = 0x31,
1508 MFI_STAT_WRONG_STATE = 0x32,
1509 MFI_STAT_LD_OFFLINE = 0x33,
1510 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
1511 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
1512 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
1513 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
1514 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
1515 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
1517 MFI_STAT_INVALID_STATUS = 0xFF
1528 MR_EVT_CLASS_INFO = 0,
1537 MR_EVT_LOCALE_LD = 0x0001,
1538 MR_EVT_LOCALE_PD = 0x0002,
1539 MR_EVT_LOCALE_ENCL = 0x0004,
1540 MR_EVT_LOCALE_BBU = 0x0008,
1541 MR_EVT_LOCALE_SAS = 0x0010,
1542 MR_EVT_LOCALE_CTRL = 0x0020,
1543 MR_EVT_LOCALE_CONFIG = 0x0040,
1544 MR_EVT_LOCALE_CLUSTER = 0x0080,
1545 MR_EVT_LOCALE_ALL = 0xffff,
1593 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
1595 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
1596 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
1597 #define MRSAS_LOAD_BALANCE_FLAG 0x1
1598 #define MRSAS_DCMD_MBOX_PEND_FLAG 0x1
1599 #define HOST_DIAG_WRITE_ENABLE 0x80
1600 #define HOST_DIAG_RESET_ADAPTER 0x4
1608 #define MPI2_TYPE_CUDA 0x2
1609 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
1610 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
1611 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
1612 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
1613 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
1614 #define MR_RL_WRITE_THROUGH_MODE 0x00
1615 #define MR_RL_WRITE_BACK_MODE 0x01
1620 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8
1621 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
1622 #define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9
1623 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB
1624 #define MRSAS_SCSI_ADDL_CDB_LEN 0x18
1625 #define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20
1626 #define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60
1632 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
1633 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
1635 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
1646 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
1647 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1
1648 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
1651 #define MRSAS_FUSION_IN_RESET 0
1653 #define RAID_CTX_SPANARM_ARM_SHIFT (0)
1654 #define RAID_CTX_SPANARM_ARM_MASK (0x1f)
1656 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
1662 REGION_TYPE_UNUSED = 0,
1671 #define MRSAS_SCSI_MAX_LUNS 0
1679 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000
1680 #define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0
1685 #define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0
1686 #define MRSAS_REQ_TYPE_AEN_FETCH 0x1
1687 #define MRSAS_REQ_TYPE_PASSTHRU 0x2
1688 #define MRSAS_REQ_TYPE_GETSET_PARAM 0x3
1689 #define MRSAS_REQ_TYPE_SCSI_IO 0x4
1692 #define MRSAS_REQ_STATE_FREE 0
1698 READ_WRITE_LDIO = 0,
1705 MRSAS_DIR_UNKNOWN = 0x1,
1706 MRSAS_DIR_IN = 0x2,
1707 MRSAS_DIR_OUT = 0x4,
1708 MRSAS_DIR_NONE = 0x8,
1715 MRSAS_HBA_OPERATIONAL = 0,
1720 MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
1790 MR_PD_QUERY_TYPE_ALL = 0,
1798 #define MR_EVT_CFG_CLEARED 0x0004
1799 #define MR_EVT_LD_STATE_CHANGE 0x0051
1800 #define MR_EVT_PD_INSERTED 0x005b
1801 #define MR_EVT_PD_REMOVED 0x0070
1802 #define MR_EVT_LD_CREATED 0x008a
1803 #define MR_EVT_LD_DELETED 0x008b
1804 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
1805 #define MR_EVT_LD_OFFLINE 0x00fc
1806 #define MR_EVT_CTRL_PROP_CHANGED 0x012f
1807 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
1810 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
1811 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
1812 MR_PD_STATE_HOT_SPARE = 0x02,
1813 MR_PD_STATE_OFFLINE = 0x10,
1814 MR_PD_STATE_FAILED = 0x11,
1815 MR_PD_STATE_REBUILD = 0x14,
1816 MR_PD_STATE_ONLINE = 0x18,
1817 MR_PD_STATE_COPYBACK = 0x20,
1818 MR_PD_STATE_SYSTEM = 0x40,
2211 char package_version[0x60];
2250 u_int16_t maxPds; /* 0x780 */
2251 u_int16_t maxDedHSPs; /* 0x782 */
2252 u_int16_t maxGlobalHSPs; /* 0x784 */
2253 u_int16_t ddfSize; /* 0x786 */
2254 u_int8_t maxLdsPerArray; /* 0x788 */
2255 u_int8_t partitionsInDDF; /* 0x789 */
2256 u_int8_t lockKeyBinding; /* 0x78a */
2257 u_int8_t maxPITsPerLd; /* 0x78b */
2258 u_int8_t maxViewsPerLd; /* 0x78c */
2259 u_int8_t maxTargetId; /* 0x78d */
2260 u_int16_t maxBvlVdSize; /* 0x78e */
2262 u_int16_t maxConfigurableSSCSize; /* 0x790 */
2263 u_int16_t currentSSCsize; /* 0x792 */
2265 char expanderFwVersion[12]; /* 0x794 */
2267 u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */
2269 u_int16_t cacheMemorySize; /* 0x7A2 */
2271 struct { /* 0x7A4 */
2323 u_int8_t driverVersion[32]; /* 0x7A8 */
2324 u_int8_t maxDAPdCountSpinup60; /* 0x7C8 */
2325 u_int8_t temperatureROC; /* 0x7C9 */
2326 u_int8_t temperatureCtrl; /* 0x7CA */
2327 u_int8_t reserved4; /* 0x7CB */
2328 u_int16_t maxConfigurablePds; /* 0x7CC */
2330 u_int8_t reserved5[2]; /* 0x7CD reserved */
2353 char clusterId[16]; /* 0x7D4 */
2355 char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */
2357 struct { /* 0x7E8 */
2439 u_int8_t pad[0x800 - 0x7FE]; /* 0x7FE */
2452 #define MRSAS_IOCTL_CMD 0
2459 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
2460 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
2461 #define MR_MAX_REPLY_QUEUES_OFFSET (0x0000001F)
2462 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET (0x003FC000)
2469 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
2490 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
2491 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
2492 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
2493 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
2495 #define MFI_OB_INTR_STATUS_MASK 0x00000002
2498 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
2499 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
2500 #define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001
2501 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
2502 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
2503 #define MFI_1068_PCSR_OFFSET 0x84
2504 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
2505 #define MFI_1068_FW_READY 0xDDDD0000
2573 u_int32_t pad_0; /* 0Ch */
2591 u_int32_t pad_0; /* 0Ch */
2621 u_int32_t pad_0; /* 0Ch */
2651 u_int32_t pad_0; /* 0Ch */
2675 u_int32_t pad_0; /* 0Ch */
2703 u_int32_t pad_0; /* 0Ch */
2731 u_int32_t pad_0; /* 0Ch */
2740 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */
2741 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */
2759 u_int32_t pad_0; /* 0Ch */
2770 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */
2771 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */
2966 FW_FAULT_OCR = 0,
3159 UNKNOWN_DRIVE = 0,
3426 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF
3634 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); in mrsas_clear_bit()
3640 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); in mrsas_set_bit()
3646 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); in mrsas_test_bit()