Lines Matching refs:pci_cfg
731 mpt->pci_cfg.Command = pci_read_config(mpt->dev, PCIR_COMMAND, 2);
732 mpt->pci_cfg.LatencyTimer_LineSize =
734 mpt->pci_cfg.IO_BAR = pci_read_config(mpt->dev, PCIR_BAR(0), 4);
735 mpt->pci_cfg.Mem0_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(1), 4);
736 mpt->pci_cfg.Mem0_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(2), 4);
737 mpt->pci_cfg.Mem1_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(3), 4);
738 mpt->pci_cfg.Mem1_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(4), 4);
739 mpt->pci_cfg.ROM_BAR = pci_read_config(mpt->dev, PCIR_BIOS, 4);
740 mpt->pci_cfg.IntLine = pci_read_config(mpt->dev, PCIR_INTLINE, 1);
741 mpt->pci_cfg.PMCSR = pci_read_config(mpt->dev, 0x44, 4);
752 if (mpt->pci_cfg.reg != val) { \
755 mpt->pci_cfg.reg, val); \
772 pci_write_config(mpt->dev, PCIR_COMMAND, mpt->pci_cfg.Command, 2);
774 mpt->pci_cfg.LatencyTimer_LineSize, 2);
775 pci_write_config(mpt->dev, PCIR_BAR(0), mpt->pci_cfg.IO_BAR, 4);
776 pci_write_config(mpt->dev, PCIR_BAR(1), mpt->pci_cfg.Mem0_BAR[0], 4);
777 pci_write_config(mpt->dev, PCIR_BAR(2), mpt->pci_cfg.Mem0_BAR[1], 4);
778 pci_write_config(mpt->dev, PCIR_BAR(3), mpt->pci_cfg.Mem1_BAR[0], 4);
779 pci_write_config(mpt->dev, PCIR_BAR(4), mpt->pci_cfg.Mem1_BAR[1], 4);
780 pci_write_config(mpt->dev, PCIR_BIOS, mpt->pci_cfg.ROM_BAR, 4);
781 pci_write_config(mpt->dev, PCIR_INTLINE, mpt->pci_cfg.IntLine, 1);
782 pci_write_config(mpt->dev, 0x44, mpt->pci_cfg.PMCSR, 4);