Lines Matching +full:0 +full:x0c

158     U8                      WhoInit;                        /* 0x00 */
159 U8 Reserved1; /* 0x01 */
160 U8 ChainOffset; /* 0x02 */
161 U8 Function; /* 0x03 */
162 U16 Reserved2; /* 0x04 */
163 U8 Reserved3; /* 0x06 */
164 U8 MsgFlags; /* 0x07 */
165 U8 VP_ID; /* 0x08 */
166 U8 VF_ID; /* 0x09 */
167 U16 Reserved4; /* 0x0A */
168 U16 MsgVersion; /* 0x0C */
169 U16 HeaderVersion; /* 0x0E */
170 U32 Reserved5; /* 0x10 */
171 U16 Reserved6; /* 0x14 */
172 U8 Reserved7; /* 0x16 */
173 U8 HostMSIxVectors; /* 0x17 */
174 U16 Reserved8; /* 0x18 */
175 U16 SystemRequestFrameSize; /* 0x1A */
176 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
177 U16 ReplyFreeQueueDepth; /* 0x1E */
178 U32 SenseBufferAddressHigh; /* 0x20 */
179 U32 SystemReplyAddressHigh; /* 0x24 */
180 U64 SystemRequestFrameBaseAddress; /* 0x28 */
181 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
182 U64 ReplyFreeQueueAddress; /* 0x38 */
183 U64 TimeStamp; /* 0x40 */
188 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
189 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
190 #define MPI2_WHOINIT_ROM_BIOS (0x02)
191 #define MPI2_WHOINIT_PCI_PEER (0x03)
192 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
193 #define MPI2_WHOINIT_MANUFACTURER (0x05)
196 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
198 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
199 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
202 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
204 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
205 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
213 U8 WhoInit; /* 0x00 */
214 U8 Reserved1; /* 0x01 */
215 U8 MsgLength; /* 0x02 */
216 U8 Function; /* 0x03 */
217 U16 Reserved2; /* 0x04 */
218 U8 Reserved3; /* 0x06 */
219 U8 MsgFlags; /* 0x07 */
220 U8 VP_ID; /* 0x08 */
221 U8 VF_ID; /* 0x09 */
222 U16 Reserved4; /* 0x0A */
223 U16 Reserved5; /* 0x0C */
224 U16 IOCStatus; /* 0x0E */
225 U32 IOCLogInfo; /* 0x10 */
236 U16 Reserved1; /* 0x00 */
237 U8 ChainOffset; /* 0x02 */
238 U8 Function; /* 0x03 */
239 U16 Reserved2; /* 0x04 */
240 U8 Reserved3; /* 0x06 */
241 U8 MsgFlags; /* 0x07 */
242 U8 VP_ID; /* 0x08 */
243 U8 VF_ID; /* 0x09 */
244 U16 Reserved4; /* 0x0A */
251 U16 MsgVersion; /* 0x00 */
252 U8 MsgLength; /* 0x02 */
253 U8 Function; /* 0x03 */
254 U16 HeaderVersion; /* 0x04 */
255 U8 IOCNumber; /* 0x06 */
256 U8 MsgFlags; /* 0x07 */
257 U8 VP_ID; /* 0x08 */
258 U8 VF_ID; /* 0x09 */
259 U16 Reserved1; /* 0x0A */
260 U16 IOCExceptions; /* 0x0C */
261 U16 IOCStatus; /* 0x0E */
262 U32 IOCLogInfo; /* 0x10 */
263 U8 MaxChainDepth; /* 0x14 */
264 U8 WhoInit; /* 0x15 */
265 U8 NumberOfPorts; /* 0x16 */
266 U8 MaxMSIxVectors; /* 0x17 */
267 U16 RequestCredit; /* 0x18 */
268 U16 ProductID; /* 0x1A */
269 U32 IOCCapabilities; /* 0x1C */
270 MPI2_VERSION_UNION FWVersion; /* 0x20 */
271 U16 IOCRequestFrameSize; /* 0x24 */
272 U16 Reserved3; /* 0x26 */
273 U16 MaxInitiators; /* 0x28 */
274 U16 MaxTargets; /* 0x2A */
275 U16 MaxSasExpanders; /* 0x2C */
276 U16 MaxEnclosures; /* 0x2E */
277 U16 ProtocolFlags; /* 0x30 */
278 U16 HighPriorityCredit; /* 0x32 */
279 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
280 U8 ReplyFrameSize; /* 0x36 */
281 U8 MaxVolumes; /* 0x37 */
282 U16 MaxDevHandle; /* 0x38 */
283 U16 MaxPersistentEntries; /* 0x3A */
284 U16 MinDevHandle; /* 0x3C */
285 U16 Reserved4; /* 0x3E */
290 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
292 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
293 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
296 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
298 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
299 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
302 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
304 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
305 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
306 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
307 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
308 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
310 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
311 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
312 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
313 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
314 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
321 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
322 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
323 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
324 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
325 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
326 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
327 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
328 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
329 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
330 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
331 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
332 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
333 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
336 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
337 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
346 U16 Reserved1; /* 0x00 */
347 U8 ChainOffset; /* 0x02 */
348 U8 Function; /* 0x03 */
349 U16 Reserved2; /* 0x04 */
350 U8 PortNumber; /* 0x06 */
351 U8 MsgFlags; /* 0x07 */
352 U8 VP_ID; /* 0x08 */
353 U8 VF_ID; /* 0x09 */
354 U16 Reserved3; /* 0x0A */
361 U16 Reserved1; /* 0x00 */
362 U8 MsgLength; /* 0x02 */
363 U8 Function; /* 0x03 */
364 U16 Reserved2; /* 0x04 */
365 U8 PortNumber; /* 0x06 */
366 U8 MsgFlags; /* 0x07 */
367 U8 VP_ID; /* 0x08 */
368 U8 VF_ID; /* 0x09 */
369 U16 Reserved3; /* 0x0A */
370 U16 Reserved4; /* 0x0C */
371 U16 IOCStatus; /* 0x0E */
372 U32 IOCLogInfo; /* 0x10 */
373 U8 Reserved5; /* 0x14 */
374 U8 PortType; /* 0x15 */
375 U16 Reserved6; /* 0x16 */
376 U16 MaxPostedCmdBuffers; /* 0x18 */
377 U16 Reserved7; /* 0x1A */
382 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
383 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
384 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
385 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
386 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
395 U16 Reserved1; /* 0x00 */
396 U8 ChainOffset; /* 0x02 */
397 U8 Function; /* 0x03 */
398 U8 Reserved2; /* 0x04 */
399 U8 PortFlags; /* 0x05 */
400 U8 Reserved3; /* 0x06 */
401 U8 MsgFlags; /* 0x07 */
402 U8 VP_ID; /* 0x08 */
403 U8 VF_ID; /* 0x09 */
404 U16 Reserved4; /* 0x0A */
411 U16 Reserved1; /* 0x00 */
412 U8 MsgLength; /* 0x02 */
413 U8 Function; /* 0x03 */
414 U8 Reserved2; /* 0x04 */
415 U8 PortFlags; /* 0x05 */
416 U8 Reserved3; /* 0x06 */
417 U8 MsgFlags; /* 0x07 */
418 U8 VP_ID; /* 0x08 */
419 U8 VF_ID; /* 0x09 */
420 U16 Reserved4; /* 0x0A */
421 U16 Reserved5; /* 0x0C */
422 U16 IOCStatus; /* 0x0E */
423 U32 IOCLogInfo; /* 0x10 */
436 U16 Reserved1; /* 0x00 */
437 U8 ChainOffset; /* 0x02 */
438 U8 Function; /* 0x03 */
439 U16 Reserved2; /* 0x04 */
440 U8 Reserved3; /* 0x06 */
441 U8 MsgFlags; /* 0x07 */
442 U8 VP_ID; /* 0x08 */
443 U8 VF_ID; /* 0x09 */
444 U16 Reserved4; /* 0x0A */
445 U32 Reserved5; /* 0x0C */
446 U32 Reserved6; /* 0x10 */
447 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
448 U16 SASBroadcastPrimitiveMasks; /* 0x24 */
449 U16 Reserved7; /* 0x26 */
450 U32 Reserved8; /* 0x28 */
458 U16 EventDataLength; /* 0x00 */
459 U8 MsgLength; /* 0x02 */
460 U8 Function; /* 0x03 */
461 U16 Reserved1; /* 0x04 */
462 U8 AckRequired; /* 0x06 */
463 U8 MsgFlags; /* 0x07 */
464 U8 VP_ID; /* 0x08 */
465 U8 VF_ID; /* 0x09 */
466 U16 Reserved2; /* 0x0A */
467 U16 Reserved3; /* 0x0C */
468 U16 IOCStatus; /* 0x0E */
469 U32 IOCLogInfo; /* 0x10 */
470 U16 Event; /* 0x14 */
471 U16 Reserved4; /* 0x16 */
472 U32 EventContext; /* 0x18 */
473 U32 EventData[1]; /* 0x1C */
478 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
479 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
482 #define MPI2_EVENT_LOG_DATA (0x0001)
483 #define MPI2_EVENT_STATE_CHANGE (0x0002)
484 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
485 #define MPI2_EVENT_EVENT_CHANGE (0x000A)
486 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */
487 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
488 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
489 #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
490 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
491 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
492 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
493 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
494 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
495 #define MPI2_EVENT_IR_VOLUME (0x001E)
496 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
497 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
498 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
499 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
500 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
501 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
502 #define MPI2_EVENT_SAS_QUIESCE (0x0025)
507 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
511 U64 TimeStamp; /* 0x00 */
512 U32 Reserved1; /* 0x08 */
513 U16 LogSequence; /* 0x0C */
514 U16 LogEntryQualifier; /* 0x0E */
515 U8 VP_ID; /* 0x10 */
516 U8 VF_ID; /* 0x11 */
517 U16 Reserved2; /* 0x12 */
518 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
527 U8 GPIONum; /* 0x00 */
528 U8 Reserved1; /* 0x01 */
529 U16 Reserved2; /* 0x02 */
538 U8 Reserved1; /* 0x00 */
539 U8 Port; /* 0x01 */
540 U16 Reserved2; /* 0x02 */
551 U16 DevHandle; /* 0x00 */
552 U16 CurrentDepth; /* 0x02 */
560 U16 TaskTag; /* 0x00 */
561 U8 ReasonCode; /* 0x02 */
562 U8 Reserved1; /* 0x03 */
563 U8 ASC; /* 0x04 */
564 U8 ASCQ; /* 0x05 */
565 U16 DevHandle; /* 0x06 */
566 U32 Reserved2; /* 0x08 */
567 U64 SASAddress; /* 0x0C */
568 U8 LUN[8]; /* 0x14 */
575 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
576 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
577 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
578 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
579 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
580 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
581 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
582 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
583 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
584 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
585 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
586 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
587 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
593 U16 VolDevHandle; /* 0x00 */
594 U16 Reserved1; /* 0x02 */
595 U8 RAIDOperation; /* 0x04 */
596 U8 PercentComplete; /* 0x05 */
597 U16 Reserved2; /* 0x06 */
598 U32 Resereved3; /* 0x08 */
605 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
606 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
607 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
608 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
609 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
615 U16 VolDevHandle; /* 0x00 */
616 U8 ReasonCode; /* 0x02 */
617 U8 Reserved1; /* 0x03 */
618 U32 NewValue; /* 0x04 */
619 U32 PreviousValue; /* 0x08 */
624 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
625 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
626 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
632 U16 Reserved1; /* 0x00 */
633 U8 ReasonCode; /* 0x02 */
634 U8 PhysDiskNum; /* 0x03 */
635 U16 PhysDiskDevHandle; /* 0x04 */
636 U16 Reserved2; /* 0x06 */
637 U16 Slot; /* 0x08 */
638 U16 EnclosureHandle; /* 0x0A */
639 U32 NewValue; /* 0x0C */
640 U32 PreviousValue; /* 0x10 */
646 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
647 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
648 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
662 U16 ElementFlags; /* 0x00 */
663 U16 VolDevHandle; /* 0x02 */
664 U8 ReasonCode; /* 0x04 */
665 U8 PhysDiskNum; /* 0x05 */
666 U16 PhysDiskDevHandle; /* 0x06 */
671 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
672 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
673 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
674 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
677 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
678 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
679 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
680 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
681 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
682 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
683 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
684 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
685 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
689 U8 NumElements; /* 0x00 */
690 U8 Reserved1; /* 0x01 */
691 U8 Reserved2; /* 0x02 */
692 U8 ConfigNum; /* 0x03 */
693 U32 Flags; /* 0x04 */
694 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */
701 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
707 U8 Flags; /* 0x00 */
708 U8 ReasonCode; /* 0x01 */
709 U8 PhysicalPort; /* 0x02 */
710 U8 Reserved1; /* 0x03 */
711 U32 DiscoveryStatus; /* 0x04 */
717 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
718 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
721 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
722 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
725 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
726 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
727 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
728 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
729 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
730 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
731 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
732 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
733 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
734 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
735 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
736 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
737 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
738 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
739 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
740 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
741 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
742 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
743 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
744 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
750 U8 PhyNum; /* 0x00 */
751 U8 Port; /* 0x01 */
752 U8 PortWidth; /* 0x02 */
753 U8 Primitive; /* 0x03 */
760 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
761 #define MPI2_EVENT_PRIMITIVE_SES (0x02)
762 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
763 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
764 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
765 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
766 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
767 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
773 U8 ReasonCode; /* 0x00 */
774 U8 PhysicalPort; /* 0x01 */
775 U16 DevHandle; /* 0x02 */
776 U64 SASAddress; /* 0x04 */
783 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
784 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
790 U16 MaxInit; /* 0x00 */
791 U16 CurrentInit; /* 0x02 */
792 U64 SASAddress; /* 0x04 */
810 U16 AttachedDevHandle; /* 0x00 */
811 U8 LinkRate; /* 0x02 */
812 U8 PhyStatus; /* 0x03 */
818 U16 EnclosureHandle; /* 0x00 */
819 U16 ExpanderDevHandle; /* 0x02 */
820 U8 NumPhys; /* 0x04 */
821 U8 Reserved1; /* 0x05 */
822 U16 Reserved2; /* 0x06 */
823 U8 NumEntries; /* 0x08 */
824 U8 StartPhyNum; /* 0x09 */
825 U8 ExpStatus; /* 0x0A */
826 U8 PhysicalPort; /* 0x0B */
827 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
834 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
835 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
836 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
837 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
838 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
841 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
843 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
844 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
846 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
847 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
848 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
849 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
850 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
851 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
852 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
853 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
854 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
855 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
858 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
859 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
861 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
862 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
863 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
864 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
865 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
866 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
872 U16 EnclosureHandle; /* 0x00 */
873 U8 ReasonCode; /* 0x02 */
874 U8 PhysicalPort; /* 0x03 */
875 U64 EnclosureLogicalID; /* 0x04 */
876 U16 NumSlots; /* 0x0C */
877 U16 StartSlot; /* 0x0E */
878 U32 PhyBits; /* 0x10 */
885 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
886 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
892 U64 TimeStamp; /* 0x00 */
893 U32 Reserved1; /* 0x08 */
894 U8 PhyEventCode; /* 0x0C */
895 U8 PhyNum; /* 0x0D */
896 U16 Reserved2; /* 0x0E */
897 U32 PhyEventInfo; /* 0x10 */
898 U8 CounterType; /* 0x14 */
899 U8 ThresholdWindow; /* 0x15 */
900 U8 TimeUnits; /* 0x16 */
901 U8 Reserved3; /* 0x17 */
902 U32 EventThreshold; /* 0x18 */
903 U16 ThresholdFlags; /* 0x1C */
904 U16 Reserved4; /* 0x1E */
921 U8 ReasonCode; /* 0x00 */
922 U8 Reserved1; /* 0x01 */
923 U16 Reserved2; /* 0x02 */
924 U32 Reserved3; /* 0x04 */
930 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
931 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
937 U8 Flags; /* 0x00 */
938 U8 NegotiatedLinkRate; /* 0x01 */
939 U8 PhyNum; /* 0x02 */
940 U8 PhysicalPort; /* 0x03 */
941 U32 Reserved1; /* 0x04 */
942 U8 InitialFrame[28]; /* 0x08 */
947 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
948 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
960 U8 DescriptorType; /* 0x00 */
961 U8 Reserved1; /* 0x01 */
962 U16 Reserved2; /* 0x02 */
963 U32 Reserved3; /* 0x04 */
964 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */
969 #define MPI2_EVENT_HBD_DT_SAS (0x01)
978 U16 Reserved1; /* 0x00 */
979 U8 ChainOffset; /* 0x02 */
980 U8 Function; /* 0x03 */
981 U16 Reserved2; /* 0x04 */
982 U8 Reserved3; /* 0x06 */
983 U8 MsgFlags; /* 0x07 */
984 U8 VP_ID; /* 0x08 */
985 U8 VF_ID; /* 0x09 */
986 U16 Reserved4; /* 0x0A */
987 U16 Event; /* 0x0C */
988 U16 Reserved5; /* 0x0E */
989 U32 EventContext; /* 0x10 */
996 U16 Reserved1; /* 0x00 */
997 U8 MsgLength; /* 0x02 */
998 U8 Function; /* 0x03 */
999 U16 Reserved2; /* 0x04 */
1000 U8 Reserved3; /* 0x06 */
1001 U8 MsgFlags; /* 0x07 */
1002 U8 VP_ID; /* 0x08 */
1003 U8 VF_ID; /* 0x09 */
1004 U16 Reserved4; /* 0x0A */
1005 U16 Reserved5; /* 0x0C */
1006 U16 IOCStatus; /* 0x0E */
1007 U32 IOCLogInfo; /* 0x10 */
1018 U8 ImageType; /* 0x00 */
1019 U8 Reserved1; /* 0x01 */
1020 U8 ChainOffset; /* 0x02 */
1021 U8 Function; /* 0x03 */
1022 U16 Reserved2; /* 0x04 */
1023 U8 Reserved3; /* 0x06 */
1024 U8 MsgFlags; /* 0x07 */
1025 U8 VP_ID; /* 0x08 */
1026 U8 VF_ID; /* 0x09 */
1027 U16 Reserved4; /* 0x0A */
1028 U32 TotalImageSize; /* 0x0C */
1029 U32 Reserved5; /* 0x10 */
1030 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1034 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1036 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1037 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1038 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1039 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1040 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1041 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1042 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1043 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1044 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1049 U8 Reserved1; /* 0x00 */
1050 U8 ContextSize; /* 0x01 */
1051 U8 DetailsLength; /* 0x02 */
1052 U8 Flags; /* 0x03 */
1053 U32 Reserved2; /* 0x04 */
1054 U32 ImageOffset; /* 0x08 */
1055 U32 ImageSize; /* 0x0C */
1062 U8 ImageType; /* 0x00 */
1063 U8 Reserved1; /* 0x01 */
1064 U8 MsgLength; /* 0x02 */
1065 U8 Function; /* 0x03 */
1066 U16 Reserved2; /* 0x04 */
1067 U8 Reserved3; /* 0x06 */
1068 U8 MsgFlags; /* 0x07 */
1069 U8 VP_ID; /* 0x08 */
1070 U8 VF_ID; /* 0x09 */
1071 U16 Reserved4; /* 0x0A */
1072 U16 Reserved5; /* 0x0C */
1073 U16 IOCStatus; /* 0x0E */
1074 U32 IOCLogInfo; /* 0x10 */
1085 U8 ImageType; /* 0x00 */
1086 U8 Reserved1; /* 0x01 */
1087 U8 ChainOffset; /* 0x02 */
1088 U8 Function; /* 0x03 */
1089 U16 Reserved2; /* 0x04 */
1090 U8 Reserved3; /* 0x06 */
1091 U8 MsgFlags; /* 0x07 */
1092 U8 VP_ID; /* 0x08 */
1093 U8 VF_ID; /* 0x09 */
1094 U16 Reserved4; /* 0x0A */
1095 U32 Reserved5; /* 0x0C */
1096 U32 Reserved6; /* 0x10 */
1097 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1101 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1102 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1103 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1104 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1105 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1106 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1107 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1108 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1109 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1110 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1114 U8 Reserved1; /* 0x00 */
1115 U8 ContextSize; /* 0x01 */
1116 U8 DetailsLength; /* 0x02 */
1117 U8 Flags; /* 0x03 */
1118 U32 Reserved2; /* 0x04 */
1119 U32 ImageOffset; /* 0x08 */
1120 U32 ImageSize; /* 0x0C */
1127 U8 ImageType; /* 0x00 */
1128 U8 Reserved1; /* 0x01 */
1129 U8 MsgLength; /* 0x02 */
1130 U8 Function; /* 0x03 */
1131 U16 Reserved2; /* 0x04 */
1132 U8 Reserved3; /* 0x06 */
1133 U8 MsgFlags; /* 0x07 */
1134 U8 VP_ID; /* 0x08 */
1135 U8 VF_ID; /* 0x09 */
1136 U16 Reserved4; /* 0x0A */
1137 U16 Reserved5; /* 0x0C */
1138 U16 IOCStatus; /* 0x0E */
1139 U32 IOCLogInfo; /* 0x10 */
1140 U32 ActualImageSize; /* 0x14 */
1147 U32 Signature; /* 0x00 */
1148 U32 Signature0; /* 0x04 */
1149 U32 Signature1; /* 0x08 */
1150 U32 Signature2; /* 0x0C */
1151 MPI2_VERSION_UNION MPIVersion; /* 0x10 */
1152 MPI2_VERSION_UNION FWVersion; /* 0x14 */
1153 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */
1154 MPI2_VERSION_UNION PackageVersion; /* 0x1C */
1155 U16 VendorID; /* 0x20 */
1156 U16 ProductID; /* 0x22 */
1157 U16 ProtocolFlags; /* 0x24 */
1158 U16 Reserved26; /* 0x26 */
1159 U32 IOCCapabilities; /* 0x28 */
1160 U32 ImageSize; /* 0x2C */
1161 U32 NextImageHeaderOffset; /* 0x30 */
1162 U32 Checksum; /* 0x34 */
1163 U32 Reserved38; /* 0x38 */
1164 U32 Reserved3C; /* 0x3C */
1165 U32 Reserved40; /* 0x40 */
1166 U32 Reserved44; /* 0x44 */
1167 U32 Reserved48; /* 0x48 */
1168 U32 Reserved4C; /* 0x4C */
1169 U32 Reserved50; /* 0x50 */
1170 U32 Reserved54; /* 0x54 */
1171 U32 Reserved58; /* 0x58 */
1172 U32 Reserved5C; /* 0x5C */
1173 U32 Reserved60; /* 0x60 */
1174 U32 FirmwareVersionNameWhat; /* 0x64 */
1175 U8 FirmwareVersionName[32]; /* 0x68 */
1176 U32 VendorNameWhat; /* 0x88 */
1177 U8 VendorName[32]; /* 0x8C */
1178 U32 PackageNameWhat; /* 0x88 */
1179 U8 PackageName[32]; /* 0x8C */
1180 U32 ReservedD0; /* 0xD0 */
1181 U32 ReservedD4; /* 0xD4 */
1182 U32 ReservedD8; /* 0xD8 */
1183 U32 ReservedDC; /* 0xDC */
1184 U32 ReservedE0; /* 0xE0 */
1185 U32 ReservedE4; /* 0xE4 */
1186 U32 ReservedE8; /* 0xE8 */
1187 U32 ReservedEC; /* 0xEC */
1188 U32 ReservedF0; /* 0xF0 */
1189 U32 ReservedF4; /* 0xF4 */
1190 U32 ReservedF8; /* 0xF8 */
1191 U32 ReservedFC; /* 0xFC */
1196 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1197 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1198 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1201 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1202 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1205 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1206 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1209 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1210 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1213 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1214 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1216 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1217 #define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1218 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1219 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1221 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1223 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1224 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1230 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1231 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1232 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1234 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1236 #define MPI2_FW_HEADER_SIZE (0x100)
1242 U8 ImageType; /* 0x00 */
1243 U8 Reserved1; /* 0x01 */
1244 U16 Reserved2; /* 0x02 */
1245 U32 Checksum; /* 0x04 */
1246 U32 ImageSize; /* 0x08 */
1247 U32 NextImageHeaderOffset; /* 0x0C */
1248 U32 PackageVersion; /* 0x10 */
1249 U32 Reserved3; /* 0x14 */
1250 U32 Reserved4; /* 0x18 */
1251 U32 Reserved5; /* 0x1C */
1252 U8 IdentifyString[32]; /* 0x20 */
1257 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1258 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1259 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1261 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1264 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1265 #define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1266 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1267 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1268 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1269 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1270 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1271 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1295 U8 RegionType; /* 0x00 */
1296 U8 Reserved1; /* 0x01 */
1297 U16 Reserved2; /* 0x02 */
1298 U32 RegionOffset; /* 0x04 */
1299 U32 RegionSize; /* 0x08 */
1300 U32 Reserved3; /* 0x0C */
1306 U32 FlashSize; /* 0x00 */
1307 U32 Reserved1; /* 0x04 */
1308 U32 Reserved2; /* 0x08 */
1309 U32 Reserved3; /* 0x0C */
1310 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1316 U8 ImageRevision; /* 0x00 */
1317 U8 Reserved1; /* 0x01 */
1318 U8 SizeOfRegion; /* 0x02 */
1319 U8 Reserved2; /* 0x03 */
1320 U16 NumberOfLayouts; /* 0x04 */
1321 U16 RegionsPerLayout; /* 0x06 */
1322 U16 MinimumSectorAlignment; /* 0x08 */
1323 U16 Reserved3; /* 0x0A */
1324 U32 Reserved4; /* 0x0C */
1325 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1330 #define MPI2_FLASH_REGION_UNUSED (0x00)
1331 #define MPI2_FLASH_REGION_FIRMWARE (0x01)
1332 #define MPI2_FLASH_REGION_BIOS (0x02)
1333 #define MPI2_FLASH_REGION_NVDATA (0x03)
1334 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1335 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1336 #define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1337 #define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1338 #define MPI2_FLASH_REGION_MEGARAID (0x09)
1339 #define MPI2_FLASH_REGION_INIT (0x0A)
1342 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1356 U16 DeviceID; /* 0x00 */
1357 U16 VendorID; /* 0x02 */
1358 U16 DeviceIDMask; /* 0x04 */
1359 U16 Reserved1; /* 0x06 */
1360 U8 LowPCIRev; /* 0x08 */
1361 U8 HighPCIRev; /* 0x09 */
1362 U16 Reserved2; /* 0x0A */
1363 U32 Reserved3; /* 0x0C */
1369 U8 ImageRevision; /* 0x00 */
1370 U8 Reserved1; /* 0x01 */
1371 U8 NumberOfDevices; /* 0x02 */
1372 U8 Reserved2; /* 0x03 */
1373 U32 Reserved3; /* 0x04 */
1374 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1379 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1386 U32 BootFlags; /* 0x00 */
1387 U32 ImageSize; /* 0x04 */
1388 U32 Signature0; /* 0x08 */
1389 U32 Signature1; /* 0x0C */
1390 U32 Signature2; /* 0x10 */
1391 U32 ResetVector; /* 0x14 */
1396 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1399 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1402 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1403 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1406 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1407 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1410 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1411 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1414 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1415 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1416 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1417 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1419 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1420 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1421 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1422 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1424 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1425 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1426 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1427 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1430 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1439 U8 Feature; /* 0x00 */
1440 U8 Reserved1; /* 0x01 */
1441 U8 ChainOffset; /* 0x02 */
1442 U8 Function; /* 0x03 */
1443 U16 Reserved2; /* 0x04 */
1444 U8 Reserved3; /* 0x06 */
1445 U8 MsgFlags; /* 0x07 */
1446 U8 VP_ID; /* 0x08 */
1447 U8 VF_ID; /* 0x09 */
1448 U16 Reserved4; /* 0x0A */
1449 U8 Parameter1; /* 0x0C */
1450 U8 Parameter2; /* 0x0D */
1451 U8 Parameter3; /* 0x0E */
1452 U8 Parameter4; /* 0x0F */
1453 U32 Reserved5; /* 0x10 */
1454 U32 Reserved6; /* 0x14 */
1459 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1460 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1461 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03)
1462 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1463 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1464 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1469 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1470 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1471 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1477 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1478 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1479 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1481 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1482 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1483 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1484 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1489 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00)
1490 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01)
1491 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02)
1493 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01)
1494 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02)
1495 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04)
1496 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08)
1501 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
1502 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
1503 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
1504 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
1510 U8 Feature; /* 0x00 */
1511 U8 Reserved1; /* 0x01 */
1512 U8 MsgLength; /* 0x02 */
1513 U8 Function; /* 0x03 */
1514 U16 Reserved2; /* 0x04 */
1515 U8 Reserved3; /* 0x06 */
1516 U8 MsgFlags; /* 0x07 */
1517 U8 VP_ID; /* 0x08 */
1518 U8 VF_ID; /* 0x09 */
1519 U16 Reserved4; /* 0x0A */
1520 U16 Reserved5; /* 0x0C */
1521 U16 IOCStatus; /* 0x0E */
1522 U32 IOCLogInfo; /* 0x10 */