Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x0fffffff
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2006-2015 LSI Corp.
5 * Copyright (c) 2013-2015 Avago Technologies
29 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
33 * Copyright (c) 2006-2015 LSI Corporation.
34 * Copyright (c) 2013-2015 Avago Technologies
46 * ---------------
49 * -------- -------- ------------------------------------------------------
50 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
51 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
52 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
53 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
54 * Moved ReplyPostHostIndex register to offset 0x6C of the
59 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
63 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
64 * Removed the MPI-defined Fault Codes and extended the
65 * product specific codes up to 0xEFFF.
67 * and changed the flush value to 0x0.
72 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
73 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
74 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
76 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
77 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
80 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
87 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
88 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
89 * Added MSI-x index mask and shift for Reply Post Host
92 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
94 * Added defines for product-specific range of message
95 * function codes, 0xF0 to 0xFF.
96 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
98 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
99 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
101 * --------------------------------------------------------------------------
113 #define MPI2_VERSION_MAJOR (0x02)
114 #define MPI2_VERSION_MINOR (0x00)
115 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
117 #define MPI2_VERSION_MINOR_MASK (0x00FF)
118 #define MPI2_VERSION_MINOR_SHIFT (0)
122 #define MPI2_VERSION_02_00 (0x0200)
125 #define MPI2_HEADER_VERSION_UNIT (0x12)
126 #define MPI2_HEADER_VERSION_DEV (0x00)
127 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
129 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
130 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
139 #define MPI2_IOC_STATE_RESET (0x00000000)
140 #define MPI2_IOC_STATE_READY (0x10000000)
141 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
142 #define MPI2_IOC_STATE_FAULT (0x40000000)
144 #define MPI2_IOC_STATE_MASK (0xF0000000)
148 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
149 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
159 U32 Doorbell; /* 0x00 */
160 U32 WriteSequence; /* 0x04 */
161 U32 HostDiagnostic; /* 0x08 */
162 U32 Reserved1; /* 0x0C */
163 U32 DiagRWData; /* 0x10 */
164 U32 DiagRWAddressLow; /* 0x14 */
165 U32 DiagRWAddressHigh; /* 0x18 */
166 U32 Reserved2[5]; /* 0x1C */
167 U32 HostInterruptStatus; /* 0x30 */
168 U32 HostInterruptMask; /* 0x34 */
169 U32 DCRData; /* 0x38 */
170 U32 DCRAddress; /* 0x3C */
171 U32 Reserved3[2]; /* 0x40 */
172 U32 ReplyFreeHostIndex; /* 0x48 */
173 U32 Reserved4[8]; /* 0x4C */
174 U32 ReplyPostHostIndex; /* 0x6C */
175 U32 Reserved5; /* 0x70 */
176 U32 HCBSize; /* 0x74 */
177 U32 HCBAddressLow; /* 0x78 */
178 U32 HCBAddressHigh; /* 0x7C */
179 U32 Reserved6[16]; /* 0x80 */
180 U32 RequestDescriptorPostLow; /* 0xC0 */
181 U32 RequestDescriptorPostHigh; /* 0xC4 */
182 U32 Reserved7[14]; /* 0xC8 */
189 #define MPI2_DOORBELL_OFFSET (0x00000000)
191 /* IOC --> System values */
192 #define MPI2_DOORBELL_USED (0x08000000)
193 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
195 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
196 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
198 /* System --> IOC values */
199 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
201 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
207 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
208 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
209 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
210 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
211 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
212 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
213 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
214 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
215 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
220 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
222 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
223 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
224 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
226 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
227 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
228 #define MPI2_DIAG_HCB_MODE (0x00000100)
229 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
230 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
231 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
232 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
233 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
234 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
239 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
240 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
241 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
246 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
247 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
249 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
250 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
251 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
257 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
258 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
259 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
261 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
267 #define MPI2_DCR_DATA_OFFSET (0x00000038)
268 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
273 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
278 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
279 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
280 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
286 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
287 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
288 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
290 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
291 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
296 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
297 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
310 U8 RequestFlags; /* 0x00 */
311 U8 MSIxIndex; /* 0x01 */
312 U16 SMID; /* 0x02 */
313 U16 LMID; /* 0x04 */
314 U16 DescriptorTypeDependent; /* 0x06 */
320 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
321 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
322 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
323 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
324 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
325 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
327 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
332 U8 RequestFlags; /* 0x00 */
333 U8 MSIxIndex; /* 0x01 */
334 U16 SMID; /* 0x02 */
335 U16 LMID; /* 0x04 */
336 U16 Reserved1; /* 0x06 */
345 U8 RequestFlags; /* 0x00 */
346 U8 MSIxIndex; /* 0x01 */
347 U16 SMID; /* 0x02 */
348 U16 LMID; /* 0x04 */
349 U16 DevHandle; /* 0x06 */
357 U8 RequestFlags; /* 0x00 */
358 U8 MSIxIndex; /* 0x01 */
359 U16 SMID; /* 0x02 */
360 U16 LMID; /* 0x04 */
361 U16 IoIndex; /* 0x06 */
370 U8 RequestFlags; /* 0x00 */
371 U8 MSIxIndex; /* 0x01 */
372 U16 SMID; /* 0x02 */
373 U16 LMID; /* 0x04 */
374 U16 Reserved; /* 0x06 */
397 U8 ReplyFlags; /* 0x00 */
398 U8 MSIxIndex; /* 0x01 */
399 U16 DescriptorTypeDependent1; /* 0x02 */
400 U32 DescriptorTypeDependent2; /* 0x04 */
405 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
406 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
407 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
408 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
409 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
410 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
411 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
414 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
415 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
420 U8 ReplyFlags; /* 0x00 */
421 U8 MSIxIndex; /* 0x01 */
422 U16 SMID; /* 0x02 */
423 U32 ReplyFrameAddress; /* 0x04 */
427 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
432 U8 ReplyFlags; /* 0x00 */
433 U8 MSIxIndex; /* 0x01 */
434 U16 SMID; /* 0x02 */
435 U16 TaskTag; /* 0x04 */
436 U16 Reserved1; /* 0x06 */
445 U8 ReplyFlags; /* 0x00 */
446 U8 MSIxIndex; /* 0x01 */
447 U16 SMID; /* 0x02 */
448 U8 SequenceNumber; /* 0x04 */
449 U8 Reserved1; /* 0x05 */
450 U16 IoIndex; /* 0x06 */
459 U8 ReplyFlags; /* 0x00 */
460 U8 MSIxIndex; /* 0x01 */
461 U8 VP_ID; /* 0x02 */
462 U8 Flags; /* 0x03 */
463 U16 InitiatorDevHandle; /* 0x04 */
464 U16 IoIndex; /* 0x06 */
471 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
476 U8 ReplyFlags; /* 0x00 */
477 U8 MSIxIndex; /* 0x01 */
478 U16 SMID; /* 0x02 */
479 U32 Reserved; /* 0x04 */
504 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
505 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
506 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
507 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
508 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
509 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
510 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
511 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
512 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
513 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
514 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
515 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
516 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
517 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
518 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
519 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
520 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
521 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
522 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
523 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
524 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
525 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
526 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
527 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
528 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
529 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */
530 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */
531 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */
532 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */
533 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */
536 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
537 #define MPI2_FUNCTION_HANDSHAKE (0x42)
546 #define MPI2_IOCSTATUS_MASK (0x7FFF)
552 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
553 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
554 #define MPI2_IOCSTATUS_BUSY (0x0002)
555 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
556 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
557 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
558 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
559 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
560 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
561 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
567 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
568 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
569 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
570 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
571 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
572 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
578 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
579 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
580 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
581 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
582 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
583 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
584 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
585 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
586 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
587 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
588 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
589 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
592 * For use by SCSI Initiator and SCSI Target end-to-end data protection
595 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
596 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
597 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
603 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
604 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
605 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
606 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
607 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
608 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
609 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
610 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
611 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
612 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
618 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
619 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
625 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
631 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
637 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
643 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
645 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
646 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
647 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
648 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
649 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
650 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
664 U16 FunctionDependent1; /* 0x00 */
665 U8 ChainOffset; /* 0x02 */
666 U8 Function; /* 0x03 */
667 U16 FunctionDependent2; /* 0x04 */
668 U8 FunctionDependent3; /* 0x06 */
669 U8 MsgFlags; /* 0x07 */
670 U8 VP_ID; /* 0x08 */
671 U8 VF_ID; /* 0x09 */
672 U16 Reserved1; /* 0x0A */
682 U16 FunctionDependent1; /* 0x00 */
683 U8 MsgLength; /* 0x02 */
684 U8 Function; /* 0x03 */
685 U16 FunctionDependent2; /* 0x04 */
686 U8 FunctionDependent3; /* 0x06 */
687 U8 MsgFlags; /* 0x07 */
688 U8 VP_ID; /* 0x08 */
689 U8 VF_ID; /* 0x09 */
690 U16 Reserved1; /* 0x0A */
691 U16 FunctionDependent5; /* 0x0C */
692 U16 IOCStatus; /* 0x0E */
693 U32 IOCLogInfo; /* 0x10 */
701 U8 Dev; /* 0x00 */
702 U8 Unit; /* 0x01 */
703 U8 Minor; /* 0x02 */
704 U8 Major; /* 0x03 */
714 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
715 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
716 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
717 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
718 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
719 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
723 * Fusion-MPT MPI Scatter Gather Elements
905 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
906 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
907 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
908 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
909 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
910 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
911 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
915 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
916 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
920 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
921 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
922 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
923 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
927 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
931 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
932 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
939 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
940 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
944 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
945 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
946 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
947 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
949 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
964 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
965 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
966 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
968 /* CAUTION - The following are READ-MODIFY-WRITE! */
969 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
970 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
976 * Fusion-MPT IEEE Scatter Gather Elements
1043 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1047 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1051 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1052 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1056 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1057 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* IEEE Simple Element only */
1058 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* IEEE Simple Element only */
1059 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1060 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* IEEE Simple Element only */
1061 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (0x03) /* IEEE Chain Element only */
1074 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1075 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1076 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_…
1078 /* CAUTION - The following are READ-MODIFY-WRITE! */
1079 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1080 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1084 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1111 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1112 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1113 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1114 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1115 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1117 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1118 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1119 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1120 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)