Lines Matching +full:0 +full:x0c
43 * with MPI v2.0 products. Unless otherwise noted, names beginning with
44 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
62 * Persistent Mapping Page 0.
64 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
65 * RAID Physical Disk Pages 0 and 1, RAID Configuration
66 * Page 0).
68 * Page 0 (_SATA_NEEDS_INITIALIZATION).
71 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
81 * Page 0.
87 * Added SAS Port Page 0.
92 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
93 * to 0x000000FF.
101 * Added additional defines for RAID Volume Page 0
103 * Modified meaning of RAID Volume Page 0 VolumeSettings
108 * RAID Physical Disk Page 0.
111 * Page 0 and SAS Expander Page 0.
115 * Expander Page 0 Flags field.
116 * Added two new AccessStatus values to SAS Device Page 0
122 * Added more pending task bits to RAID Volume Page 0
125 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
126 * and SAS Expander Page 0 to flag a downstream initiator
129 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
132 * SAS Device Page 0.
136 * Expander Page 0.
142 * to SAS Device Page 0 Flags field.
230 * Device Page 0.
238 * PCIe device page 0.
242 * to match SAS DevicePage 0.
253 * Added ChassisSlot field to SAS Enclosure Page 0.
255 * in SAS Enclosure Page 0.
290 U8 PageVersion; /* 0x00 */
291 U8 PageLength; /* 0x01 */
292 U8 PageNumber; /* 0x02 */
293 U8 PageType; /* 0x03 */
309 U8 PageVersion; /* 0x00 */
310 U8 Reserved1; /* 0x01 */
311 U8 PageNumber; /* 0x02 */
312 U8 PageType; /* 0x03 */
313 U16 ExtPageLength; /* 0x04 */
314 U8 ExtPageType; /* 0x06 */
315 U8 Reserved2; /* 0x07 */
331 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
332 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
333 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
334 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
336 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
337 #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
338 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
339 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
340 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
341 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
342 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
343 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
345 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
348 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
349 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
350 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
351 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
352 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
353 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
354 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
355 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
356 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
357 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
358 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
359 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B) /* MPI v2.6 and later */
360 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C) /* MPI v2.6 and later */
361 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D) /* MPI v2.6 and later */
362 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E) /* MPI v2.6 and later */
363 /* Product specific reserved values 0xE0 - 0xEF */
364 /* Vendor specific reserved values 0xF0 - 0xFF */
371 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
372 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
373 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
375 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
378 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
379 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
380 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
381 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
383 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
384 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
387 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
388 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
389 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
390 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
392 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
393 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
397 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
398 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
399 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
401 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
404 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
405 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
406 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
408 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
409 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
412 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
413 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
414 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
416 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
419 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
420 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
421 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
423 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
426 #define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000)
427 #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
428 #define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
430 #define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
433 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
434 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
435 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
436 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
438 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
441 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
442 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
444 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
446 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
449 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
450 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
452 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
455 #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000)
456 #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
457 #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000)
458 #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000)
460 #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF)
461 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000)
465 #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000)
466 #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
467 #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000)
469 #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
472 #define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000)
473 #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000)
474 #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000)
476 #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF)
485 U8 Action; /* 0x00 */
486 U8 SGLFlags; /* 0x01 */
487 U8 ChainOffset; /* 0x02 */
488 U8 Function; /* 0x03 */
489 U16 ExtPageLength; /* 0x04 */
490 U8 ExtPageType; /* 0x06 */
491 U8 MsgFlags; /* 0x07 */
492 U8 VP_ID; /* 0x08 */
493 U8 VF_ID; /* 0x09 */
494 U16 Reserved1; /* 0x0A */
495 U8 Reserved2; /* 0x0C */
496 U8 ProxyVF_ID; /* 0x0D */
497 U16 Reserved4; /* 0x0E */
498 U32 Reserved3; /* 0x10 */
499 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
500 U32 PageAddress; /* 0x18 */
501 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
506 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
507 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
508 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
509 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
510 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
511 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
512 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
513 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
520 U8 Action; /* 0x00 */
521 U8 SGLFlags; /* 0x01 */
522 U8 MsgLength; /* 0x02 */
523 U8 Function; /* 0x03 */
524 U16 ExtPageLength; /* 0x04 */
525 U8 ExtPageType; /* 0x06 */
526 U8 MsgFlags; /* 0x07 */
527 U8 VP_ID; /* 0x08 */
528 U8 VF_ID; /* 0x09 */
529 U16 Reserved1; /* 0x0A */
530 U16 Reserved2; /* 0x0C */
531 U16 IOCStatus; /* 0x0E */
532 U32 IOCLogInfo; /* 0x10 */
533 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
547 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
549 /* MPI v2.0 SAS products */
550 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
551 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
552 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
553 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
554 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
555 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
556 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
558 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
560 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
561 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
562 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
563 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
564 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
565 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
566 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
567 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
568 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
571 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096)
572 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097)
573 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090)
574 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091)
575 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094)
576 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095)
579 #define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9)
580 #define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4)
581 #define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5)
582 #define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6)
583 #define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7)
584 #define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8)
585 #define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0)
586 #define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1)
587 #define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2)
588 #define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3)
590 #define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA)
591 #define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB)
592 #define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC)
593 #define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD)
594 #define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE)
595 #define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF)
597 #define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0)
598 #define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1)
599 #define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2)
601 #define MPI26_MFGPAGE_DEVID_SEC_MASK_SAS3916 (0x0003)
602 #define MPI26_MFGPAGE_DEVID_INVALID0_SAS3916 (0x00E0)
603 #define MPI26_MFGPAGE_DEVID_CFG_SEC_SAS3916 (0x00E1)
604 #define MPI26_MFGPAGE_DEVID_HARD_SEC_SAS3916 (0x00E2)
605 #define MPI26_MFGPAGE_DEVID_INVALID1_SAS3916 (0x00E3)
607 #define MPI26_MFGPAGE_DEVID_SEC_MASK_SAS3816 (0x0003)
608 #define MPI26_MFGPAGE_DEVID_INVALID0_SAS3816 (0x00E4)
609 #define MPI26_MFGPAGE_DEVID_CFG_SEC_SAS3816 (0x00E5)
610 #define MPI26_MFGPAGE_DEVID_HARD_SEC_SAS3816 (0x00E6)
611 #define MPI26_MFGPAGE_DEVID_INVALID1_SAS3816 (0x00E7)
613 /* Manufacturing Page 0 */
617 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
618 U8 ChipName[16]; /* 0x04 */
619 U8 ChipRevision[8]; /* 0x14 */
620 U8 BoardName[16]; /* 0x1C */
621 U8 BoardAssembly[16]; /* 0x2C */
622 U8 BoardTracerNumber[16]; /* 0x3C */
627 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
633 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
634 U8 VPD[256]; /* 0x04 */
639 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
643 U16 DeviceID; /* 0x00 */
644 U8 PCIRevisionID; /* 0x02 */
645 U8 Reserved; /* 0x03 */
661 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
662 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
663 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
668 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
682 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
683 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
684 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
689 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
695 U8 PowerSaveFlags; /* 0x00 */
696 U8 InternalOperationsSleepTime; /* 0x01 */
697 U8 InternalOperationsRunTime; /* 0x02 */
698 U8 HostIdleTime; /* 0x03 */
704 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
705 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
706 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
707 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
711 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
712 U32 Reserved1; /* 0x04 */
713 U32 Flags; /* 0x08 */
714 U8 InquirySize; /* 0x0C */
715 U8 Reserved2; /* 0x0D */
716 U16 Reserved3; /* 0x0E */
717 U8 InquiryData[56]; /* 0x10 */
718 U32 RAID0VolumeSettings; /* 0x48 */
719 U32 RAID1EVolumeSettings; /* 0x4C */
720 U32 RAID1VolumeSettings; /* 0x50 */
721 U32 RAID10VolumeSettings; /* 0x54 */
722 U32 Reserved4; /* 0x58 */
723 U32 Reserved5; /* 0x5C */
724 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
725 U8 MaxOCEDisks; /* 0x64 */
726 U8 ResyncRate; /* 0x65 */
727 U16 DataScrubDuration; /* 0x66 */
728 U8 MaxHotSpares; /* 0x68 */
729 U8 MaxPhysDisksPerVol; /* 0x69 */
730 U8 MaxPhysDisks; /* 0x6A */
731 U8 MaxVolumes; /* 0x6B */
736 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
739 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
740 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
742 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
743 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
744 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
746 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
747 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
748 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
749 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
750 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
752 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
753 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
754 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
755 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
757 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
758 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
759 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
760 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
761 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
762 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
763 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
764 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
778 U64 WWID; /* 0x00 */
779 U64 DeviceName; /* 0x08 */
785 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
786 U8 NumPhys; /* 0x04 */
787 U8 Reserved1; /* 0x05 */
788 U16 Reserved2; /* 0x06 */
789 U32 Reserved3; /* 0x08 */
790 U32 Reserved4; /* 0x0C */
791 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
796 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
802 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
803 U32 ProductSpecificInfo;/* 0x04 */
808 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
814 U32 Pinout; /* 0x00 */
815 U8 Connector[16]; /* 0x04 */
816 U8 Location; /* 0x14 */
817 U8 ReceptacleID; /* 0x15 */
818 U16 Slot; /* 0x16 */
819 U16 Slotx4; /* 0x18 */
820 U16 Slotx2; /* 0x1A */
825 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
828 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
829 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
830 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
831 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
832 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
833 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
834 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
835 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
836 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
837 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
838 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
839 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
840 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
841 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
842 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
843 #define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E)
844 #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F)
845 #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10)
846 #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11)
847 #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12)
848 #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13)
851 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
852 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
853 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
854 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
855 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
856 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
857 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
860 #define MPI2_MANPAGE7_SLOT_UNKNOWN (0xFFFF)
872 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
873 U32 Reserved1; /* 0x04 */
874 U32 Reserved2; /* 0x08 */
875 U32 Flags; /* 0x0C */
876 U8 EnclosureName[16]; /* 0x10 */
877 U8 NumPhys; /* 0x20 */
878 U8 Reserved3; /* 0x21 */
879 U16 Reserved4; /* 0x22 */
880 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
885 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
888 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008)
889 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002)
890 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
899 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
900 U32 ProductSpecificInfo;/* 0x04 */
905 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
906 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
907 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
908 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
909 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
910 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
911 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
912 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
913 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
914 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
915 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
916 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
917 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
918 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
919 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
920 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
921 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
922 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
923 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
924 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
925 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
926 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
927 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
928 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
934 /* IO Unit Page 0 */
938 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
939 U64 UniqueValue; /* 0x04 */
940 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
941 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
945 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
951 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
952 U32 Flags; /* 0x04 */
956 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
959 #define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_MASK (0x00030000)
960 #define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_ENABLE (0x00000000)
961 #define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_DISABLE (0x00010000)
962 #define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_NO_CHANGE (0x00020000)
963 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000)
964 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000)
965 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000)
966 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
967 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
969 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
970 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
971 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
972 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
973 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
974 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
975 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
989 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
990 U8 GPIOCount; /* 0x04 */
991 U8 Reserved1; /* 0x05 */
992 U16 Reserved2; /* 0x06 */
993 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
997 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
1000 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
1002 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
1003 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
1017 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1018 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
1019 U64 RaidAcceleratorBufferSize; /* 0x0C */
1020 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
1021 U8 RAControlSize; /* 0x1C */
1022 U8 NumDmaEngines; /* 0x1D */
1023 U8 RAMinControlSize; /* 0x1E */
1024 U8 RAMaxControlSize; /* 0x1F */
1025 U32 Reserved1; /* 0x20 */
1026 U32 Reserved2; /* 0x24 */
1027 U32 Reserved3; /* 0x28 */
1028 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
1032 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
1035 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000)
1038 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
1039 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
1040 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
1041 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
1047 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1048 U16 Flags; /* 0x04 */
1049 U8 RAHostControlSize; /* 0x06 */
1050 U8 Reserved0; /* 0x07 */
1051 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
1052 U32 Reserved1; /* 0x10 */
1053 U32 Reserved2; /* 0x14 */
1054 U32 Reserved3; /* 0x18 */
1058 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
1061 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
1067 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1068 …U8 CurrentPowerMode; /* 0x04 */ /* reserved in MPI 2.0 …
1069 …U8 PreviousPowerMode; /* 0x05 */ /* reserved in MPI 2.0 …
1070 U8 PCIeWidth; /* 0x06 */
1071 U8 PCIeSpeed; /* 0x07 */
1072 U32 ProcessorState; /* 0x08 */
1073 U32 PowerManagementCapabilities; /* 0x0C */
1074 U16 IOCTemperature; /* 0x10 */
1075 U8 IOCTemperatureUnits; /* 0x12 */
1076 U8 IOCSpeed; /* 0x13 */
1077 U16 BoardTemperature; /* 0x14 */
1078 U8 BoardTemperatureUnits; /* 0x16 */
1079 U8 Reserved3; /* 0x17 */
1080 …U32 BoardPowerRequirement; /* 0x18 */ /* reserved…
1081 …U32 PCISlotPowerAllocation; /* 0x1C */ /* reserve…
1082 …U8 Flags; /* 0x20 */ /* reserved prior to MPI v2…
1083 U8 Reserved6; /* 0x21 */
1084 U16 Reserved7; /* 0x22 */
1085 U32 Reserved8; /* 0x24 */
1089 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x05)
1092 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0)
1093 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00)
1094 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40)
1095 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80)
1096 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0)
1098 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07)
1099 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00)
1100 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01)
1101 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04)
1102 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05)
1103 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06)
1106 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
1107 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
1108 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
1109 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
1110 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10)
1113 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
1114 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
1115 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
1116 #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03)
1119 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
1120 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
1122 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
1123 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
1124 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
1127 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000)
1128 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000)
1129 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000)
1130 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000)
1131 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000)
1132 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000)
1133 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000)
1134 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000)
1135 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000)
1136 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400)
1137 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200)
1138 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100)
1139 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040)
1140 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020)
1141 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010)
1142 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) /* obsolete */
1143 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) /* obsolete */
1144 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) /* obsolete */
1145 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) /* obsolete */
1148 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
1149 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
1150 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
1151 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /* obsolete */
1152 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /* obsolete */
1155 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
1156 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
1157 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
1160 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
1161 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
1162 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
1163 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
1166 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
1167 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
1168 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
1171 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01)
1179 U16 Flags; /* 0x00 */
1180 U16 Reserved1; /* 0x02 */
1181 U16 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */
1182 U32 Reserved2; /* 0x0C */
1183 U32 Reserved3; /* 0x10 */
1184 U32 Reserved4; /* 0x14 */
1189 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
1190 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
1191 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
1192 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
1204 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1205 U32 Reserved1; /* 0x04 */
1206 U32 Reserved2; /* 0x08 */
1207 U8 NumSensors; /* 0x0C */
1208 U8 PollingInterval; /* 0x0D */
1209 U16 Reserved3; /* 0x0E */
1210 MPI2_IOUNIT8_SENSOR Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */
1214 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
1220 U16 CurrentTemperature; /* 0x00 */
1221 U16 Reserved1; /* 0x02 */
1222 U8 Flags; /* 0x04 */
1223 U8 Reserved2; /* 0x05 */
1224 U16 Reserved3; /* 0x06 */
1225 U32 Reserved4; /* 0x08 */
1226 U32 Reserved5; /* 0x0C */
1231 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
1243 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1244 U32 Reserved1; /* 0x04 */
1245 U32 Reserved2; /* 0x08 */
1246 U8 NumSensors; /* 0x0C */
1247 U8 Reserved4; /* 0x0D */
1248 U16 Reserved3; /* 0x0E */
1249 MPI2_IOUNIT9_SENSOR Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */
1253 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
1259 U8 CreditPercent; /* 0x00 */
1260 U8 Reserved1; /* 0x01 */
1261 U16 Reserved2; /* 0x02 */
1275 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1276 U8 NumFunctions; /* 0x04 */
1277 U8 Reserved1; /* 0x05 */
1278 U16 Reserved2; /* 0x06 */
1279 U32 Reserved3; /* 0x08 */
1280 U32 Reserved4; /* 0x0C */
1281 MPI2_IOUNIT10_FUNCTION Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES]; /* 0x10 */
1285 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
1291 U8 MaxTargetSpinup; /* 0x00 */
1292 U8 SpinupDelay; /* 0x01 */
1293 U8 SpinupFlags; /* 0x02 */
1294 U8 Reserved1; /* 0x03 */
1299 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01)
1311 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1312 U32 Reserved1; /* 0x04 */
1313 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
1314 U32 Reserved2; /* 0x18 */
1315 U32 Reserved3; /* 0x1C */
1316 U32 Reserved4; /* 0x20 */
1317 U8 BootDeviceWaitTime; /* 0x24 */
1318 U8 SATADeviceWaitTime; /* 0x25 */
1319 U16 Reserved6; /* 0x26 */
1320 U8 NumPhys; /* 0x28 */
1321 U8 PEInitialSpinupDelay; /* 0x29 */
1322 U8 PEReplyDelay; /* 0x2A */
1323 U8 Flags; /* 0x2B */
1324 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/* 0x2C */
1329 #define MPI26_IOUNITPAGE11_PAGEVERSION (0x00)
1332 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01)
1335 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03)
1341 /* IOC Page 0 */
1345 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1346 U32 Reserved1; /* 0x04 */
1347 U32 Reserved2; /* 0x08 */
1348 U16 VendorID; /* 0x0C */
1349 U16 DeviceID; /* 0x0E */
1350 U8 RevisionID; /* 0x10 */
1351 U8 Reserved3; /* 0x11 */
1352 U16 Reserved4; /* 0x12 */
1353 U32 ClassCode; /* 0x14 */
1354 U16 SubsystemVendorID; /* 0x18 */
1355 U16 SubsystemID; /* 0x1A */
1359 #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
1365 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1366 U32 Flags; /* 0x04 */
1367 U32 CoalescingTimeout; /* 0x08 */
1368 U8 CoalescingDepth; /* 0x0C */
1369 U8 PCISlotNum; /* 0x0D */
1370 U8 PCIBusNum; /* 0x0E */
1371 U8 PCIDomainSegment; /* 0x0F */
1372 U32 Reserved1; /* 0x10 */
1373 U32 ProductSpecific; /* 0x14 */
1377 #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1380 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1382 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1383 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1384 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1390 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1391 U32 CapabilitiesFlags; /* 0x04 */
1392 U8 MaxDrivesRAID0; /* 0x08 */
1393 U8 MaxDrivesRAID1; /* 0x09 */
1394 U8 MaxDrivesRAID1E; /* 0x0A */
1395 U8 MaxDrivesRAID10; /* 0x0B */
1396 U8 MinDrivesRAID0; /* 0x0C */
1397 U8 MinDrivesRAID1; /* 0x0D */
1398 U8 MinDrivesRAID1E; /* 0x0E */
1399 U8 MinDrivesRAID10; /* 0x0F */
1400 U32 Reserved1; /* 0x10 */
1401 U8 MaxGlobalHotSpares; /* 0x14 */
1402 U8 MaxPhysDisks; /* 0x15 */
1403 U8 MaxVolumes; /* 0x16 */
1404 U8 MaxConfigs; /* 0x17 */
1405 U8 MaxOCEDisks; /* 0x18 */
1406 U8 Reserved2; /* 0x19 */
1407 U16 Reserved3; /* 0x1A */
1408 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
1409 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
1410 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
1411 U32 Reserved4; /* 0x28 */
1412 U32 Reserved5; /* 0x2C */
1413 U16 DefaultMetadataSize; /* 0x30 */
1414 U16 Reserved6; /* 0x32 */
1415 U16 MaxBadBlockTableEntries; /* 0x34 */
1416 U16 Reserved7; /* 0x36 */
1417 U32 IRNvsramVersion; /* 0x38 */
1421 #define MPI2_IOCPAGE6_PAGEVERSION (0x05)
1424 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020)
1425 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1426 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1427 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1428 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1429 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1437 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1438 U32 Reserved1; /* 0x04 */
1439 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1440 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
1441 U16 SASNotifyPrimitiveMasks; /* 0x1A */
1442 U32 Reserved3; /* 0x1C */
1446 #define MPI2_IOCPAGE7_PAGEVERSION (0x02)
1452 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1453 U8 NumDevsPerEnclosure; /* 0x04 */
1454 U8 Reserved1; /* 0x05 */
1455 U16 Reserved2; /* 0x06 */
1456 U16 MaxPersistentEntries; /* 0x08 */
1457 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
1458 U16 Flags; /* 0x0C */
1459 U16 Reserved3; /* 0x0E */
1460 U16 IRVolumeMappingFlags; /* 0x10 */
1461 U16 Reserved4; /* 0x12 */
1462 U32 Reserved5; /* 0x14 */
1466 #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1469 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1470 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1472 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1473 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1474 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1476 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1477 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1480 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1481 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1482 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1492 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1493 U32 BiosOptions; /* 0x04 */
1494 U32 IOCSettings; /* 0x08 */
1495 U8 SSUTimeout; /* 0x0C */
1496 U8 MaxEnclosureLevel; /* 0x0D */
1497 U16 Reserved2; /* 0x0E */
1498 U32 DeviceSettings; /* 0x10 */
1499 U16 NumberOfDevices; /* 0x14 */
1500 U16 UEFIVersion; /* 0x16 */
1501 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
1502 U16 IOTimeoutSequential; /* 0x1A */
1503 U16 IOTimeoutOther; /* 0x1C */
1504 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
1508 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07)
1511 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000)
1512 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000)
1514 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800)
1515 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000)
1516 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800)
1517 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000)
1518 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800)
1519 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000)
1521 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400)
1523 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300)
1524 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000)
1525 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100)
1526 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200)
1527 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300)
1529 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0)
1530 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000)
1532 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006)
1533 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000)
1534 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002)
1535 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004)
1537 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1540 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1541 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1542 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1544 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1545 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1546 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1547 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1549 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1550 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1551 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1552 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1553 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1555 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1558 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1559 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1560 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1561 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1562 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1565 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00)
1567 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF)
1568 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0)
1574 U32 Reserved1; /* 0x00 */
1575 U32 Reserved2; /* 0x04 */
1576 U32 Reserved3; /* 0x08 */
1577 U32 Reserved4; /* 0x0C */
1578 U32 Reserved5; /* 0x10 */
1579 U32 Reserved6; /* 0x14 */
1586 U64 SASAddress; /* 0x00 */
1587 U8 LUN[8]; /* 0x08 */
1588 U32 Reserved1; /* 0x10 */
1589 U32 Reserved2; /* 0x14 */
1595 U64 EnclosureLogicalID; /* 0x00 */
1596 U32 Reserved1; /* 0x08 */
1597 U32 Reserved2; /* 0x0C */
1598 U16 SlotNumber; /* 0x10 */
1599 U16 Reserved3; /* 0x12 */
1600 U32 Reserved4; /* 0x14 */
1607 U64 DeviceName; /* 0x00 */
1608 U8 LUN[8]; /* 0x08 */
1609 U32 Reserved1; /* 0x10 */
1610 U32 Reserved2; /* 0x14 */
1625 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1626 U32 Reserved1; /* 0x04 */
1627 U32 Reserved2; /* 0x08 */
1628 U32 Reserved3; /* 0x0C */
1629 U32 Reserved4; /* 0x10 */
1630 U32 Reserved5; /* 0x14 */
1631 U32 Reserved6; /* 0x18 */
1632 U8 ReqBootDeviceForm; /* 0x1C */
1633 U8 Reserved7; /* 0x1D */
1634 U16 Reserved8; /* 0x1E */
1635 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1636 U8 ReqAltBootDeviceForm; /* 0x38 */
1637 U8 Reserved9; /* 0x39 */
1638 U16 Reserved10; /* 0x3A */
1639 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1640 U8 CurrentBootDeviceForm; /* 0x58 */
1641 U8 Reserved11; /* 0x59 */
1642 U16 Reserved12; /* 0x5A */
1643 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1647 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1650 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1651 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1652 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1653 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1654 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1662 U8 PciBusNumber; /* 0x00 */
1663 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1664 U16 AdapterFlags; /* 0x02 */
1668 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1669 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1673 U64 WWID; /* 0x00 */
1674 U32 Reserved1; /* 0x08 */
1675 U32 Reserved2; /* 0x0C */
1681 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1682 U32 GlobalFlags; /* 0x04 */
1683 U32 BiosVersion; /* 0x08 */
1684 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x0C */
1685 U32 Reserved1; /* 0x1C */
1686 …MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x20 */ /* MPI v2.5 and ne…
1690 #define MPI2_BIOSPAGE3_PAGEVERSION (0x01)
1693 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1694 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1695 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1697 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1698 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1699 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1700 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1714 U64 ReassignmentWWID; /* 0x00 */
1715 U64 ReassignmentDeviceName; /* 0x08 */
1721 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1722 U8 NumPhys; /* 0x04 */
1723 U8 Reserved1; /* 0x05 */
1724 U16 Reserved2; /* 0x06 */
1725 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1729 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1735 /* RAID Volume Page 0 */
1739 U8 RAIDSetNum; /* 0x00 */
1740 U8 PhysDiskMap; /* 0x01 */
1741 U8 PhysDiskNum; /* 0x02 */
1742 U8 Reserved; /* 0x03 */
1747 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1748 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1752 U16 Settings; /* 0x00 */
1753 U8 HotSparePool; /* 0x01 */
1754 U8 Reserved; /* 0x02 */
1758 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1759 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1760 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1761 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1762 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1763 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1764 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1765 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1766 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1768 /* RAID Volume Page 0 VolumeSettings defines */
1769 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1770 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1772 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1773 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1774 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1775 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1787 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1788 U16 DevHandle; /* 0x04 */
1789 U8 VolumeState; /* 0x06 */
1790 U8 VolumeType; /* 0x07 */
1791 U32 VolumeStatusFlags; /* 0x08 */
1792 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1793 U64 MaxLBA; /* 0x10 */
1794 U32 StripeSize; /* 0x18 */
1795 U16 BlockSize; /* 0x1C */
1796 U16 Reserved1; /* 0x1E */
1797 U8 SupportedPhysDisks; /* 0x20 */
1798 U8 ResyncRate; /* 0x21 */
1799 U16 DataScrubDuration; /* 0x22 */
1800 U8 NumPhysDisks; /* 0x24 */
1801 U8 Reserved2; /* 0x25 */
1802 U8 Reserved3; /* 0x26 */
1803 U8 InactiveStatus; /* 0x27 */
1804 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1808 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1811 #define MPI2_RAID_VOL_STATE_MISSING (0x00)
1812 #define MPI2_RAID_VOL_STATE_FAILED (0x01)
1813 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1814 #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1815 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1816 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1819 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1820 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1821 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1822 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1823 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1825 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1826 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1827 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1828 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1829 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1830 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1831 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1832 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1833 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1834 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1835 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1836 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1837 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1838 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1839 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1840 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1841 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1842 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1843 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1844 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1846 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1847 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1848 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1849 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1850 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1852 /* values for RAID Volume Page 0 InactiveStatus field */
1853 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1854 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1855 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1856 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1857 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1858 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1859 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1865 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1866 U16 DevHandle; /* 0x04 */
1867 U16 Reserved0; /* 0x06 */
1868 U8 GUID[24]; /* 0x08 */
1869 U8 Name[16]; /* 0x20 */
1870 U64 WWID; /* 0x30 */
1871 U32 Reserved1; /* 0x38 */
1872 U32 Reserved2; /* 0x3C */
1876 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1882 /* RAID Physical Disk Page 0 */
1886 U16 Reserved1; /* 0x00 */
1887 U8 HotSparePool; /* 0x02 */
1888 U8 Reserved2; /* 0x03 */
1896 U8 VendorID[8]; /* 0x00 */
1897 U8 ProductID[16]; /* 0x08 */
1898 U8 ProductRevLevel[4]; /* 0x18 */
1899 U8 SerialNum[32]; /* 0x1C */
1906 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1907 U16 DevHandle; /* 0x04 */
1908 U8 Reserved1; /* 0x06 */
1909 U8 PhysDiskNum; /* 0x07 */
1910 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1911 U32 Reserved2; /* 0x0C */
1912 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1913 U32 Reserved3; /* 0x4C */
1914 U8 PhysDiskState; /* 0x50 */
1915 U8 OfflineReason; /* 0x51 */
1916 U8 IncompatibleReason; /* 0x52 */
1917 U8 PhysDiskAttributes; /* 0x53 */
1918 U32 PhysDiskStatusFlags; /* 0x54 */
1919 U64 DeviceMaxLBA; /* 0x58 */
1920 U64 HostMaxLBA; /* 0x60 */
1921 U64 CoercedMaxLBA; /* 0x68 */
1922 U16 BlockSize; /* 0x70 */
1923 U16 Reserved5; /* 0x72 */
1924 U32 Reserved6; /* 0x74 */
1929 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1932 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1933 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1934 #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1935 #define MPI2_RAID_PD_STATE_ONLINE (0x03)
1936 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1937 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1938 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1939 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1942 #define MPI2_PHYSDISK0_ONLINE (0x00)
1943 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1944 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1945 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1946 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1947 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1948 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1951 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1952 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1953 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1954 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1955 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1956 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1957 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1958 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1961 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
1962 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1963 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1965 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1966 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1967 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1970 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1971 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1972 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1973 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1974 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1975 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1976 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1977 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1991 U16 DevHandle; /* 0x00 */
1992 U16 Reserved1; /* 0x02 */
1993 U64 WWID; /* 0x04 */
1994 U64 OwnerWWID; /* 0x0C */
1995 U8 OwnerIdentifier; /* 0x14 */
1996 U8 Reserved2; /* 0x15 */
1997 U16 Flags; /* 0x16 */
2002 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
2003 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
2004 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
2008 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
2009 U8 NumPhysDiskPaths; /* 0x04 */
2010 U8 PhysDiskNum; /* 0x05 */
2011 U16 Reserved1; /* 0x06 */
2012 U32 Reserved2; /* 0x08 */
2013 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
2018 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
2025 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
2027 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
2029 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
2030 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
2031 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
2032 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
2033 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
2034 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
2035 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
2036 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
2037 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
2038 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
2039 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B)
2040 #define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C)
2043 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
2044 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
2045 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
2047 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
2048 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
2049 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
2050 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
2051 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
2052 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
2053 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
2054 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
2055 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
2056 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
2059 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
2061 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
2063 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
2064 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
2065 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
2067 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
2068 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
2069 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
2070 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
2071 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
2072 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
2074 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
2075 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
2076 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
2077 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
2078 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
2079 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
2080 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
2081 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
2082 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
2083 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
2085 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
2086 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
2087 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
2088 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
2090 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
2093 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
2094 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
2095 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
2096 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
2099 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
2100 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
2101 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
2102 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
2103 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
2104 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0)
2105 #define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0)
2106 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
2107 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
2108 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
2109 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
2110 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
2111 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B)
2112 #define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C)
2115 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
2116 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
2117 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
2118 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
2119 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0)
2120 #define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0)
2121 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
2122 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
2123 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
2124 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
2125 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B)
2126 #define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C)
2132 /* SAS IO Unit Page 0 */
2136 U8 Port; /* 0x00 */
2137 U8 PortFlags; /* 0x01 */
2138 U8 PhyFlags; /* 0x02 */
2139 U8 NegotiatedLinkRate; /* 0x03 */
2140 U32 ControllerPhyDeviceInfo;/* 0x04 */
2141 U16 AttachedDevHandle; /* 0x08 */
2142 U16 ControllerDevHandle; /* 0x0A */
2143 U32 DiscoveryStatus; /* 0x0C */
2144 U32 Reserved; /* 0x10 */
2158 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2159 U32 Reserved1; /* 0x08 */
2160 U8 NumPhys; /* 0x0C */
2161 U8 Reserved2; /* 0x0D */
2162 U16 Reserved3; /* 0x0E */
2163 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
2168 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
2170 /* values for SAS IO Unit Page 0 PortFlags */
2171 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
2172 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
2174 /* values for SAS IO Unit Page 0 PhyFlags */
2175 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40)
2176 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20)
2177 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
2178 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
2182 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2184 /* values for SAS IO Unit Page 0 DiscoveryStatus */
2185 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2186 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2187 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
2188 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2189 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2190 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2191 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2192 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
2193 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2194 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
2195 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
2196 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2197 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2198 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2199 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2200 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2201 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2202 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2203 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2204 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
2210 U8 Port; /* 0x00 */
2211 U8 PortFlags; /* 0x01 */
2212 U8 PhyFlags; /* 0x02 */
2213 U8 MaxMinLinkRate; /* 0x03 */
2214 U32 ControllerPhyDeviceInfo; /* 0x04 */
2215 U16 MaxTargetPortConnectTime; /* 0x08 */
2216 U16 Reserved1; /* 0x0A */
2230 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2231 U16 ControlFlags; /* 0x08 */
2232 U16 SASNarrowMaxQueueDepth; /* 0x0A */
2233 U16 AdditionalControlFlags; /* 0x0C */
2234 U16 SASWideMaxQueueDepth; /* 0x0E */
2235 U8 NumPhys; /* 0x10 */
2236 U8 SATAMaxQDepth; /* 0x11 */
2237 U8 ReportDeviceMissingDelay; /* 0x12 */
2238 U8 IODeviceMissingDelay; /* 0x13 */
2239 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
2244 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
2247 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2248 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2249 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) /* MPI v2.0 only. Obso…
2250 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2252 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2254 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
2255 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
2256 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
2258 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2259 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2260 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2261 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2262 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
2263 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2264 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2265 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) /* MPI v2.0 only. Obso…
2268 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100)
2269 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
2270 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
2271 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
2272 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
2273 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
2274 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
2275 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
2276 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
2279 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
2280 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
2283 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2286 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40)
2287 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20)
2288 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
2289 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
2292 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
2293 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
2294 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
2295 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
2296 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0)
2297 #define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0)
2298 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
2299 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
2300 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
2301 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
2302 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B)
2303 #define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C)
2311 U8 MaxTargetSpinup; /* 0x00 */
2312 U8 SpinupDelay; /* 0x01 */
2313 U8 SpinupFlags; /* 0x02 */
2314 U8 Reserved1; /* 0x03 */
2319 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01)
2331 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2332 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
2333 U32 Reserved1; /* 0x18 */
2334 U32 Reserved2; /* 0x1C */
2335 U32 Reserved3; /* 0x20 */
2336 U8 BootDeviceWaitTime; /* 0x24 */
2337 U8 SATADeviceWaitTime; /* 0x25 */
2338 U16 Reserved5; /* 0x26 */
2339 U8 NumPhys; /* 0x28 */
2340 U8 PEInitialSpinupDelay; /* 0x29 */
2341 U8 PEReplyDelay; /* 0x2A */
2342 U8 Flags; /* 0x2B */
2343 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
2348 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
2351 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
2354 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
2360 U8 ControlFlags; /* 0x00 */
2361 U8 PortWidthModGroup; /* 0x01 */
2362 U16 InactivityTimerExponent; /* 0x02 */
2363 U8 SATAPartialTimeout; /* 0x04 */
2364 U8 Reserved2; /* 0x05 */
2365 U8 SATASlumberTimeout; /* 0x06 */
2366 U8 Reserved3; /* 0x07 */
2367 U8 SASPartialTimeout; /* 0x08 */
2368 U8 Reserved4; /* 0x09 */
2369 U8 SASSlumberTimeout; /* 0x0A */
2370 U8 Reserved5; /* 0x0B */
2376 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
2377 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
2378 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
2379 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
2382 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
2385 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
2387 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
2389 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
2391 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
2392 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
2401 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
2413 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2414 U8 NumPhys; /* 0x08 */
2415 U8 Reserved1; /* 0x09 */
2416 U16 Reserved2; /* 0x0A */
2417 U32 Reserved3; /* 0x0C */
2418 …SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
2423 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2429 U8 CurrentStatus; /* 0x00 */
2430 U8 CurrentModulation; /* 0x01 */
2431 U8 CurrentUtilization; /* 0x02 */
2432 U8 Reserved1; /* 0x03 */
2433 U32 Reserved2; /* 0x04 */
2440 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2441 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2442 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2443 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2444 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2445 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2446 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2447 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2450 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2451 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2452 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2453 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2465 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2466 U32 Reserved1; /* 0x08 */
2467 U32 Reserved2; /* 0x0C */
2468 U8 NumGroups; /* 0x10 */
2469 U8 Reserved3; /* 0x11 */
2470 U16 Reserved4; /* 0x12 */
2472 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2477 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2483 U8 Flags; /* 0x00 */
2484 U8 Reserved1; /* 0x01 */
2485 U16 Reserved2; /* 0x02 */
2486 U8 Threshold75Pct; /* 0x04 */
2487 U8 Threshold50Pct; /* 0x05 */
2488 U8 Threshold25Pct; /* 0x06 */
2489 U8 Reserved3; /* 0x07 */
2496 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2508 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2509 U8 SamplingInterval; /* 0x08 */
2510 U8 WindowLength; /* 0x09 */
2511 U16 Reserved1; /* 0x0A */
2512 U32 Reserved2; /* 0x0C */
2513 U32 Reserved3; /* 0x10 */
2514 U8 NumGroups; /* 0x14 */
2515 U8 Reserved4; /* 0x15 */
2516 U16 Reserved5; /* 0x16 */
2518 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2523 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2529 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2530 U32 Reserved1; /* 0x08 */
2531 U32 PowerManagementCapabilities; /* 0x0C */
2532 …U8 TxRxSleepStatus; /* 0x10 */ /* reserved in MPI …
2533 U8 Reserved2; /* 0x11 */
2534 U16 Reserved3; /* 0x12 */
2539 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2542 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
2543 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
2544 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
2545 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
2546 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
2547 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
2548 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
2549 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
2550 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
2551 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
2554 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00)
2555 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01)
2556 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02)
2557 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03)
2563 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2564 U64 TimeStamp; /* 0x08 */
2565 U32 Reserved1; /* 0x10 */
2566 U32 Reserved2; /* 0x14 */
2567 U32 FastPathPendedRequests; /* 0x18 */
2568 U32 FastPathUnPendedRequests; /* 0x1C */
2569 U32 FastPathHostRequestStarts; /* 0x20 */
2570 U32 FastPathFirmwareRequestStarts; /* 0x24 */
2571 U32 FastPathHostCompletions; /* 0x28 */
2572 U32 FastPathFirmwareCompletions; /* 0x2C */
2573 U32 NonFastPathRequestStarts; /* 0x30 */
2574 U32 NonFastPathHostCompletions; /* 0x30 */
2579 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00)
2585 /* SAS Expander Page 0 */
2589 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2590 U8 PhysicalPort; /* 0x08 */
2591 U8 ReportGenLength; /* 0x09 */
2592 U16 EnclosureHandle; /* 0x0A */
2593 U64 SASAddress; /* 0x0C */
2594 U32 DiscoveryStatus; /* 0x14 */
2595 U16 DevHandle; /* 0x18 */
2596 U16 ParentDevHandle; /* 0x1A */
2597 U16 ExpanderChangeCount; /* 0x1C */
2598 U16 ExpanderRouteIndexes; /* 0x1E */
2599 U8 NumPhys; /* 0x20 */
2600 U8 SASLevel; /* 0x21 */
2601 U16 Flags; /* 0x22 */
2602 U16 STPBusInactivityTimeLimit; /* 0x24 */
2603 U16 STPMaxConnectTimeLimit; /* 0x26 */
2604 U16 STP_SMP_NexusLossTime; /* 0x28 */
2605 U16 MaxNumRoutedSasAddresses; /* 0x2A */
2606 U64 ActiveZoneManagerSASAddress;/* 0x2C */
2607 U16 ZoneLockInactivityLimit; /* 0x34 */
2608 U16 Reserved1; /* 0x36 */
2609 U8 TimeToReducedFunc; /* 0x38 */
2610 U8 InitialTimeToReducedFunc; /* 0x39 */
2611 U8 MaxReducedFuncTime; /* 0x3A */
2612 U8 Reserved2; /* 0x3B */
2616 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2618 /* values for SAS Expander Page 0 DiscoveryStatus field */
2619 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2620 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2621 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2622 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2623 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2624 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2625 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2626 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2627 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2628 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2629 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2630 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2631 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2632 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2633 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2634 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2635 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2636 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2637 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2638 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2640 /* values for SAS Expander Page 0 Flags field */
2641 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2642 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2643 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2644 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2645 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2646 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2647 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2648 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2649 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2650 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2651 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2657 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2658 U8 PhysicalPort; /* 0x08 */
2659 U8 Reserved1; /* 0x09 */
2660 U16 Reserved2; /* 0x0A */
2661 U8 NumPhys; /* 0x0C */
2662 U8 Phy; /* 0x0D */
2663 U16 NumTableEntriesProgrammed; /* 0x0E */
2664 U8 ProgrammedLinkRate; /* 0x10 */
2665 U8 HwLinkRate; /* 0x11 */
2666 U16 AttachedDevHandle; /* 0x12 */
2667 U32 PhyInfo; /* 0x14 */
2668 U32 AttachedDeviceInfo; /* 0x18 */
2669 U16 ExpanderDevHandle; /* 0x1C */
2670 U8 ChangeCount; /* 0x1E */
2671 U8 NegotiatedLinkRate; /* 0x1F */
2672 U8 PhyIdentifier; /* 0x20 */
2673 U8 AttachedPhyIdentifier; /* 0x21 */
2674 U8 Reserved3; /* 0x22 */
2675 U8 DiscoveryInfo; /* 0x23 */
2676 U32 AttachedPhyInfo; /* 0x24 */
2677 U8 ZoneGroup; /* 0x28 */
2678 U8 SelfConfigStatus; /* 0x29 */
2679 U16 Reserved4; /* 0x2A */
2683 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2696 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2697 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2698 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2706 /* SAS Device Page 0 */
2710 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2711 U16 Slot; /* 0x08 */
2712 U16 EnclosureHandle; /* 0x0A */
2713 U64 SASAddress; /* 0x0C */
2714 U16 ParentDevHandle; /* 0x14 */
2715 U8 PhyNum; /* 0x16 */
2716 U8 AccessStatus; /* 0x17 */
2717 U16 DevHandle; /* 0x18 */
2718 U8 AttachedPhyIdentifier; /* 0x1A */
2719 U8 ZoneGroup; /* 0x1B */
2720 U32 DeviceInfo; /* 0x1C */
2721 U16 Flags; /* 0x20 */
2722 U8 PhysicalPort; /* 0x22 */
2723 U8 MaxPortConnections; /* 0x23 */
2724 U64 DeviceName; /* 0x24 */
2725 U8 PortGroups; /* 0x2C */
2726 U8 DmaGroup; /* 0x2D */
2727 U8 ControlGroup; /* 0x2E */
2728 U8 EnclosureLevel; /* 0x2F */
2729 U8 ConnectorName[4]; /* 0x30 */
2730 U32 Reserved3; /* 0x34 */
2734 #define MPI2_SASDEVICE0_PAGEVERSION (0x09)
2736 /* values for SAS Device Page 0 AccessStatus field */
2737 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2738 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2739 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2740 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2741 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2742 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2743 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2744 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2746 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2747 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2748 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2749 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2750 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2751 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2752 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2753 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2754 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2755 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2756 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2758 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2760 /* values for SAS Device Page 0 Flags field */
2761 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
2762 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000)
2763 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000)
2764 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2765 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2766 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2767 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2768 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2769 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2770 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2771 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2772 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2773 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2774 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004)
2775 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002)
2776 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2782 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2783 U32 Reserved1; /* 0x08 */
2784 U64 SASAddress; /* 0x0C */
2785 U32 Reserved2; /* 0x14 */
2786 U16 DevHandle; /* 0x18 */
2787 U16 Reserved3; /* 0x1A */
2788 U8 InitialRegDeviceFIS[20];/* 0x1C */
2792 #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2798 /* SAS PHY Page 0 */
2802 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2803 U16 OwnerDevHandle; /* 0x08 */
2804 U16 Reserved1; /* 0x0A */
2805 U16 AttachedDevHandle; /* 0x0C */
2806 U8 AttachedPhyIdentifier; /* 0x0E */
2807 U8 Reserved2; /* 0x0F */
2808 U32 AttachedPhyInfo; /* 0x10 */
2809 U8 ProgrammedLinkRate; /* 0x14 */
2810 U8 HwLinkRate; /* 0x15 */
2811 U8 ChangeCount; /* 0x16 */
2812 U8 Flags; /* 0x17 */
2813 U32 PhyInfo; /* 0x18 */
2814 U8 NegotiatedLinkRate; /* 0x1C */
2815 U8 Reserved3; /* 0x1D */
2816 U16 Reserved4; /* 0x1E */
2820 #define MPI2_SASPHY0_PAGEVERSION (0x03)
2828 /* values for SAS PHY Page 0 Flags field */
2829 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2839 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2840 U32 Reserved1; /* 0x08 */
2841 U32 InvalidDwordCount; /* 0x0C */
2842 U32 RunningDisparityErrorCount; /* 0x10 */
2843 U32 LossDwordSynchCount; /* 0x14 */
2844 U32 PhyResetProblemCount; /* 0x18 */
2848 #define MPI2_SASPHY1_PAGEVERSION (0x01)
2854 U8 PhyEventCode; /* 0x00 */
2855 U8 Reserved1; /* 0x01 */
2856 U16 Reserved2; /* 0x02 */
2857 U32 PhyEventInfo; /* 0x04 */
2873 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2874 U32 Reserved1; /* 0x08 */
2875 U8 NumPhyEvents; /* 0x0C */
2876 U8 Reserved2; /* 0x0D */
2877 U16 Reserved3; /* 0x0E */
2878 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */
2882 #define MPI2_SASPHY2_PAGEVERSION (0x00)
2888 U8 PhyEventCode; /* 0x00 */
2889 U8 Reserved1; /* 0x01 */
2890 U16 Reserved2; /* 0x02 */
2891 U8 CounterType; /* 0x04 */
2892 U8 ThresholdWindow; /* 0x05 */
2893 U8 TimeUnits; /* 0x06 */
2894 U8 Reserved3; /* 0x07 */
2895 U32 EventThreshold; /* 0x08 */
2896 U16 ThresholdFlags; /* 0x0C */
2897 U16 Reserved4; /* 0x0E */
2902 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2903 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2904 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2905 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2906 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2907 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2908 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2909 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2910 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2911 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2912 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2913 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2914 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2915 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2916 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2917 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2918 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2919 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2920 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2921 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2922 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2923 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2924 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2925 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2926 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2927 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2928 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2929 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2930 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2931 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2932 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2933 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2934 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2935 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2936 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2937 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2938 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2940 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3)
2941 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4)
2942 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5)
2943 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6)
2944 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7)
2945 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8)
2946 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9)
2947 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA)
2948 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB)
2949 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC)
2952 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2953 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2954 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2957 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2958 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2959 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2960 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2963 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2964 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2976 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2977 U32 Reserved1; /* 0x08 */
2978 U8 NumPhyEvents; /* 0x0C */
2979 U8 Reserved2; /* 0x0D */
2980 U16 Reserved3; /* 0x0E */
2981 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2985 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2991 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2992 U16 Reserved1; /* 0x08 */
2993 U8 Reserved2; /* 0x0A */
2994 U8 Flags; /* 0x0B */
2995 U8 InitialFrame[28]; /* 0x0C */
2999 #define MPI2_SASPHY4_PAGEVERSION (0x00)
3002 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
3003 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
3009 /* SAS Port Page 0 */
3013 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3014 U8 PortNumber; /* 0x08 */
3015 U8 PhysicalPort; /* 0x09 */
3016 U8 PortWidth; /* 0x0A */
3017 U8 PhysicalPortWidth; /* 0x0B */
3018 U8 ZoneGroup; /* 0x0C */
3019 U8 Reserved1; /* 0x0D */
3020 U16 Reserved2; /* 0x0E */
3021 U64 SASAddress; /* 0x10 */
3022 U32 DeviceInfo; /* 0x18 */
3023 U32 Reserved3; /* 0x1C */
3024 U32 Reserved4; /* 0x20 */
3028 #define MPI2_SASPORT0_PAGEVERSION (0x00)
3030 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
3036 /* SAS Enclosure Page 0, Enclosure Page 0 */
3040 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3041 U32 Reserved1; /* 0x08 */
3042 U64 EnclosureLogicalID; /* 0x0C */
3043 U16 Flags; /* 0x14 */
3044 U16 EnclosureHandle; /* 0x16 */
3045 U16 NumSlots; /* 0x18 */
3046 U16 StartSlot; /* 0x1A */
3047 U8 ChassisSlot; /* 0x1C */
3048 U8 EnclosureLevel; /* 0x1D */
3049 U16 SEPDevHandle; /* 0x1E */
3050 U8 OEMRD; /* 0x20 */
3051 U8 Reserved1a; /* 0x21 */
3052 U16 Reserved2; /* 0x22 */
3053 U32 Reserved3; /* 0x24 */
3061 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04)
3063 /* values for SAS Enclosure Page 0 Flags field */
3064 #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_VALID (0x0080)
3065 #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040)
3066 #define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020)
3067 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
3068 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
3069 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
3070 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
3071 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
3072 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
3073 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
3074 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
3076 #define MPI26_ENCLOSURE0_PAGEVERSION (0x04)
3078 /* Values for Enclosure Page 0 Flags field */
3079 #define MPI26_ENCLS0_FLAGS_OEMRD_VALID (0x0080)
3080 #define MPI26_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040)
3081 #define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020)
3082 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
3083 #define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F)
3084 #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
3085 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
3086 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
3087 #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
3088 #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
3089 #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
3095 /* Log Page 0 */
3105 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
3109 U64 TimeStamp; /* 0x00 */
3110 U32 Reserved1; /* 0x08 */
3111 U16 LogSequence; /* 0x0C */
3112 U16 LogEntryQualifier; /* 0x0E */
3113 U8 VP_ID; /* 0x10 */
3114 U8 VF_ID; /* 0x11 */
3115 U16 Reserved2; /* 0x12 */
3116 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
3120 /* values for Log Page 0 LogEntry LogEntryQualifier field */
3121 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
3122 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
3123 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
3124 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
3125 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
3129 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3130 U32 Reserved1; /* 0x08 */
3131 U32 Reserved2; /* 0x0C */
3132 U16 NumLogEntries; /* 0x10 */
3133 U16 Reserved3; /* 0x12 */
3134 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
3138 #define MPI2_LOG_0_PAGEVERSION (0x02)
3144 /* RAID Page 0 */
3156 U16 ElementFlags; /* 0x00 */
3157 U16 VolDevHandle; /* 0x02 */
3158 U8 HotSparePool; /* 0x04 */
3159 U8 PhysDiskNum; /* 0x05 */
3160 U16 PhysDiskDevHandle; /* 0x06 */
3166 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
3167 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
3168 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
3169 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
3170 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
3174 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3175 U8 NumHotSpares; /* 0x08 */
3176 U8 NumPhysDisks; /* 0x09 */
3177 U8 NumVolumes; /* 0x0A */
3178 U8 ConfigNum; /* 0x0B */
3179 U32 Flags; /* 0x0C */
3180 U8 ConfigGUID[24]; /* 0x10 */
3181 U32 Reserved1; /* 0x28 */
3182 U8 NumElements; /* 0x2C */
3183 U8 Reserved2; /* 0x2D */
3184 U16 Reserved3; /* 0x2E */
3185 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
3190 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
3192 /* values for RAID Configuration Page 0 Flags field */
3193 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
3199 /* Driver Persistent Mapping Page 0 */
3203 U64 PhysicalIdentifier; /* 0x00 */
3204 U16 MappingInformation; /* 0x08 */
3205 U16 DeviceIndex; /* 0x0A */
3206 U32 PhysicalBitsMapping; /* 0x0C */
3207 U32 Reserved1; /* 0x10 */
3214 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3215 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
3220 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
3222 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
3223 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
3225 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
3231 /* Ethernet Page 0 */
3245 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3246 U8 NumInterfaces; /* 0x08 */
3247 U8 Reserved0; /* 0x09 */
3248 U16 Reserved1; /* 0x0A */
3249 U32 Status; /* 0x0C */
3250 U8 MediaState; /* 0x10 */
3251 U8 Reserved2; /* 0x11 */
3252 U16 Reserved3; /* 0x12 */
3253 U8 MacAddress[6]; /* 0x14 */
3254 U8 Reserved4; /* 0x1A */
3255 U8 Reserved5; /* 0x1B */
3256 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
3257 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
3258 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
3259 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
3260 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
3261 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
3262 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
3266 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
3268 /* values for Ethernet Page 0 Status field */
3269 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
3270 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
3271 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
3272 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
3273 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
3274 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
3275 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
3276 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
3277 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
3278 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
3279 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
3280 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
3282 /* values for Ethernet Page 0 MediaState field */
3283 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
3284 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
3285 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
3287 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
3288 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
3289 #define MPI2_ETHPG0_MS_10MBIT (0x01)
3290 #define MPI2_ETHPG0_MS_100MBIT (0x02)
3291 #define MPI2_ETHPG0_MS_1GBIT (0x03)
3297 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3298 U32 Reserved0; /* 0x08 */
3299 U32 Flags; /* 0x0C */
3300 U8 MediaState; /* 0x10 */
3301 U8 Reserved1; /* 0x11 */
3302 U16 Reserved2; /* 0x12 */
3303 U8 MacAddress[6]; /* 0x14 */
3304 U8 Reserved3; /* 0x1A */
3305 U8 Reserved4; /* 0x1B */
3306 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
3307 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
3308 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
3309 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
3310 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
3311 U32 Reserved5; /* 0x6C */
3312 U32 Reserved6; /* 0x70 */
3313 U32 Reserved7; /* 0x74 */
3314 U32 Reserved8; /* 0x78 */
3315 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
3319 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
3322 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
3323 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
3324 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
3325 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
3326 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
3327 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
3328 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
3329 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
3330 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
3333 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
3334 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
3335 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
3337 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
3338 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
3339 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
3340 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
3341 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
3355 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3356 U32 ProductSpecificInfo; /* 0x08 */
3368 #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
3370 #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00)
3371 #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01)
3372 #define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02)
3373 #define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03)
3374 #define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04)
3375 #define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05)
3381 /* PCIe IO Unit Page 0 */
3385 U8 Link; /* 0x00 */
3386 U8 LinkFlags; /* 0x01 */
3387 U8 PhyFlags; /* 0x02 */
3388 U8 NegotiatedLinkRate; /* 0x03 */
3389 U32 ControllerPhyDeviceInfo;/* 0x04 */
3390 U16 AttachedDevHandle; /* 0x08 */
3391 U16 ControllerDevHandle; /* 0x0A */
3392 U32 EnumerationStatus; /* 0x0C */
3393 U32 Reserved1; /* 0x10 */
3407 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3408 U32 Reserved1; /* 0x08 */
3409 U8 NumPhys; /* 0x0C */
3410 U8 InitStatus; /* 0x0D */
3411 U16 Reserved3; /* 0x0E */
3412 MPI26_PCIE_IO_UNIT0_PHY_DATA PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX]; /* 0x10 */
3417 #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00)
3419 /* values for PCIe IO Unit Page 0 LinkFlags */
3420 #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08)
3422 /* values for PCIe IO Unit Page 0 PhyFlags */
3423 #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
3427 /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */
3429 /* values for PCIe IO Unit Page 0 EnumerationStatus */
3430 #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000)
3431 #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000)
3437 U8 Link; /* 0x00 */
3438 U8 LinkFlags; /* 0x01 */
3439 U8 PhyFlags; /* 0x02 */
3440 U8 MaxMinLinkRate; /* 0x03 */
3441 U32 ControllerPhyDeviceInfo; /* 0x04 */
3442 U32 Reserved1; /* 0x08 */
3447 #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK (0x00)
3448 #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN (0x01)
3449 #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN (0x02)
3461 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3462 U16 ControlFlags; /* 0x08 */
3463 U16 Reserved; /* 0x0A */
3464 U16 AdditionalControlFlags; /* 0x0C */
3465 U16 NVMeMaxQueueDepth; /* 0x0E */
3466 U8 NumPhys; /* 0x10 */
3467 U8 DMDReportPCIe; /* 0x11 */
3468 U16 Reserved2; /* 0x12 */
3469 MPI26_PCIE_IO_UNIT1_PHY_DATA PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/* 0x14 */
3474 #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00)
3477 #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
3478 #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01)
3481 #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0)
3483 #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20)
3484 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30)
3485 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40)
3486 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50)
3489 #define MPI26_PCIEIOUNIT1_DMD_REPORT_UNITS_MASK (0x80)
3490 #define MPI26_PCIEIOUNIT1_DMD_REPORT_UNITS_1_SEC (0x00)
3491 #define MPI26_PCIEIOUNIT1_DMD_REPORT_UNITS_16_SEC (0x80)
3492 #define MPI26_PCIEIOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7F)
3494 /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */
3500 /* PCIe Switch Page 0 */
3504 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3505 U8 PhysicalPort; /* 0x08 */
3506 U8 Reserved1; /* 0x09 */
3507 U16 Reserved2; /* 0x0A */
3508 U16 DevHandle; /* 0x0C */
3509 U16 ParentDevHandle; /* 0x0E */
3510 U8 NumPorts; /* 0x10 */
3511 U8 PCIeLevel; /* 0x11 */
3512 U16 Reserved3; /* 0x12 */
3513 U32 Reserved4; /* 0x14 */
3514 U32 Reserved5; /* 0x18 */
3515 U32 Reserved6; /* 0x1C */
3519 #define MPI26_PCIESWITCH0_PAGEVERSION (0x00)
3525 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3526 U8 PhysicalPort; /* 0x08 */
3527 U8 Reserved1; /* 0x09 */
3528 U16 Reserved2; /* 0x0A */
3529 U8 NumPorts; /* 0x0C */
3530 U8 PortNum; /* 0x0D */
3531 U16 AttachedDevHandle; /* 0x0E */
3532 U16 SwitchDevHandle; /* 0x10 */
3533 U8 NegotiatedPortWidth; /* 0x12 */
3534 U8 NegotiatedLinkRate; /* 0x13 */
3535 U16 Flags; /* 0x14 */
3536 U16 Reserved4; /* 0x16 */
3537 U32 Reserved5; /* 0x18 */
3541 #define MPI26_PCIESWITCH1_PAGEVERSION (0x00)
3546 #define MPI26_PCIESWITCH1_2_RETIMER_PRESENCE (0x0002)
3547 #define MPI26_PCIESWITCH1_RETIMER_PRESENCE (0x0001)
3553 /* PCIe Device Page 0 */
3557 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3558 U16 Slot; /* 0x08 */
3559 U16 EnclosureHandle; /* 0x0A */
3560 U64 WWID; /* 0x0C */
3561 U16 ParentDevHandle; /* 0x14 */
3562 U8 PortNum; /* 0x16 */
3563 U8 AccessStatus; /* 0x17 */
3564 U16 DevHandle; /* 0x18 */
3565 U8 PhysicalPort; /* 0x1A */
3566 U8 Reserved1; /* 0x1B */
3567 U32 DeviceInfo; /* 0x1C */
3568 U32 Flags; /* 0x20 */
3569 U8 SupportedLinkRates; /* 0x24 */
3570 U8 MaxPortWidth; /* 0x25 */
3571 U8 NegotiatedPortWidth; /* 0x26 */
3572 U8 NegotiatedLinkRate; /* 0x27 */
3573 U8 EnclosureLevel; /* 0x28 */
3574 U8 Reserved2; /* 0x29 */
3575 U16 Reserved3; /* 0x2A */
3576 U8 ConnectorName[4]; /* 0x2C */
3577 U32 Reserved4; /* 0x30 */
3578 U32 Reserved5; /* 0x34 */
3582 #define MPI26_PCIEDEVICE0_PAGEVERSION (0x01)
3584 /* values for PCIe Device Page 0 AccessStatus field */
3585 #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00)
3586 #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04)
3587 #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02)
3588 #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07)
3589 #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08)
3590 #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09)
3591 #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A)
3592 #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10)
3594 #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30)
3595 #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31)
3596 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32)
3597 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33)
3598 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34)
3599 #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35)
3600 #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36)
3601 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37)
3602 #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38)
3604 #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F)
3608 /* values for PCIe Device Page 0 Flags field */
3609 #define MPI26_PCIEDEV0_FLAGS_2_RETIMER_PRESENCE (0x00020000)
3610 #define MPI26_PCIEDEV0_FLAGS_RETIMER_PRESENCE (0x00010000)
3611 #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x00008000)
3612 #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x00004000)
3613 #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x00002000)
3614 #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x00000400)
3615 #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x00000200)
3616 #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x00000100)
3617 #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x00000080)
3618 #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x00000040)
3619 #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x00000020)
3620 #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x00000010)
3621 #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x00000002)
3622 #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x00000001)
3624 /* values for PCIe Device Page 0 SupportedLinkRates field */
3625 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08)
3626 #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04)
3627 #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02)
3628 #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01)
3636 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3637 U16 DevHandle; /* 0x08 */
3638 U8 ControllerResetTO; /* 0x0A */
3639 U8 Reserved1; /* 0x0B */
3640 U32 MaximumDataTransferSize;/* 0x0C */
3641 U32 Capabilities; /* 0x10 */
3642 U16 NOIOB; /* 0x14 */
3643 U16 Reserved2; /* 0x16 */
3647 #define MPI26_PCIEDEVICE2_PAGEVERSION (0x01)
3650 #define MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN (0x00000008)
3651 #define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004)
3652 #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002)
3653 #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001)
3656 #define MPI26_PCIEDEV2_NOIOB_UNSUPPORTED (0x0000)
3666 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3667 U8 Link; /* 0x08 */
3668 U8 Reserved1; /* 0x09 */
3669 U16 Reserved2; /* 0x0A */
3670 U32 CorrectableErrorCount; /* 0x0C */
3671 U16 NonFatalErrorCount; /* 0x10 */
3672 U16 Reserved3; /* 0x12 */
3673 U16 FatalErrorCount; /* 0x14 */
3674 U16 Reserved4; /* 0x16 */
3678 #define MPI26_PCIELINK1_PAGEVERSION (0x00)
3684 U8 LinkEventCode; /* 0x00 */
3685 U8 Reserved1; /* 0x01 */
3686 U16 Reserved2; /* 0x02 */
3687 U32 LinkEventInfo; /* 0x04 */
3703 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3704 U8 Link; /* 0x08 */
3705 U8 Reserved1; /* 0x09 */
3706 U16 Reserved2; /* 0x0A */
3707 U8 NumLinkEvents; /* 0x0C */
3708 U8 Reserved3; /* 0x0D */
3709 U16 Reserved4; /* 0x0E */
3710 MPI26_PCIELINK2_LINK_EVENT LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX]; /* 0x10 */
3714 #define MPI26_PCIELINK2_PAGEVERSION (0x00)
3720 U8 LinkEventCode; /* 0x00 */
3721 U8 Reserved1; /* 0x01 */
3722 U16 Reserved2; /* 0x02 */
3723 U8 CounterType; /* 0x04 */
3724 U8 ThresholdWindow; /* 0x05 */
3725 U8 TimeUnits; /* 0x06 */
3726 U8 Reserved3; /* 0x07 */
3727 U32 EventThreshold; /* 0x08 */
3728 U16 ThresholdFlags; /* 0x0C */
3729 U16 Reserved4; /* 0x0E */
3734 #define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00)
3735 #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01)
3736 #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02)
3737 #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03)
3738 #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04)
3739 #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05)
3740 #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06)
3741 #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07)
3742 #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08)
3743 #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09)
3744 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A)
3745 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B)
3746 #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C)
3747 #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D)
3748 #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E)
3749 #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F)
3750 #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10)
3751 #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11)
3752 #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12)
3755 #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00)
3756 #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01)
3757 #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02)
3760 #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00)
3761 #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01)
3762 #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02)
3763 #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03)
3766 #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001)
3778 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3779 U8 Link; /* 0x08 */
3780 U8 Reserved1; /* 0x09 */
3781 U16 Reserved2; /* 0x0A */
3782 U8 NumLinkEvents; /* 0x0C */
3783 U8 Reserved3; /* 0x0D */
3784 U16 Reserved4; /* 0x0E */
3785 MPI26_PCIELINK3_LINK_EVENT_CONFIG LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /* 0x10 */
3789 #define MPI26_PCIELINK3_PAGEVERSION (0x00)