Lines Matching +full:1 +full:- +full:sdxc
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Copyright (c) 2015-2016 Ilya Bakulin <kibab@FreeBSD.org>
11 * 1. Redistributions of source code must retain the above copyright
35 * Group. This Simplified Specification is provided on a non-confidential
38 * Association, SD Group, SD-3C LLC or other third parties.
44 * is provided "AS-IS" without any representations or warranties of any
45 * kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD
47 * right of the SD Group, SD-3C LLC, the SD Card Association or any third
50 * SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing
51 * herein shall be construed as an obligation by the SD Group, the SD-3C LLC
53 * information, know-how or other confidential information to any third party.
72 #define MMC_RSP_PRESENT (1ul << 0) /* Response */
73 #define MMC_RSP_136 (1ul << 1) /* 136 bit response */
74 #define MMC_RSP_CRC (1ul << 2) /* Expect valid crc */
75 #define MMC_RSP_BUSY (1ul << 3) /* Card may send busy */
76 #define MMC_RSP_OPCODE (1ul << 4) /* Response include opcode */
79 #define MMC_CMD_ADTC (1ul << 5) /* Addressed Data transfer cmd */
99 #define MMC_ERR_TIMEOUT 1
126 #define R1_OUT_OF_RANGE (1u << 31) /* erx, c */
127 #define R1_ADDRESS_ERROR (1u << 30) /* erx, c */
128 #define R1_BLOCK_LEN_ERROR (1u << 29) /* erx, c */
129 #define R1_ERASE_SEQ_ERROR (1u << 28) /* er, c */
130 #define R1_ERASE_PARAM (1u << 27) /* erx, c */
131 #define R1_WP_VIOLATION (1u << 26) /* erx, c */
132 #define R1_CARD_IS_LOCKED (1u << 25) /* sx, a */
133 #define R1_LOCK_UNLOCK_FAILED (1u << 24) /* erx, c */
134 #define R1_COM_CRC_ERROR (1u << 23) /* er, b */
135 #define R1_ILLEGAL_COMMAND (1u << 22) /* er, b */
136 #define R1_CARD_ECC_FAILED (1u << 21) /* erx, c */
137 #define R1_CC_ERROR (1u << 20) /* erx, c */
138 #define R1_ERROR (1u << 19) /* erx, c */
139 #define R1_CSD_OVERWRITE (1u << 16) /* erx, c */
140 #define R1_WP_ERASE_SKIP (1u << 15) /* erx, c */
141 #define R1_CARD_ECC_DISABLED (1u << 14) /* sx, a */
142 #define R1_ERASE_RESET (1u << 13) /* sr, c */
144 #define R1_READY_FOR_DATA (1u << 8) /* sx, a */
145 #define R1_SWITCH_ERROR (1u << 7) /* sx, c */
146 #define R1_APP_CMD (1u << 5) /* sr, c */
147 #define R1_AKE_SEQ_ERROR (1u << 3) /* er, c */
151 #define R1_STATE_READY 1
181 #define R5_COM_CRC_ERROR (1u << 15) /* er, b */
182 #define R5_ILLEGAL_COMMAND (1u << 14) /* er, b */
185 #define R5_ERROR (1u << 11) /* erx, c */
186 #define R5_FUNCTION_NUMBER (1u << 9) /* er, c */
187 #define R5_OUT_OF_RANGE (1u << 8) /* er, c */
194 #define MMC_DATA_WRITE (1UL << 0)
195 #define MMC_DATA_READ (1UL << 1)
196 #define MMC_DATA_STREAM (1UL << 2)
197 #define MMC_DATA_MULTI (1UL << 3)
198 #define MMC_DATA_BLOCK_SIZE (1UL << 4)
210 #define MMC_REQ_DONE 1
216 /* Class 0 and 1: Basic commands & read stream commands */
218 #define MMC_SEND_OP_COND 1
227 #define MMC_SWITCH_FUNC_SET 1
270 /* 34 -- reserved old command */
273 /* 37 -- reserved old command */
316 #define SD_ARG_CMD52_WRITE (1 << 31)
319 #define SD_ARG_CMD52_EXCHANGE (1 << 27)
329 #define SD_ARG_CMD53_WRITE (1 << 31)
332 #define SD_ARG_CMD53_BLOCK_MODE (1 << 27)
333 #define SD_ARG_CMD53_INCREMENT (1 << 26)
450 #define EXT_CSD_CMD_SET_NORMAL 1
455 #define EXT_CSD_HS_TIMING_HS 1
475 #define EXT_CSD_BUS_WIDTH_4 1
516 #define SD_SWITCH_MODE_SET 1
519 #define SD_SWITCH_HS_MODE 1
526 #define SD_SET_CARD_DETECT 1
541 #define SD_IO_RW_WR (1u << 31)
543 #define SD_IO_RW_RAW (1u << 27)
544 #define SD_IO_RW_INCR (1u << 26)
551 #define SD_IOE_RW_INCR (1u << 26)
552 #define SD_IOE_RW_BLK (1u << 27)
554 #define SD_IOE_RW_WR (1u << 31)
561 #define SD_IO_CCCR_INT_ENABLE 0x04 /* Per-function interrupt enable */
562 #define SD_IO_CCCR_INT_PENDING 0x05 /* Per-function interrupt pending */
564 #define CCCR_CTL_RES (1 << 3) /* Perform SDIO reset */
566 #define CCCR_BUS_WIDTH_4 (1 << 1)
567 #define CCCR_BUS_WIDTH_1 (1 << 0)
569 #define CCCR_CC_SMB (1 << 1) /* CMD53 block mode support */
570 #define CCCR_CC_LSC (1 << 6)
572 #define SD_IO_CCCR_CISPTR 0x09 /* 0x09 - 0x0B */
573 #define SD_IO_CCCR_FN0_BLKSZ 0x10 /* 0x10 - 0x11 */
575 #define CCCR_SPEED_SHS (1 << 0)
576 #define CCCR_SPEED_BSS_MASK (0x7 << 1)
577 #define CCCR_SPEED_EHS (1 << 1)
578 #define CCCR_SPEED_SDR12 (0 << 1)
579 #define CCCR_SPEED_SDR25 (1 << 1)
580 #define CCCR_SPEED_SDR50 (2 << 1)
581 #define CCCR_SPEED_SDR104 (3 << 1)
582 #define CCCR_SPEED_DDR50 (4 << 1)
588 #define SD_IO_FBR_START_F(n) (SD_IO_FBR_START + (n-1) * SD_IO_FBR_F_SIZE)
610 * in SD 2.0 spec, bits 8-14 are now marked reserved
612 * Low voltage in MC 3.31 spec is bit 7, 1.65-1.95V
613 * Specs prior to MMC 3.31 defined bits 0-7 as voltages down to 1.5V.
615 * support the 2.7-3.6V and fixed the OCR to be 0xfff8000 for high voltage
617 * Looks like the fine-grained control of the voltage tolerance ranges
623 #define MMC_OCR_LOW_VOLTAGE (1u << 7) /* Low Voltage Range -- tbd */
625 #define MMC_OCR_200_210 (1U << 8) /* Vdd voltage 2.00 ~ 2.10 */
626 #define MMC_OCR_210_220 (1U << 9) /* Vdd voltage 2.10 ~ 2.20 */
627 #define MMC_OCR_220_230 (1U << 10) /* Vdd voltage 2.20 ~ 2.30 */
628 #define MMC_OCR_230_240 (1U << 11) /* Vdd voltage 2.30 ~ 2.40 */
629 #define MMC_OCR_240_250 (1U << 12) /* Vdd voltage 2.40 ~ 2.50 */
630 #define MMC_OCR_250_260 (1U << 13) /* Vdd voltage 2.50 ~ 2.60 */
631 #define MMC_OCR_260_270 (1U << 14) /* Vdd voltage 2.60 ~ 2.70 */
632 #define MMC_OCR_270_280 (1U << 15) /* Vdd voltage 2.70 ~ 2.80 */
633 #define MMC_OCR_280_290 (1U << 16) /* Vdd voltage 2.80 ~ 2.90 */
634 #define MMC_OCR_290_300 (1U << 17) /* Vdd voltage 2.90 ~ 3.00 */
635 #define MMC_OCR_300_310 (1U << 18) /* Vdd voltage 3.00 ~ 3.10 */
636 #define MMC_OCR_310_320 (1U << 19) /* Vdd voltage 3.10 ~ 3.20 */
637 #define MMC_OCR_320_330 (1U << 20) /* Vdd voltage 3.20 ~ 3.30 */
638 #define MMC_OCR_330_340 (1U << 21) /* Vdd voltage 3.30 ~ 3.40 */
639 #define MMC_OCR_340_350 (1U << 22) /* Vdd voltage 3.40 ~ 3.50 */
640 #define MMC_OCR_350_360 (1U << 23) /* Vdd voltage 3.50 ~ 3.60 */
642 #define MMC_OCR_S18R (1U << 24) /* Switching to 1.8 V requested (SD) */
644 #define MMC_OCR_XPC (1U << 28) /* SDXC Power Control */
646 #define MMC_OCR_ACCESS_MODE_SECT (1U << 29) /* Access Mode Sector (MMC) */
648 #define MMC_OCR_CCS (1u << 30) /* Card Capacity status (SD vs SDHC) */
649 #define MMC_OCR_CARD_BUSY (1U << 31) /* Card Power up status */
651 /* CSD -- decoded structure */
680 unsigned int read_bl_partial:1,
681 read_blk_misalign:1,
682 write_bl_partial:1,
683 write_blk_misalign:1,
684 dsr_imp:1,
685 erase_blk_en:1,
686 wp_grp_enable:1;
692 #define SD_SCR_BUS_WIDTH_1 (1 << 0)
693 #define SD_SCR_BUS_WIDTH_4 (1 << 2)
711 #define MMC_QUIRK_MID_ANY ((uint32_t)-1)
713 #define MMC_QUIRK_OID_ANY ((uint16_t)-1)