Lines Matching +full:timeout +full:- +full:enable
1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
37 #define SDMMC_CTRL_INT_ENABLE (1 << 4) /* Enable interrupts */
41 #define SDMMC_PWREN 0x4 /* Power Enable Register */
45 #define SDMMC_CLKENA 0x10 /* Clock Enable Register */
46 #define SDMMC_CLKENA_LP (1 << 16) /* Low-power mode */
47 #define SDMMC_CLKENA_CCLK_EN (1 << 0) /* SD/MMC Enable */
48 #define SDMMC_TMOUT 0x14 /* Timeout Register */
55 #define SDMMC_INTMASK_SDIO (1 << 16) /* SDIO Interrupt Enable */
56 #define SDMMC_INTMASK_EBE (1 << 15) /* End-bit error */
58 #define SDMMC_INTMASK_SBE (1 << 13) /* Start-bit error */
61 #define SDMMC_INTMASK_HTO (1 << 10) /* Data starvation by host timeout */
62 #define SDMMC_INTMASK_DRT (1 << 9) /* Data read timeout */
63 #define SDMMC_INTMASK_RTO (1 << 8) /* Response timeout */
104 #define SDMMC_TBBCNT 0x60 /* Transferred Host to BIU-FIFO Byte Count */
109 #define SDMMC_UHS_REG 0x74 /* UHS-1 Register */
113 #define SDMMC_BMOD_DE (1 << 7) /* IDMAC Enable */
119 #define SDMMC_IDINTEN 0x90 /* Internal DMAC Interrupt Enable */
149 /* Platform-specific defines */