Lines Matching +full:reg +full:- +full:data
1 /*-
2 * Copyright (c) 2014-2019 Ruslan Bukin <br@bsdpad.com>
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * Chapter 14, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22)
89 bus_read_4((_sc)->res[0], _reg)
91 bus_write_4((_sc)->res[0], _reg, _val)
95 #define DWMMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
96 #define DWMMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
98 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
100 #define DWMMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
101 #define DWMMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
102 #define DWMMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
137 * but must be a multiple of the data bus size.Additionally, we must ensure
149 #define DWMMC_MAX_DATA (IDMAC_MAX_SIZE * (IDMAC_DESC_SEGS - 2)) / MMC_SECTOR_SIZE
162 { -1, 0 }
192 sc->desc_ring[idx].des0 = DES0_DIC | DES0_CH; in dwmmc_ring_setup()
193 sc->desc_ring[idx].des1 = segs[idx].ds_len & DES1_BS1_MASK; in dwmmc_ring_setup()
194 sc->desc_ring[idx].des2 = segs[idx].ds_addr; in dwmmc_ring_setup()
197 sc->desc_ring[idx].des0 |= DES0_FS; in dwmmc_ring_setup()
199 if (idx == (nsegs - 1)) { in dwmmc_ring_setup()
200 sc->desc_ring[idx].des0 &= ~(DES0_DIC | DES0_CH); in dwmmc_ring_setup()
201 sc->desc_ring[idx].des0 |= DES0_LD; in dwmmc_ring_setup()
204 sc->desc_ring[idx].des0 |= DES0_OWN; in dwmmc_ring_setup()
211 int reg; in dwmmc_ctrl_reset() local
214 reg = READ4(sc, SDMMC_CTRL); in dwmmc_ctrl_reset()
215 reg |= (reset_bits); in dwmmc_ctrl_reset()
216 WRITE4(sc, SDMMC_CTRL, reg); in dwmmc_ctrl_reset()
225 device_printf(sc->dev, "Reset failed\n"); in dwmmc_ctrl_reset()
241 bus_get_dma_tag(sc->dev), /* Parent tag. */ in dma_setup()
250 &sc->desc_tag); in dma_setup()
252 device_printf(sc->dev, in dma_setup()
257 error = bus_dmamem_alloc(sc->desc_tag, (void**)&sc->desc_ring, in dma_setup()
259 &sc->desc_map); in dma_setup()
261 device_printf(sc->dev, in dma_setup()
266 error = bus_dmamap_load(sc->desc_tag, sc->desc_map, in dma_setup()
267 sc->desc_ring, IDMAC_DESC_SIZE, dwmmc_get1paddr, in dma_setup()
268 &sc->desc_ring_paddr, 0); in dma_setup()
270 device_printf(sc->dev, in dma_setup()
276 sc->desc_ring[idx].des0 = DES0_CH; in dma_setup()
277 sc->desc_ring[idx].des1 = 0; in dma_setup()
279 sc->desc_ring[idx].des3 = sc->desc_ring_paddr + \ in dma_setup()
282 sc->desc_ring[idx - 1].des3 = sc->desc_ring_paddr; in dma_setup()
283 sc->desc_ring[idx - 1].des0 |= DES0_ER; in dma_setup()
286 bus_get_dma_tag(sc->dev), /* Parent tag. */ in dma_setup()
296 &sc->buf_tag); in dma_setup()
298 device_printf(sc->dev, in dma_setup()
303 error = bus_dmamap_create(sc->buf_tag, 0, in dma_setup()
304 &sc->buf_map); in dma_setup()
306 device_printf(sc->dev, in dma_setup()
323 ccb = sc->ccb; in dwmmc_cmd_done()
326 cmd = &ccb->mmcio.cmd; in dwmmc_cmd_done()
328 cmd = sc->curcmd; in dwmmc_cmd_done()
333 if (cmd->flags & MMC_RSP_PRESENT) { in dwmmc_cmd_done()
334 if (cmd->flags & MMC_RSP_136) { in dwmmc_cmd_done()
335 cmd->resp[3] = READ4(sc, SDMMC_RESP0); in dwmmc_cmd_done()
336 cmd->resp[2] = READ4(sc, SDMMC_RESP1); in dwmmc_cmd_done()
337 cmd->resp[1] = READ4(sc, SDMMC_RESP2); in dwmmc_cmd_done()
338 cmd->resp[0] = READ4(sc, SDMMC_RESP3); in dwmmc_cmd_done()
340 cmd->resp[3] = 0; in dwmmc_cmd_done()
341 cmd->resp[2] = 0; in dwmmc_cmd_done()
342 cmd->resp[1] = 0; in dwmmc_cmd_done()
343 cmd->resp[0] = READ4(sc, SDMMC_RESP0); in dwmmc_cmd_done()
353 cmd = sc->curcmd; in dwmmc_tasklet()
357 if (!sc->cmd_done) in dwmmc_tasklet()
360 if (cmd->error != MMC_ERR_NONE || !cmd->data) { in dwmmc_tasklet()
362 } else if (cmd->data && sc->dto_rcvd) { in dwmmc_tasklet()
363 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || in dwmmc_tasklet()
364 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && in dwmmc_tasklet()
365 sc->use_auto_stop) { in dwmmc_tasklet()
366 if (sc->acd_rcvd) in dwmmc_tasklet()
379 uint32_t reg; in dwmmc_intr() local
385 cmd = sc->curcmd; in dwmmc_intr()
388 reg = READ4(sc, SDMMC_MINTSTS); in dwmmc_intr()
389 if (reg) { in dwmmc_intr()
390 dprintf("%s 0x%08x\n", __func__, reg); in dwmmc_intr()
392 if (reg & DWMMC_CMD_ERR_FLAGS) { in dwmmc_intr()
394 reg, cmd->opcode); in dwmmc_intr()
395 cmd->error = MMC_ERR_TIMEOUT; in dwmmc_intr()
398 if (reg & DWMMC_DATA_ERR_FLAGS) { in dwmmc_intr()
399 dprintf("data err 0x%08x cmd 0x%08x\n", in dwmmc_intr()
400 reg, cmd->opcode); in dwmmc_intr()
401 cmd->error = MMC_ERR_FAILED; in dwmmc_intr()
402 if (!sc->use_pio) { in dwmmc_intr()
408 if (reg & SDMMC_INTMASK_CMD_DONE) { in dwmmc_intr()
410 sc->cmd_done = 1; in dwmmc_intr()
413 if (reg & SDMMC_INTMASK_ACD) in dwmmc_intr()
414 sc->acd_rcvd = 1; in dwmmc_intr()
416 if (reg & SDMMC_INTMASK_DTO) in dwmmc_intr()
417 sc->dto_rcvd = 1; in dwmmc_intr()
419 if (reg & SDMMC_INTMASK_CD) { in dwmmc_intr()
426 WRITE4(sc, SDMMC_RINTSTS, reg); in dwmmc_intr()
428 if (sc->use_pio) { in dwmmc_intr()
429 if (reg & (SDMMC_INTMASK_RXDR|SDMMC_INTMASK_DTO)) { in dwmmc_intr()
432 if (reg & (SDMMC_INTMASK_TXDR|SDMMC_INTMASK_DTO)) { in dwmmc_intr()
437 reg = READ4(sc, SDMMC_IDSTS); in dwmmc_intr()
438 if (reg) { in dwmmc_intr()
439 dprintf("dma intr 0x%08x\n", reg); in dwmmc_intr()
440 if (reg & (SDMMC_IDINTEN_TI | SDMMC_IDINTEN_RI)) { in dwmmc_intr()
462 was_present = sc->child != NULL; in dwmmc_handle_card_present()
466 &sc->card_delayed_task, -(hz / 2)); in dwmmc_handle_card_present()
468 taskqueue_enqueue(taskqueue_bus, &sc->card_task); in dwmmc_handle_card_present()
478 mmc_cam_sim_discover(&sc->mmc_sim); in dwmmc_card_task()
482 (sc->mmc_helper.props & MMC_PROP_BROKEN_CD)) { in dwmmc_card_task()
483 if (sc->child == NULL) { in dwmmc_card_task()
485 device_printf(sc->dev, "Card inserted\n"); in dwmmc_card_task()
487 sc->child = device_add_child(sc->dev, "mmc", DEVICE_UNIT_ANY); in dwmmc_card_task()
488 if (sc->child) { in dwmmc_card_task()
489 device_set_ivars(sc->child, sc); in dwmmc_card_task()
490 (void)device_probe_and_attach(sc->child); in dwmmc_card_task()
495 if (sc->child != NULL) { in dwmmc_card_task()
497 device_printf(sc->dev, "Card removed\n"); in dwmmc_card_task()
499 device_delete_child(sc->dev, sc->child); in dwmmc_card_task()
500 sc->child = NULL; in dwmmc_card_task()
516 if ((node = ofw_bus_get_node(sc->dev)) == -1) in parse_fdt()
520 sc->host.f_min = 400000; in parse_fdt()
521 sc->host.f_max = 200000000; in parse_fdt()
522 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; in parse_fdt()
523 sc->host.caps = MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330; in parse_fdt()
524 mmc_fdt_parse(sc->dev, node, &sc->mmc_helper, &sc->host); in parse_fdt()
526 /* fifo-depth */ in parse_fdt()
527 if ((len = OF_getproplen(node, "fifo-depth")) > 0) { in parse_fdt()
528 OF_getencprop(node, "fifo-depth", dts_value, len); in parse_fdt()
529 sc->fifo_depth = dts_value[0]; in parse_fdt()
532 /* num-slots (Deprecated) */ in parse_fdt()
533 sc->num_slots = 1; in parse_fdt()
534 if ((len = OF_getproplen(node, "num-slots")) > 0) { in parse_fdt()
535 device_printf(sc->dev, "num-slots property is deprecated\n"); in parse_fdt()
536 OF_getencprop(node, "num-slots", dts_value, len); in parse_fdt()
537 sc->num_slots = dts_value[0]; in parse_fdt()
540 /* clock-frequency */ in parse_fdt()
541 if ((len = OF_getproplen(node, "clock-frequency")) > 0) { in parse_fdt()
542 OF_getencprop(node, "clock-frequency", dts_value, len); in parse_fdt()
547 error = hwreset_get_by_ofw_name(sc->dev, 0, "reset", &sc->hwreset); in parse_fdt()
551 device_printf(sc->dev, "Cannot get reset\n"); in parse_fdt()
556 error = regulator_get_by_ofw_property(sc->dev, 0, "vmmc-supply", in parse_fdt()
557 &sc->vmmc); in parse_fdt()
561 device_printf(sc->dev, "Cannot get regulator 'vmmc-supply'\n"); in parse_fdt()
566 error = regulator_get_by_ofw_property(sc->dev, 0, "vqmmc-supply", in parse_fdt()
567 &sc->vqmmc); in parse_fdt()
571 device_printf(sc->dev, "Cannot get regulator 'vqmmc-supply'\n"); in parse_fdt()
576 if (sc->hwreset != NULL) { in parse_fdt()
577 error = hwreset_assert(sc->hwreset); in parse_fdt()
579 device_printf(sc->dev, "Cannot assert reset\n"); in parse_fdt()
585 error = clk_get_by_ofw_name(sc->dev, 0, "biu", &sc->biu); in parse_fdt()
589 device_printf(sc->dev, "Cannot get 'biu' clock\n"); in parse_fdt()
593 if (sc->biu) { in parse_fdt()
594 error = clk_enable(sc->biu); in parse_fdt()
596 device_printf(sc->dev, "cannot enable biu clock\n"); in parse_fdt()
603 * if no clock-frequency property is given in parse_fdt()
605 error = clk_get_by_ofw_name(sc->dev, 0, "ciu", &sc->ciu); in parse_fdt()
609 device_printf(sc->dev, "Cannot get 'ciu' clock\n"); in parse_fdt()
613 if (sc->ciu) { in parse_fdt()
615 error = clk_set_freq(sc->ciu, bus_hz, 0); in parse_fdt()
617 device_printf(sc->dev, in parse_fdt()
620 error = clk_enable(sc->ciu); in parse_fdt()
622 device_printf(sc->dev, "cannot enable ciu clock\n"); in parse_fdt()
625 clk_get_freq(sc->ciu, &sc->bus_hz); in parse_fdt()
629 if (sc->vmmc != NULL) { in parse_fdt()
630 error = regulator_enable(sc->vmmc); in parse_fdt()
632 device_printf(sc->dev, "Cannot enable vmmc regulator\n"); in parse_fdt()
636 if (sc->vqmmc != NULL) { in parse_fdt()
637 error = regulator_enable(sc->vqmmc); in parse_fdt()
639 device_printf(sc->dev, "Cannot enable vqmmc regulator\n"); in parse_fdt()
645 if (sc->hwreset != NULL) { in parse_fdt()
646 error = hwreset_deassert(sc->hwreset); in parse_fdt()
648 device_printf(sc->dev, "Cannot deassert reset\n"); in parse_fdt()
653 if (sc->bus_hz == 0) { in parse_fdt()
654 device_printf(sc->dev, "No bus speed provided\n"); in parse_fdt()
672 sc->dev = dev; in dwmmc_attach()
675 sc->use_auto_stop = 1; in dwmmc_attach()
685 if (bus_alloc_resources(dev, dwmmc_spec, sc->res)) { in dwmmc_attach()
691 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, in dwmmc_attach()
692 NULL, dwmmc_intr, sc, &sc->intr_cookie); in dwmmc_attach()
707 dwmmc_setup_bus(sc, sc->host.f_min); in dwmmc_attach()
709 if (sc->fifo_depth == 0) { in dwmmc_attach()
710 sc->fifo_depth = 1 + in dwmmc_attach()
712 device_printf(dev, "No fifo-depth, using FIFOTH %x\n", in dwmmc_attach()
713 sc->fifo_depth); in dwmmc_attach()
716 if (!sc->use_pio) { in dwmmc_attach()
722 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr); in dwmmc_attach()
749 TASK_INIT(&sc->card_task, 0, dwmmc_card_task, sc); in dwmmc_attach()
750 TIMEOUT_TASK_INIT(taskqueue_bus, &sc->card_delayed_task, 0, in dwmmc_attach()
754 sc->ccb = NULL; in dwmmc_attach()
755 if (mmc_cam_sim_alloc(dev, "dw_mmc", &sc->mmc_sim) != 0) { in dwmmc_attach()
781 taskqueue_drain(taskqueue_bus, &sc->card_task); in dwmmc_detach()
782 taskqueue_drain_timeout(taskqueue_bus, &sc->card_delayed_task); in dwmmc_detach()
784 if (sc->intr_cookie != NULL) { in dwmmc_detach()
785 ret = bus_teardown_intr(dev, sc->res[1], sc->intr_cookie); in dwmmc_detach()
789 bus_release_resources(dev, dwmmc_spec, sc->res); in dwmmc_detach()
793 if (sc->hwreset != NULL && hwreset_deassert(sc->hwreset) != 0) in dwmmc_detach()
794 device_printf(sc->dev, "cannot deassert reset\n"); in dwmmc_detach()
795 if (sc->biu != NULL && clk_disable(sc->biu) != 0) in dwmmc_detach()
796 device_printf(sc->dev, "cannot disable biu clock\n"); in dwmmc_detach()
797 if (sc->ciu != NULL && clk_disable(sc->ciu) != 0) in dwmmc_detach()
798 device_printf(sc->dev, "cannot disable ciu clock\n"); in dwmmc_detach()
800 if (sc->vmmc && regulator_disable(sc->vmmc) != 0) in dwmmc_detach()
801 device_printf(sc->dev, "Cannot disable vmmc regulator\n"); in dwmmc_detach()
802 if (sc->vqmmc && regulator_disable(sc->vqmmc) != 0) in dwmmc_detach()
803 device_printf(sc->dev, "Cannot disable vqmmc regulator\n"); in dwmmc_detach()
806 mmc_cam_sim_free(&sc->mmc_sim); in dwmmc_detach()
825 if (tout-- < 0) { in dwmmc_setup_bus()
826 device_printf(sc->dev, "Failed update clk\n"); in dwmmc_setup_bus()
837 div = (sc->bus_hz != freq) ? DIV_ROUND_UP(sc->bus_hz, 2 * freq) : 0; in dwmmc_setup_bus()
845 if (tout-- < 0) { in dwmmc_setup_bus()
846 device_printf(sc->dev, "Failed to update clk\n"); in dwmmc_setup_bus()
857 if (tout-- < 0) { in dwmmc_setup_bus()
858 device_printf(sc->dev, "Failed to enable clk\n"); in dwmmc_setup_bus()
871 uint32_t reg; in dwmmc_update_ios() local
875 ios = &sc->host.ios; in dwmmc_update_ios()
878 ios->clock, ios->bus_width, ios->timing); in dwmmc_update_ios()
880 switch (ios->power_mode) { in dwmmc_update_ios()
891 mmc_fdt_set_power(&sc->mmc_helper, ios->power_mode); in dwmmc_update_ios()
893 if (ios->bus_width == bus_width_8) in dwmmc_update_ios()
895 else if (ios->bus_width == bus_width_4) in dwmmc_update_ios()
900 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_EXYNOS) { in dwmmc_update_ios()
902 WRITE4(sc, SDMMC_CLKSEL, sc->sdr_timing); in dwmmc_update_ios()
906 reg = READ4(sc, SDMMC_UHS_REG); in dwmmc_update_ios()
907 if (ios->timing == bus_timing_uhs_ddr50 || in dwmmc_update_ios()
908 ios->timing == bus_timing_mmc_ddr52 || in dwmmc_update_ios()
909 ios->timing == bus_timing_mmc_hs400) in dwmmc_update_ios()
910 reg |= (SDMMC_UHS_REG_DDR); in dwmmc_update_ios()
912 reg &= ~(SDMMC_UHS_REG_DDR); in dwmmc_update_ios()
913 WRITE4(sc, SDMMC_UHS_REG, reg); in dwmmc_update_ios()
915 if (sc->update_ios) in dwmmc_update_ios()
916 ret = sc->update_ios(sc, ios); in dwmmc_update_ios()
918 dwmmc_setup_bus(sc, ios->clock); in dwmmc_update_ios()
926 struct mmc_data *data; in dma_done() local
928 data = cmd->data; in dma_done()
930 if (data->flags & MMC_DATA_WRITE) in dma_done()
931 bus_dmamap_sync(sc->buf_tag, sc->buf_map, in dma_done()
934 bus_dmamap_sync(sc->buf_tag, sc->buf_map, in dma_done()
937 bus_dmamap_sync(sc->desc_tag, sc->desc_map, in dma_done()
940 bus_dmamap_unload(sc->buf_tag, sc->buf_map); in dma_done()
948 int reg; in dma_stop() local
950 reg = READ4(sc, SDMMC_CTRL); in dma_stop()
951 reg &= ~(SDMMC_CTRL_USE_IDMAC); in dma_stop()
952 reg |= (SDMMC_CTRL_DMA_RESET); in dma_stop()
953 WRITE4(sc, SDMMC_CTRL, reg); in dma_stop()
955 reg = READ4(sc, SDMMC_BMOD); in dma_stop()
956 reg &= ~(SDMMC_BMOD_DE | SDMMC_BMOD_FB); in dma_stop()
957 reg |= (SDMMC_BMOD_SWR); in dma_stop()
958 WRITE4(sc, SDMMC_BMOD, reg); in dma_stop()
966 struct mmc_data *data; in dma_prepare() local
968 int reg; in dma_prepare() local
970 data = cmd->data; in dma_prepare()
972 reg = READ4(sc, SDMMC_INTMASK); in dma_prepare()
973 reg &= ~(SDMMC_INTMASK_TXDR | SDMMC_INTMASK_RXDR); in dma_prepare()
974 WRITE4(sc, SDMMC_INTMASK, reg); in dma_prepare()
975 dprintf("%s: bus_dmamap_load size: %zu\n", __func__, data->len); in dma_prepare()
976 err = bus_dmamap_load(sc->buf_tag, sc->buf_map, in dma_prepare()
977 data->data, data->len, dwmmc_ring_setup, in dma_prepare()
983 bus_dmamap_sync(sc->desc_tag, sc->desc_map, in dma_prepare()
986 if (data->flags & MMC_DATA_WRITE) in dma_prepare()
987 bus_dmamap_sync(sc->buf_tag, sc->buf_map, in dma_prepare()
990 bus_dmamap_sync(sc->buf_tag, sc->buf_map, in dma_prepare()
993 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S); in dma_prepare()
994 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S; in dma_prepare()
995 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S; in dma_prepare()
997 WRITE4(sc, SDMMC_FIFOTH, reg); in dma_prepare()
1000 reg = READ4(sc, SDMMC_CTRL); in dma_prepare()
1001 reg |= (SDMMC_CTRL_USE_IDMAC | SDMMC_CTRL_DMA_ENABLE); in dma_prepare()
1002 WRITE4(sc, SDMMC_CTRL, reg); in dma_prepare()
1005 reg = READ4(sc, SDMMC_BMOD); in dma_prepare()
1006 reg |= (SDMMC_BMOD_DE | SDMMC_BMOD_FB); in dma_prepare()
1007 WRITE4(sc, SDMMC_BMOD, reg); in dma_prepare()
1018 struct mmc_data *data; in pio_prepare() local
1019 int reg; in pio_prepare() local
1021 data = cmd->data; in pio_prepare()
1022 data->xfer_len = 0; in pio_prepare()
1024 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S); in pio_prepare()
1025 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S; in pio_prepare()
1026 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S; in pio_prepare()
1028 WRITE4(sc, SDMMC_FIFOTH, reg); in pio_prepare()
1037 struct mmc_data *data; in pio_read() local
1040 if (cmd == NULL || cmd->data == NULL) in pio_read()
1043 data = cmd->data; in pio_read()
1044 if ((data->flags & MMC_DATA_READ) == 0) in pio_read()
1047 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned")); in pio_read()
1048 p = (uint32_t *)data->data + (data->xfer_len >> 2); in pio_read()
1050 while (data->xfer_len < data->len) { in pio_read()
1055 data->xfer_len += 4; in pio_read()
1064 struct mmc_data *data; in pio_write() local
1067 if (cmd == NULL || cmd->data == NULL) in pio_write()
1070 data = cmd->data; in pio_write()
1071 if ((data->flags & MMC_DATA_WRITE) == 0) in pio_write()
1074 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned")); in pio_write()
1075 p = (uint32_t *)data->data + (data->xfer_len >> 2); in pio_write()
1077 while (data->xfer_len < data->len) { in pio_write()
1082 data->xfer_len += 4; in pio_write()
1091 struct mmc_data *data; in dwmmc_start_cmd() local
1096 sc->curcmd = cmd; in dwmmc_start_cmd()
1097 data = cmd->data; in dwmmc_start_cmd()
1101 cmd->mrq = sc->req; in dwmmc_start_cmd()
1105 cmdr = cmd->opcode; in dwmmc_start_cmd()
1107 dprintf("cmd->opcode 0x%08x\n", cmd->opcode); in dwmmc_start_cmd()
1109 if (cmd->opcode == MMC_STOP_TRANSMISSION || in dwmmc_start_cmd()
1110 cmd->opcode == MMC_GO_IDLE_STATE || in dwmmc_start_cmd()
1111 cmd->opcode == MMC_GO_INACTIVE_STATE) in dwmmc_start_cmd()
1113 else if (cmd->opcode != MMC_SEND_STATUS && data) in dwmmc_start_cmd()
1117 if (MMC_RSP(cmd->flags) != MMC_RSP_NONE) { in dwmmc_start_cmd()
1119 if (cmd->flags & MMC_RSP_136) in dwmmc_start_cmd()
1123 if (cmd->flags & MMC_RSP_CRC) in dwmmc_start_cmd()
1131 if ((sc->flags & CARD_INIT_DONE) == 0) { in dwmmc_start_cmd()
1132 sc->flags |= (CARD_INIT_DONE); in dwmmc_start_cmd()
1136 if (data) { in dwmmc_start_cmd()
1137 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || in dwmmc_start_cmd()
1138 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && in dwmmc_start_cmd()
1139 sc->use_auto_stop) in dwmmc_start_cmd()
1143 if (data->flags & MMC_DATA_STREAM) in dwmmc_start_cmd()
1145 if (data->flags & MMC_DATA_WRITE) in dwmmc_start_cmd()
1150 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) { in dwmmc_start_cmd()
1151 WRITE4(sc, SDMMC_BLKSIZ, cmd->data->block_size); in dwmmc_start_cmd()
1152 WRITE4(sc, SDMMC_BYTCNT, cmd->data->len); in dwmmc_start_cmd()
1156 WRITE4(sc, SDMMC_BYTCNT, data->len); in dwmmc_start_cmd()
1157 blksz = (data->len < MMC_SECTOR_SIZE) ? \ in dwmmc_start_cmd()
1158 data->len : MMC_SECTOR_SIZE; in dwmmc_start_cmd()
1162 if (sc->use_pio) { in dwmmc_start_cmd()
1172 WRITE4(sc, SDMMC_CMDARG, cmd->arg); in dwmmc_start_cmd()
1185 ccb = sc->ccb; in dwmmc_next_operation()
1188 cmd = &ccb->mmcio.cmd; in dwmmc_next_operation()
1192 req = sc->req; in dwmmc_next_operation()
1195 cmd = req->cmd; in dwmmc_next_operation()
1198 sc->acd_rcvd = 0; in dwmmc_next_operation()
1199 sc->dto_rcvd = 0; in dwmmc_next_operation()
1200 sc->cmd_done = 0; in dwmmc_next_operation()
1204 * We do need this to prevent data timeouts, in dwmmc_next_operation()
1205 * mostly caused by multi-block write command in dwmmc_next_operation()
1206 * followed by single-read. in dwmmc_next_operation()
1211 if (sc->flags & PENDING_CMD) { in dwmmc_next_operation()
1212 sc->flags &= ~PENDING_CMD; in dwmmc_next_operation()
1215 } else if (sc->flags & PENDING_STOP && !sc->use_auto_stop) { in dwmmc_next_operation()
1216 sc->flags &= ~PENDING_STOP; in dwmmc_next_operation()
1218 //dwmmc_start_cmd(sc, req->stop); in dwmmc_next_operation()
1223 sc->ccb = NULL; in dwmmc_next_operation()
1224 sc->curcmd = NULL; in dwmmc_next_operation()
1225 ccb->ccb_h.status = in dwmmc_next_operation()
1226 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); in dwmmc_next_operation()
1229 sc->req = NULL; in dwmmc_next_operation()
1230 sc->curcmd = NULL; in dwmmc_next_operation()
1231 req->done(req); in dwmmc_next_operation()
1247 sc->flags |= PENDING_CMD; in dwmmc_request()
1249 if (sc->req != NULL) { in dwmmc_request()
1254 sc->req = req; in dwmmc_request()
1255 sc->flags |= PENDING_CMD; in dwmmc_request()
1256 if (sc->req->stop) in dwmmc_request()
1257 sc->flags |= PENDING_STOP; in dwmmc_request()
1283 while (sc->bus_busy) in dwmmc_acquire_host()
1284 msleep(sc, &sc->sc_mtx, PZERO, "dwmmcah", hz / 5); in dwmmc_acquire_host()
1285 sc->bus_busy++; in dwmmc_acquire_host()
1298 sc->bus_busy--; in dwmmc_release_host()
1316 *(int *)result = sc->host.ios.bus_mode; in dwmmc_read_ivar()
1319 *(int *)result = sc->host.ios.bus_width; in dwmmc_read_ivar()
1322 *(int *)result = sc->host.ios.chip_select; in dwmmc_read_ivar()
1325 *(int *)result = sc->host.ios.clock; in dwmmc_read_ivar()
1328 *(int *)result = sc->host.f_min; in dwmmc_read_ivar()
1331 *(int *)result = sc->host.f_max; in dwmmc_read_ivar()
1334 *(int *)result = sc->host.host_ocr; in dwmmc_read_ivar()
1337 *(int *)result = sc->host.mode; in dwmmc_read_ivar()
1340 *(int *)result = sc->host.ocr; in dwmmc_read_ivar()
1343 *(int *)result = sc->host.ios.power_mode; in dwmmc_read_ivar()
1346 *(int *)result = sc->host.ios.vdd; in dwmmc_read_ivar()
1349 *(int *)result = sc->host.ios.vccq; in dwmmc_read_ivar()
1352 *(int *)result = sc->host.caps; in dwmmc_read_ivar()
1358 *(int *)result = sc->host.ios.timing; in dwmmc_read_ivar()
1375 sc->host.ios.bus_mode = value; in dwmmc_write_ivar()
1378 sc->host.ios.bus_width = value; in dwmmc_write_ivar()
1381 sc->host.ios.chip_select = value; in dwmmc_write_ivar()
1384 sc->host.ios.clock = value; in dwmmc_write_ivar()
1387 sc->host.mode = value; in dwmmc_write_ivar()
1390 sc->host.ocr = value; in dwmmc_write_ivar()
1393 sc->host.ios.power_mode = value; in dwmmc_write_ivar()
1396 sc->host.ios.vdd = value; in dwmmc_write_ivar()
1399 sc->host.ios.timing = value; in dwmmc_write_ivar()
1402 sc->host.ios.vccq = value; in dwmmc_write_ivar()
1404 /* These are read-only */ in dwmmc_write_ivar()
1431 cts->host_ocr = sc->host.host_ocr; in dwmmc_get_tran_settings()
1432 cts->host_f_min = sc->host.f_min; in dwmmc_get_tran_settings()
1433 cts->host_f_max = sc->host.f_max; in dwmmc_get_tran_settings()
1434 cts->host_caps = sc->host.caps; in dwmmc_get_tran_settings()
1435 cts->host_max_data = DWMMC_MAX_DATA; in dwmmc_get_tran_settings()
1436 memcpy(&cts->ios, &sc->host.ios, sizeof(struct mmc_ios)); in dwmmc_get_tran_settings()
1450 ios = &sc->host.ios; in dwmmc_set_tran_settings()
1452 new_ios = &cts->ios; in dwmmc_set_tran_settings()
1455 if (cts->ios_valid & MMC_CLK) { in dwmmc_set_tran_settings()
1456 ios->clock = new_ios->clock; in dwmmc_set_tran_settings()
1458 device_printf(sc->dev, "Clock => %d\n", ios->clock); in dwmmc_set_tran_settings()
1460 if (cts->ios_valid & MMC_VDD) { in dwmmc_set_tran_settings()
1461 ios->vdd = new_ios->vdd; in dwmmc_set_tran_settings()
1463 device_printf(sc->dev, "VDD => %d\n", ios->vdd); in dwmmc_set_tran_settings()
1465 if (cts->ios_valid & MMC_CS) { in dwmmc_set_tran_settings()
1466 ios->chip_select = new_ios->chip_select; in dwmmc_set_tran_settings()
1468 device_printf(sc->dev, "CS => %d\n", ios->chip_select); in dwmmc_set_tran_settings()
1470 if (cts->ios_valid & MMC_BW) { in dwmmc_set_tran_settings()
1471 ios->bus_width = new_ios->bus_width; in dwmmc_set_tran_settings()
1473 device_printf(sc->dev, "Bus width => %d\n", ios->bus_width); in dwmmc_set_tran_settings()
1475 if (cts->ios_valid & MMC_PM) { in dwmmc_set_tran_settings()
1476 ios->power_mode = new_ios->power_mode; in dwmmc_set_tran_settings()
1478 device_printf(sc->dev, "Power mode => %d\n", ios->power_mode); in dwmmc_set_tran_settings()
1480 if (cts->ios_valid & MMC_BT) { in dwmmc_set_tran_settings()
1481 ios->timing = new_ios->timing; in dwmmc_set_tran_settings()
1483 device_printf(sc->dev, "Timing => %d\n", ios->timing); in dwmmc_set_tran_settings()
1485 if (cts->ios_valid & MMC_BM) { in dwmmc_set_tran_settings()
1486 ios->bus_mode = new_ios->bus_mode; in dwmmc_set_tran_settings()
1488 device_printf(sc->dev, "Bus mode => %d\n", ios->bus_mode); in dwmmc_set_tran_settings()
1490 if (cts->ios_valid & MMC_VCCQ) { in dwmmc_set_tran_settings()
1491 ios->vccq = new_ios->vccq; in dwmmc_set_tran_settings()
1493 device_printf(sc->dev, "VCCQ => %d\n", ios->vccq); in dwmmc_set_tran_settings()
1494 res = dwmmc_switch_vccq(sc->dev, NULL); in dwmmc_set_tran_settings()
1495 device_printf(sc->dev, "VCCQ switch result: %d\n", res); in dwmmc_set_tran_settings()
1498 return (dwmmc_update_ios(sc->dev, NULL)); in dwmmc_set_tran_settings()
1508 mmcio = &ccb->mmcio; in dwmmc_cam_request()
1514 device_printf(sc->dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", in dwmmc_cam_request()
1515 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, in dwmmc_cam_request()
1516 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, in dwmmc_cam_request()
1517 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); in dwmmc_cam_request()
1520 if (mmcio->cmd.data != NULL) { in dwmmc_cam_request()
1521 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) in dwmmc_cam_request()
1522 panic("data->len = %d, data->flags = %d -- something is b0rked", in dwmmc_cam_request()
1523 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); in dwmmc_cam_request()
1525 if (sc->ccb != NULL) { in dwmmc_cam_request()
1526 device_printf(sc->dev, "Controller still has an active command\n"); in dwmmc_cam_request()
1529 sc->ccb = ccb; in dwmmc_cam_request()
1531 dwmmc_request(sc->dev, NULL, NULL); in dwmmc_cam_request()