233 	MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);  in mlx5_fpga_conn_create_mkey()
234 	MLX5_SET(mkc, mkc, lw, 1);  in mlx5_fpga_conn_create_mkey()
235 	MLX5_SET(mkc, mkc, lr, 1);  in mlx5_fpga_conn_create_mkey()
237 	MLX5_SET(mkc, mkc, pd, pdn);  in mlx5_fpga_conn_create_mkey()
238 	MLX5_SET(mkc, mkc, length64, 1);  in mlx5_fpga_conn_create_mkey()
239 	MLX5_SET(mkc, mkc, qpn, 0xffffff);  in mlx5_fpga_conn_create_mkey()
439 	MLX5_SET(cqc, temp_cqc, log_cq_size, ilog2(cq_size));  in mlx5_fpga_conn_create_cq()
467 	MLX5_SET(cqc, cqc, log_cq_size, ilog2(cq_size));  in mlx5_fpga_conn_create_cq()
468 	MLX5_SET(cqc, cqc, c_eqn, eqn);  in mlx5_fpga_conn_create_cq()
469 	MLX5_SET(cqc, cqc, uar_page, fdev->conn_res.uar->index);  in mlx5_fpga_conn_create_cq()
470 	MLX5_SET(cqc, cqc, log_page_size, conn->cq.wq_ctrl.frag_buf.page_shift -  in mlx5_fpga_conn_create_cq()
543 	MLX5_SET(qpc, temp_qpc, log_rq_stride, ilog2(MLX5_SEND_WQE_DS) - 4);  in mlx5_fpga_conn_create_qp()
544 	MLX5_SET(qpc, temp_qpc, log_rq_size, ilog2(conn->qp.rq.size));  in mlx5_fpga_conn_create_qp()
545 	MLX5_SET(qpc, temp_qpc, log_sq_size, ilog2(conn->qp.sq.size));  in mlx5_fpga_conn_create_qp()
574 	MLX5_SET(qpc, qpc, uar_page, fdev->conn_res.uar->index);  in mlx5_fpga_conn_create_qp()
575 	MLX5_SET(qpc, qpc, log_page_size,  in mlx5_fpga_conn_create_qp()
577 	MLX5_SET(qpc, qpc, fre, 1);  in mlx5_fpga_conn_create_qp()
578 	MLX5_SET(qpc, qpc, rlky, 1);  in mlx5_fpga_conn_create_qp()
579 	MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);  in mlx5_fpga_conn_create_qp()
580 	MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);  in mlx5_fpga_conn_create_qp()
581 	MLX5_SET(qpc, qpc, pd, fdev->conn_res.pdn);  in mlx5_fpga_conn_create_qp()
582 	MLX5_SET(qpc, qpc, log_rq_stride, ilog2(MLX5_SEND_WQE_DS) - 4);  in mlx5_fpga_conn_create_qp()
583 	MLX5_SET(qpc, qpc, log_rq_size, ilog2(conn->qp.rq.size));  in mlx5_fpga_conn_create_qp()
584 	MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);  in mlx5_fpga_conn_create_qp()
585 	MLX5_SET(qpc, qpc, log_sq_size, ilog2(conn->qp.sq.size));  in mlx5_fpga_conn_create_qp()
586 	MLX5_SET(qpc, qpc, cqn_snd, conn->cq.mcq.cqn);  in mlx5_fpga_conn_create_qp()
587 	MLX5_SET(qpc, qpc, cqn_rcv, conn->cq.mcq.cqn);  in mlx5_fpga_conn_create_qp()
590 		MLX5_SET(qpc, qpc, user_index, 0xFFFFFF);  in mlx5_fpga_conn_create_qp()
686 	MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);  in mlx5_fpga_conn_init_qp()
687 	MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);  in mlx5_fpga_conn_init_qp()
688 	MLX5_SET(qpc, qpc, primary_address_path.pkey_index, MLX5_FPGA_PKEY_INDEX);  in mlx5_fpga_conn_init_qp()
689 	MLX5_SET(qpc, qpc, primary_address_path.port, MLX5_FPGA_PORT_NUM);  in mlx5_fpga_conn_init_qp()
690 	MLX5_SET(qpc, qpc, pd, conn->fdev->conn_res.pdn);  in mlx5_fpga_conn_init_qp()
691 	MLX5_SET(qpc, qpc, cqn_snd, conn->cq.mcq.cqn);  in mlx5_fpga_conn_init_qp()
692 	MLX5_SET(qpc, qpc, cqn_rcv, conn->cq.mcq.cqn);  in mlx5_fpga_conn_init_qp()
722 	MLX5_SET(qpc, qpc, mtu, MLX5_QPC_MTU_1K_BYTES);  in mlx5_fpga_conn_rtr_qp()
723 	MLX5_SET(qpc, qpc, log_msg_max, (u8)MLX5_CAP_GEN(mdev, log_max_msg));  in mlx5_fpga_conn_rtr_qp()
724 	MLX5_SET(qpc, qpc, remote_qpn, conn->fpga_qpn);  in mlx5_fpga_conn_rtr_qp()
725 	MLX5_SET(qpc, qpc, next_rcv_psn,  in mlx5_fpga_conn_rtr_qp()
727 	MLX5_SET(qpc, qpc, primary_address_path.pkey_index, MLX5_FPGA_PKEY_INDEX);  in mlx5_fpga_conn_rtr_qp()
728 	MLX5_SET(qpc, qpc, primary_address_path.port, MLX5_FPGA_PORT_NUM);  in mlx5_fpga_conn_rtr_qp()
731 	MLX5_SET(qpc, qpc, primary_address_path.udp_sport,  in mlx5_fpga_conn_rtr_qp()
733 	MLX5_SET(qpc, qpc, primary_address_path.src_addr_index,  in mlx5_fpga_conn_rtr_qp()
735 	MLX5_SET(qpc, qpc, primary_address_path.hop_limit, 0);  in mlx5_fpga_conn_rtr_qp()
768 	MLX5_SET(qpc, qpc, log_ack_req_freq, 8);  in mlx5_fpga_conn_rts_qp()
769 	MLX5_SET(qpc, qpc, min_rnr_nak, 0x12);  in mlx5_fpga_conn_rts_qp()
770 	MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 0x12); /* ~1.07s */  in mlx5_fpga_conn_rts_qp()
771 	MLX5_SET(qpc, qpc, next_send_psn,  in mlx5_fpga_conn_rts_qp()
773 	MLX5_SET(qpc, qpc, retry_count, 7);  in mlx5_fpga_conn_rts_qp()
774 	MLX5_SET(qpc, qpc, rnr_retry, 7); /* Infinite retry if RNR NACK */  in mlx5_fpga_conn_rts_qp()
794 	MLX5_SET(fpga_qpc, conn->fpga_qpc, state, MLX5_FPGA_QPC_STATE_ACTIVE);  in mlx5_fpga_conn_connect()
834 	MLX5_SET(fpga_qpc, conn->fpga_qpc, state, MLX5_FPGA_QPC_STATE_INIT);  in mlx5_fpga_conn_connect()
917 	MLX5_SET(fpga_qpc, conn->fpga_qpc, state, MLX5_FPGA_QPC_STATE_INIT);  in mlx5_fpga_conn_create()
918 	MLX5_SET(fpga_qpc, conn->fpga_qpc, qp_type, qp_type);  in mlx5_fpga_conn_create()
919 	MLX5_SET(fpga_qpc, conn->fpga_qpc, st, MLX5_FPGA_QPC_ST_RC);  in mlx5_fpga_conn_create()
920 	MLX5_SET(fpga_qpc, conn->fpga_qpc, ether_type, ETH_P_8021Q);  in mlx5_fpga_conn_create()
921 	MLX5_SET(fpga_qpc, conn->fpga_qpc, vid, 0);  in mlx5_fpga_conn_create()
922 	MLX5_SET(fpga_qpc, conn->fpga_qpc, next_rcv_psn, 1);  in mlx5_fpga_conn_create()
923 	MLX5_SET(fpga_qpc, conn->fpga_qpc, next_send_psn, 0);  in mlx5_fpga_conn_create()
924 	MLX5_SET(fpga_qpc, conn->fpga_qpc, pkey, MLX5_FPGA_PKEY);  in mlx5_fpga_conn_create()
925 	MLX5_SET(fpga_qpc, conn->fpga_qpc, remote_qpn, conn->qp.mqp.qpn);  in mlx5_fpga_conn_create()
926 	MLX5_SET(fpga_qpc, conn->fpga_qpc, rnr_retry, 7);  in mlx5_fpga_conn_create()
927 	MLX5_SET(fpga_qpc, conn->fpga_qpc, retry_count, 7);  in mlx5_fpga_conn_create()