46 	u32 in[MLX5_FPGA_ACCESS_REG_SZ] = {0};  in mlx5_fpga_access_reg()  local
57 	MLX5_SET(fpga_access_reg, in, size, size);  in mlx5_fpga_access_reg()
58 	MLX5_SET64(fpga_access_reg, in, address, addr);  in mlx5_fpga_access_reg()
60 		memcpy(MLX5_ADDR_OF(fpga_access_reg, in, data), buf, size);  in mlx5_fpga_access_reg()
62 	err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),  in mlx5_fpga_access_reg()
75 	u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};  in mlx5_fpga_caps()  local
77 	return mlx5_core_access_reg(dev, in, sizeof(in), dev->caps.fpga,  in mlx5_fpga_caps()
84 	u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};  in mlx5_fpga_ctrl_op()  local
87 	MLX5_SET(fpga_ctrl, in, operation, op);  in mlx5_fpga_ctrl_op()
89 	return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),  in mlx5_fpga_ctrl_op()
128 	u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};  in mlx5_fpga_ctrl_write()  local
131 	MLX5_SET(fpga_ctrl, in, operation, op);  in mlx5_fpga_ctrl_write()
132 	MLX5_SET(fpga_ctrl, in, flash_select_admin, image);  in mlx5_fpga_ctrl_write()
134 	return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),  in mlx5_fpga_ctrl_write()
151 	u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};  in mlx5_fpga_query()  local
155 	err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),  in mlx5_fpga_query()
169 	u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};  in mlx5_fpga_ctrl_connect()  local
175 		err = mlx5_core_access_reg(dev, in, sizeof(in), out,  in mlx5_fpga_ctrl_connect()
185 		MLX5_SET(fpga_ctrl, in, operation, *connect);  in mlx5_fpga_ctrl_connect()
186 		err = mlx5_core_access_reg(dev, in, sizeof(in), out,  in mlx5_fpga_ctrl_connect()
196 	u32 in[MLX5_ST_SZ_DW(mtmp_reg)] = {0};  in mlx5_fpga_query_mtmp()  local
200 	MLX5_SET(mtmp_reg, in, sensor_index, temp->index);  in mlx5_fpga_query_mtmp()
201 	MLX5_SET(mtmp_reg, in, i,  in mlx5_fpga_query_mtmp()
205 	err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),  in mlx5_fpga_query_mtmp()
228 	u32 in[MLX5_ST_SZ_DW(fpga_create_qp_in)] = {0};  in mlx5_fpga_create_qp()  local
232 	MLX5_SET(fpga_create_qp_in, in, opcode, MLX5_CMD_OP_FPGA_CREATE_QP);  in mlx5_fpga_create_qp()
233 	memcpy(MLX5_ADDR_OF(fpga_create_qp_in, in, fpga_qpc), fpga_qpc,  in mlx5_fpga_create_qp()
236 	ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));  in mlx5_fpga_create_qp()
250 	u32 in[MLX5_ST_SZ_DW(fpga_modify_qp_in)] = {0};  in mlx5_fpga_modify_qp()  local
253 	MLX5_SET(fpga_modify_qp_in, in, opcode, MLX5_CMD_OP_FPGA_MODIFY_QP);  in mlx5_fpga_modify_qp()
254 	MLX5_SET(fpga_modify_qp_in, in, field_select, fields);  in mlx5_fpga_modify_qp()
255 	MLX5_SET(fpga_modify_qp_in, in, fpga_qpn, fpga_qpn);  in mlx5_fpga_modify_qp()
256 	memcpy(MLX5_ADDR_OF(fpga_modify_qp_in, in, fpga_qpc), fpga_qpc,  in mlx5_fpga_modify_qp()
259 	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));  in mlx5_fpga_modify_qp()
265 	u32 in[MLX5_ST_SZ_DW(fpga_query_qp_in)] = {0};  in mlx5_fpga_query_qp()  local
269 	MLX5_SET(fpga_query_qp_in, in, opcode, MLX5_CMD_OP_FPGA_QUERY_QP);  in mlx5_fpga_query_qp()
270 	MLX5_SET(fpga_query_qp_in, in, fpga_qpn, fpga_qpn);  in mlx5_fpga_query_qp()
272 	ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));  in mlx5_fpga_query_qp()
283 	u32 in[MLX5_ST_SZ_DW(fpga_destroy_qp_in)] = {0};  in mlx5_fpga_destroy_qp()  local
286 	MLX5_SET(fpga_destroy_qp_in, in, opcode, MLX5_CMD_OP_FPGA_DESTROY_QP);  in mlx5_fpga_destroy_qp()
287 	MLX5_SET(fpga_destroy_qp_in, in, fpga_qpn, fpga_qpn);  in mlx5_fpga_destroy_qp()
289 	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));  in mlx5_fpga_destroy_qp()
295 	u32 in[MLX5_ST_SZ_DW(fpga_query_qp_counters_in)] = {0};  in mlx5_fpga_query_qp_counters()  local
299 	MLX5_SET(fpga_query_qp_counters_in, in, opcode,  in mlx5_fpga_query_qp_counters()
301 	MLX5_SET(fpga_query_qp_counters_in, in, clear, clear);  in mlx5_fpga_query_qp_counters()
302 	MLX5_SET(fpga_query_qp_counters_in, in, fpga_qpn, fpga_qpn);  in mlx5_fpga_query_qp_counters()
304 	ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));  in mlx5_fpga_query_qp_counters()
325 	u32 in[MLX5_ST_SZ_DW(fpga_shell_counters)] = {0};  in mlx5_fpga_shell_counters()  local
329 	MLX5_SET(fpga_shell_counters, in, clear, clear);  in mlx5_fpga_shell_counters()
330 	err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),  in mlx5_fpga_shell_counters()