Lines Matching +full:0 +full:x18
37 MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX = 0x2c9,
41 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_EXAMPLE = 0x1,
42 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC = 0x2,
43 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_TLS = 0x3,
47 MLX5_FPGA_SHELL_CAPS_QP_TYPE_SHELL_QP = 0x1,
48 MLX5_FPGA_SHELL_CAPS_QP_TYPE_SANDBOX_QP = 0x2,
52 u8 max_num_qps[0x10];
53 u8 reserved_at_10[0x8];
54 u8 total_rcv_credits[0x8];
56 u8 reserved_at_20[0xe];
57 u8 qp_type[0x2];
58 u8 reserved_at_30[0x5];
59 u8 rae[0x1];
60 u8 rwe[0x1];
61 u8 rre[0x1];
62 u8 reserved_at_38[0x4];
63 u8 dc[0x1];
64 u8 ud[0x1];
65 u8 uc[0x1];
66 u8 rc[0x1];
68 u8 reserved_at_40[0x1a];
69 u8 log_ddr_size[0x6];
71 u8 max_fpga_qp_msg_size[0x20];
73 u8 reserved_at_80[0x180];
77 u8 fpga_id[0x8];
78 u8 fpga_device[0x18];
80 u8 register_file_ver[0x20];
82 u8 fpga_ctrl_modify[0x1];
83 u8 reserved_at_41[0x5];
84 u8 access_reg_query_mode[0x2];
85 u8 reserved_at_48[0x6];
86 u8 access_reg_modify_mode[0x2];
87 u8 reserved_at_50[0x10];
89 u8 reserved_at_60[0x20];
91 u8 image_version[0x20];
93 u8 image_date[0x20];
95 u8 image_time[0x20];
97 u8 shell_version[0x20];
99 u8 reserved_at_100[0x80];
103 u8 reserved_at_380[0x8];
104 u8 ieee_vendor_id[0x18];
106 u8 sandbox_product_version[0x10];
107 u8 sandbox_product_id[0x10];
109 u8 sandbox_basic_caps[0x20];
111 u8 reserved_at_3e0[0x10];
112 u8 sandbox_extended_caps_len[0x10];
114 u8 sandbox_extended_caps_addr[0x40];
116 u8 fpga_ddr_start_addr[0x40];
118 u8 fpga_cr_space_start_addr[0x40];
120 u8 fpga_ddr_size[0x20];
122 u8 fpga_cr_space_size[0x20];
124 u8 reserved_at_500[0x300];
128 MLX5_FPGA_CTRL_OPERATION_LOAD = 0x1,
129 MLX5_FPGA_CTRL_OPERATION_RESET = 0x2,
130 MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT = 0x3,
131 MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON = 0x4,
132 MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF = 0x5,
133 MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX = 0x6,
134 MLX5_FPGA_CTRL_OPERATION_DISCONNECT = 0x9,
135 MLX5_FPGA_CTRL_OPERATION_CONNECT = 0xA,
136 MLX5_FPGA_CTRL_OPERATION_RELOAD = 0xB,
140 u8 reserved_at_0[0x8];
141 u8 operation[0x8];
142 u8 reserved_at_10[0x8];
143 u8 status[0x8];
145 u8 reserved_at_20[0x8];
146 u8 flash_select_admin[0x8];
147 u8 reserved_at_30[0x8];
148 u8 flash_select_oper[0x8];
150 u8 reserved_at_40[0x40];
154 MLX5_FPGA_ERROR_EVENT_SYNDROME_CORRUPTED_DDR = 0x1,
155 MLX5_FPGA_ERROR_EVENT_SYNDROME_FLASH_TIMEOUT = 0x2,
156 MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR = 0x3,
157 MLX5_FPGA_ERROR_EVENT_SYNDROME_WATCHDOG_FAILURE = 0x4,
158 MLX5_FPGA_ERROR_EVENT_SYNDROME_I2C_FAILURE = 0x5,
159 MLX5_FPGA_ERROR_EVENT_SYNDROME_IMAGE_CHANGED = 0x6,
160 MLX5_FPGA_ERROR_EVENT_SYNDROME_TEMPERATURE_CRITICAL = 0x7,
164 u8 reserved_at_0[0x40];
166 u8 reserved_at_40[0x18];
167 u8 syndrome[0x8];
169 u8 reserved_at_60[0x80];
175 u8 reserved_at_0[0x20];
177 u8 reserved_at_20[0x10];
178 u8 size[0x10];
180 u8 address[0x40];
182 u8 data[0][0x8];
186 MLX5_FPGA_QPC_STATE_INIT = 0x0,
187 MLX5_FPGA_QPC_STATE_ACTIVE = 0x1,
188 MLX5_FPGA_QPC_STATE_ERROR = 0x2,
192 MLX5_FPGA_QPC_QP_TYPE_SHELL_QP = 0x0,
193 MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP = 0x1,
197 MLX5_FPGA_QPC_ST_RC = 0x0,
201 u8 state[0x4];
202 u8 reserved_at_4[0x1b];
203 u8 qp_type[0x1];
205 u8 reserved_at_20[0x4];
206 u8 st[0x4];
207 u8 reserved_at_28[0x10];
208 u8 traffic_class[0x8];
210 u8 ether_type[0x10];
211 u8 prio[0x3];
212 u8 dei[0x1];
213 u8 vid[0xc];
215 u8 reserved_at_60[0x20];
217 u8 reserved_at_80[0x8];
218 u8 next_rcv_psn[0x18];
220 u8 reserved_at_a0[0x8];
221 u8 next_send_psn[0x18];
223 u8 reserved_at_c0[0x10];
224 u8 pkey[0x10];
226 u8 reserved_at_e0[0x8];
227 u8 remote_qpn[0x18];
229 u8 reserved_at_100[0x15];
230 u8 rnr_retry[0x3];
231 u8 reserved_at_118[0x5];
232 u8 retry_count[0x3];
234 u8 reserved_at_120[0x20];
236 u8 reserved_at_140[0x10];
237 u8 remote_mac_47_32[0x10];
239 u8 remote_mac_31_0[0x20];
241 u8 remote_ip[16][0x8];
243 u8 reserved_at_200[0x40];
245 u8 reserved_at_240[0x10];
246 u8 fpga_mac_47_32[0x10];
248 u8 fpga_mac_31_0[0x20];
250 u8 fpga_ip[16][0x8];
254 u8 opcode[0x10];
255 u8 reserved_at_10[0x10];
257 u8 reserved_at_20[0x10];
258 u8 op_mod[0x10];
260 u8 reserved_at_40[0x40];
266 u8 status[0x8];
267 u8 reserved_at_8[0x18];
269 u8 syndrome[0x20];
271 u8 reserved_at_40[0x8];
272 u8 fpga_qpn[0x18];
274 u8 reserved_at_60[0x20];
280 u8 opcode[0x10];
281 u8 reserved_at_10[0x10];
283 u8 reserved_at_20[0x10];
284 u8 op_mod[0x10];
286 u8 reserved_at_40[0x8];
287 u8 fpga_qpn[0x18];
289 u8 field_select[0x20];
295 u8 status[0x8];
296 u8 reserved_at_8[0x18];
298 u8 syndrome[0x20];
300 u8 reserved_at_40[0x40];
304 u8 opcode[0x10];
305 u8 reserved_at_10[0x10];
307 u8 reserved_at_20[0x10];
308 u8 op_mod[0x10];
310 u8 reserved_at_40[0x8];
311 u8 fpga_qpn[0x18];
313 u8 reserved_at_60[0x20];
317 u8 status[0x8];
318 u8 reserved_at_8[0x18];
320 u8 syndrome[0x20];
322 u8 reserved_at_40[0x40];
328 u8 opcode[0x10];
329 u8 reserved_at_10[0x10];
331 u8 reserved_at_20[0x10];
332 u8 op_mod[0x10];
334 u8 clear[0x1];
335 u8 reserved_at_41[0x7];
336 u8 fpga_qpn[0x18];
338 u8 reserved_at_60[0x20];
342 u8 status[0x8];
343 u8 reserved_at_8[0x18];
345 u8 syndrome[0x20];
347 u8 reserved_at_40[0x40];
349 u8 rx_ack_packets[0x40];
351 u8 rx_send_packets[0x40];
353 u8 tx_ack_packets[0x40];
355 u8 tx_send_packets[0x40];
357 u8 rx_total_drop[0x40];
359 u8 reserved_at_1c0[0x1c0];
363 u8 opcode[0x10];
364 u8 reserved_at_10[0x10];
366 u8 reserved_at_20[0x10];
367 u8 op_mod[0x10];
369 u8 reserved_at_40[0x8];
370 u8 fpga_qpn[0x18];
372 u8 reserved_at_60[0x20];
376 u8 status[0x8];
377 u8 reserved_at_8[0x18];
379 u8 syndrome[0x20];
381 u8 reserved_at_40[0x40];
385 u8 encapsulation[0x20];
387 u8 reserved_0[0x15];
388 u8 ipv4_fragment[0x1];
389 u8 ipv6[0x1];
390 u8 esn[0x1];
391 u8 lso[0x1];
392 u8 transport_and_tunnel_mode[0x1];
393 u8 tunnel_mode[0x1];
394 u8 transport_mode[0x1];
395 u8 ah_esp[0x1];
396 u8 esp[0x1];
397 u8 ah[0x1];
398 u8 ipv4_options[0x1];
400 u8 auth_alg[0x20];
402 u8 enc_alg[0x20];
404 u8 sa_cap[0x20];
406 u8 reserved_1[0x10];
407 u8 number_of_ipsec_counters[0x10];
409 u8 ipsec_counters_addr_low[0x20];
410 u8 ipsec_counters_addr_high[0x20];
414 u8 dec_in_packets[0x40];
416 u8 dec_out_packets[0x40];
418 u8 dec_bypass_packets[0x40];
420 u8 enc_in_packets[0x40];
422 u8 enc_out_packets[0x40];
424 u8 enc_bypass_packets[0x40];
426 u8 drop_dec_packets[0x40];
428 u8 failed_auth_dec_packets[0x40];
430 u8 drop_enc_packets[0x40];
432 u8 success_add_sa[0x40];
434 u8 fail_add_sa[0x40];
436 u8 success_delete_sa[0x40];
438 u8 fail_delete_sa[0x40];
440 u8 dropped_cmd[0x40];
444 u8 reserved_0[0x20];
446 u8 clear[0x1];
447 u8 reserved_1[0x1f];
449 u8 reserved_2[0x40];
451 u8 ddr_read_requests[0x40];
453 u8 ddr_write_requests[0x40];
455 u8 ddr_read_bytes[0x40];
457 u8 ddr_write_bytes[0x40];
459 u8 reserved_3[0x200];
463 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_READ = 0x0,
464 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_WRITE = 0x1,
465 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_READ_RESPONSE = 0x2,
466 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_WRITE_RESPONSE = 0x3,
470 u8 version[0x4];
471 u8 syndrome[0x4];
472 u8 reserved_at_8[0x4];
473 u8 type[0x4];
474 u8 reserved_at_10[0x8];
475 u8 tid[0x8];
477 u8 len[0x20];
479 u8 address[0x40];
481 u8 data[0][0x8];
485 MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RETRY_COUNTER_EXPIRED = 0x1,
486 MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RNR_EXPIRED = 0x2,
490 u8 reserved_0[0x40];
492 u8 reserved_1[0x18];
493 u8 syndrome[0x8];
495 u8 reserved_2[0x60];
497 u8 reserved_3[0x8];
498 u8 fpga_qpn[0x18];