Lines Matching refs:eth
397 wqe->eth.swp_outer_l3_offset = eth_hdr_len / 2;
398 wqe->eth.cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
405 wqe->eth.swp_outer_l4_offset = eth_hdr_len / 2;
406 wqe->eth.swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L4_TYPE;
417 wqe->eth.swp_outer_l3_offset = eth_hdr_len / 2;
418 wqe->eth.cs_flags = MLX5_ETH_WQE_L4_CSUM;
424 wqe->eth.swp_outer_l4_offset = eth_hdr_len / 2;
425 wqe->eth.swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L4_TYPE |
466 wqe->eth.swp_inner_l3_offset = eth_hdr_len / 2;
467 wqe->eth.cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM;
477 wqe->eth.swp_inner_l3_offset = eth_hdr_len / 2;
478 wqe->eth.swp_flags |= MLX5_ETH_WQE_SWP_INNER_L3_TYPE;
499 wqe->eth.swp_inner_l4_offset = (eth_hdr_len / 2);
500 wqe->eth.cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
501 wqe->eth.swp_flags |= MLX5_ETH_WQE_SWP_INNER_L4_TYPE;
509 wqe->eth.swp_inner_l4_offset = eth_hdr_len / 2;
510 wqe->eth.cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
523 wqe->eth.swp_outer_l3_offset += ETHER_VLAN_ENCAP_LEN / 2;
524 wqe->eth.swp_outer_l4_offset += ETHER_VLAN_ENCAP_LEN / 2;
525 wqe->eth.swp_inner_l3_offset += ETHER_VLAN_ENCAP_LEN / 2;
526 wqe->eth.swp_inner_l4_offset += ETHER_VLAN_ENCAP_LEN / 2;
533 if (wqe->eth.cs_flags & (MLX5_ETH_WQE_L3_INNER_CSUM |
535 wqe->eth.cs_flags &= ~MLX5_ETH_WQE_L4_CSUM;
755 wqe->eth.cs_flags |= MLX5_ETH_WQE_L3_CSUM;
758 wqe->eth.cs_flags |= MLX5_ETH_WQE_L4_CSUM;
760 if (wqe->eth.cs_flags == 0) {
768 wqe->eth.mss = cpu_to_be16(mss);
794 wqe->eth.mss = cpu_to_be16(mss);
875 wqe->eth.vlan_cmd = htons(0x8000); /* bit 0 CVLAN */
876 wqe->eth.vlan_hdr = htons(mb->m_pkthdr.ether_vtag);
897 wqe->eth.inline_hdr_start;
921 wqe->eth.inline_hdr_sz = cpu_to_be16(args.ihs);
932 m_copydata(mb, 0, args.ihs, wqe->eth.inline_hdr_start);
934 wqe->eth.inline_hdr_sz = cpu_to_be16(args.ihs);
938 if (args.ihs > sizeof(wqe->eth.inline_hdr_start)) {
939 ds_cnt += DIV_ROUND_UP(args.ihs - sizeof(wqe->eth.inline_hdr_start),