Lines Matching defs:wqe

58 	struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi);
60 memset(&wqe->ctrl, 0, sizeof(wqe->ctrl));
62 wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);
63 wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
65 wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
67 wqe->ctrl.fm_ce_se = 0;
70 memcpy(sq->doorbell.d32, &wqe->ctrl, sizeof(sq->doorbell.d32));
353 mlx5e_get_vxlan_header_size(const struct mbuf *mb, struct mlx5e_tx_wqe *wqe,
397 wqe->eth.swp_outer_l3_offset = eth_hdr_len / 2;
398 wqe->eth.cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
405 wqe->eth.swp_outer_l4_offset = eth_hdr_len / 2;
406 wqe->eth.swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L4_TYPE;
417 wqe->eth.swp_outer_l3_offset = eth_hdr_len / 2;
418 wqe->eth.cs_flags = MLX5_ETH_WQE_L4_CSUM;
424 wqe->eth.swp_outer_l4_offset = eth_hdr_len / 2;
425 wqe->eth.swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L4_TYPE |
466 wqe->eth.swp_inner_l3_offset = eth_hdr_len / 2;
467 wqe->eth.cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM;
477 wqe->eth.swp_inner_l3_offset = eth_hdr_len / 2;
478 wqe->eth.swp_flags |= MLX5_ETH_WQE_SWP_INNER_L3_TYPE;
499 wqe->eth.swp_inner_l4_offset = (eth_hdr_len / 2);
500 wqe->eth.cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
501 wqe->eth.swp_flags |= MLX5_ETH_WQE_SWP_INNER_L4_TYPE;
509 wqe->eth.swp_inner_l4_offset = eth_hdr_len / 2;
510 wqe->eth.cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
523 wqe->eth.swp_outer_l3_offset += ETHER_VLAN_ENCAP_LEN / 2;
524 wqe->eth.swp_outer_l4_offset += ETHER_VLAN_ENCAP_LEN / 2;
525 wqe->eth.swp_inner_l3_offset += ETHER_VLAN_ENCAP_LEN / 2;
526 wqe->eth.swp_inner_l4_offset += ETHER_VLAN_ENCAP_LEN / 2;
533 if (wqe->eth.cs_flags & (MLX5_ETH_WQE_L3_INNER_CSUM |
535 wqe->eth.cs_flags &= ~MLX5_ETH_WQE_L4_CSUM;
551 struct mlx5_wqe_dump_seg *wqe;
619 wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi);
630 memset(&wqe->ctrl, 0, sizeof(wqe->ctrl));
633 wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
634 wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
635 wqe->ctrl.imm = cpu_to_be32(parg->tisn << 8);
638 wqe->data.addr = cpu_to_be64((uint64_t)segs[x].ds_addr + off);
639 wqe->data.lkey = sq->mkey_be;
640 wqe->data.byte_count = cpu_to_be32(len);
643 if (unlikely(wqe == wqe_last))
644 wqe = mlx5_wq_cyc_get_wqe(&sq->wq, 0);
646 wqe++;
653 wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi);
657 wqe->ctrl.fm_ce_se |= MLX5_FENCE_MODE_INITIATOR_SMALL;
690 struct mlx5e_tx_wqe *wqe;
740 wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi);
743 memset(wqe, 0, sizeof(*wqe));
748 mlx5e_accel_ipsec_handle_tx(mb, wqe);
755 wqe->eth.cs_flags |= MLX5_ETH_WQE_L3_CSUM;
758 wqe->eth.cs_flags |= MLX5_ETH_WQE_L4_CSUM;
760 if (wqe->eth.cs_flags == 0) {
768 wqe->eth.mss = cpu_to_be16(mss);
794 wqe->eth.mss = cpu_to_be16(mss);
798 args.ihs = mlx5e_get_vxlan_header_size(mb, wqe,
844 args.ihs = mlx5e_get_vxlan_header_size(mb, wqe,
875 wqe->eth.vlan_cmd = htons(0x8000); /* bit 0 CVLAN */
876 wqe->eth.vlan_hdr = htons(mb->m_pkthdr.ether_vtag);
897 wqe->eth.inline_hdr_start;
921 wqe->eth.inline_hdr_sz = cpu_to_be16(args.ihs);
932 m_copydata(mb, 0, args.ihs, wqe->eth.inline_hdr_start);
934 wqe->eth.inline_hdr_sz = cpu_to_be16(args.ihs);
937 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
938 if (args.ihs > sizeof(wqe->eth.inline_hdr_start)) {
939 ds_cnt += DIV_ROUND_UP(args.ihs - sizeof(wqe->eth.inline_hdr_start),
942 dseg = ((struct mlx5_wqe_data_seg *)&wqe->ctrl) + ds_cnt;
983 ds_cnt = (dseg - ((struct mlx5_wqe_data_seg *)&wqe->ctrl));
985 wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
986 wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
987 wqe->ctrl.imm = cpu_to_be32(args.tisn << 8);
990 wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
992 wqe->ctrl.fm_ce_se = 0;
995 memcpy(sq->doorbell.d32, &wqe->ctrl, sizeof(sq->doorbell.d32));