Lines Matching +full:per +full:- +full:lane
1 /*-
2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved.
110 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
129 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \
130 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \
133 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \
134 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */
140 memset(&(ptr)->field, 0, \
141 sizeof(*(ptr)) - __offsetof(__typeof(*(ptr)), field))
152 __func__, __LINE__, curthread->td_proc->p_pid, \
157 __func__, __LINE__, curthread->td_proc->p_pid, \
162 __func__, __LINE__, curthread->td_proc->p_pid, \
312 "Total number of corrected bits for lane 0") \
314 "Total number of corrected bits for lane 1") \
316 "Total number of corrected bits for lane 2") \
318 "Total number of corrected bits for lane 3")
327 "Indicates the number of PRBS errors on lane 0") \
329 "Indicates the number of PRBS errors on lane 1") \
331 "Indicates the number of PRBS errors on lane 2") \
333 "Indicates the number of PRBS errors on lane 3") \
335 "FEC correctable block counter lane 0") \
337 "FEC correctable block counter lane 1") \
339 "FEC correctable block counter lane 2") \
341 "FEC correctable block counter lane 3") \
347 "The number of RS-FEC blocks received that had no errors") \
349 "The number of corrected RS-FEC blocks received that had" \
354 "FEC corrected symbol counter lane 0") \
356 "FEC corrected symbol counter lane 1") \
358 "FEC corrected symbol counter lane 2") \
360 "FEC corrected symbol counter lane 3")
362 /* Per priority statistics for PFC */
389 m(c, t, pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d)
439 "outbound non-posted read requests but could not perform the " \
440 "operation due to insufficient non-posted credits.", \
510 "Number of non-Fatal error msg sent.", pcie_timers_states) \
516 "Error counter for PCI lane 0", pcie_lanes_counters) \
518 "Error counter for PCI lane 1", pcie_lanes_counters) \
520 "Error counter for PCI lane 2", pcie_lanes_counters) \
522 "Error counter for PCI lane 3", pcie_lanes_counters) \
524 "Error counter for PCI lane 4", pcie_lanes_counters) \
526 "Error counter for PCI lane 5", pcie_lanes_counters) \
528 "Error counter for PCI lane 6", pcie_lanes_counters) \
530 "Error counter for PCI lane 7", pcie_lanes_counters) \
532 "Error counter for PCI lane 8", pcie_lanes_counters) \
534 "Error counter for PCI lane 9", pcie_lanes_counters) \
536 "Error counter for PCI lane 10", pcie_lanes_counters) \
538 "Error counter for PCI lane 11", pcie_lanes_counters) \
540 "Error counter for PCI lane 12", pcie_lanes_counters) \
542 "Error counter for PCI lane 13", pcie_lanes_counters) \
544 "Error counter for PCI lane 14", pcie_lanes_counters) \
546 "Error counter for PCI lane 15", pcie_lanes_counters)
714 …m(+1, s64, irq_cpu_base, "irq_cpu_base", "-1: Don't bind IRQ 0..NCPU-1: select this base CPU when …
715 …m(+1, s64, irq_cpu_stride, "irq_cpu_stride", "0..NCPU-1: Distance between IRQ vectors when binding…
738 /* data path - accessed per cqe */
741 /* data path - accessed per HW polling */
819 /* pointers to per request info: write@xmit, read@completion */
877 /* pointers to per packet info: write@xmit, read@completion */
902 u16 cc = sq->cc; in mlx5e_sq_has_room_for()
903 u16 pc = sq->pc; in mlx5e_sq_has_room_for()
905 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); in mlx5e_sq_has_room_for()
917 cc = sq->cc; in mlx5e_sq_queue_level()
918 pc = sq->pc; in mlx5e_sq_queue_level()
920 return (((sq->wq.sz_m1 & (pc - cc)) * in mlx5e_sq_queue_level()
921 IF_SND_QUEUE_LEVEL_MAX) / sq->wq.sz_m1); in mlx5e_sq_queue_level()
961 /* flow table rule per traffic type */
1078 /* priv data path fields - start */
1083 /* priv data path fields - end */
1087 #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock)
1088 #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock)
1089 #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock)
1090 #define PRIV_ASSERT_LOCKED(priv) sx_assert(&(priv)->state_lock, SA_XLOCKED)
1200 #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL)
1240 if (unlikely((force == false && sq->db_inhibit != 0) || sq->doorbell.d64 == 0)) { in mlx5e_tx_notify_hw()
1248 *sq->wq.db = cpu_to_be32(sq->pc); in mlx5e_tx_notify_hw()
1256 mlx5_write64(sq->doorbell.d32, sq->uar_map, in mlx5e_tx_notify_hw()
1257 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); in mlx5e_tx_notify_hw()
1259 sq->doorbell.d64 = 0; in mlx5e_tx_notify_hw()
1267 mcq = &cq->mcq; in mlx5e_cq_arm()
1268 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); in mlx5e_cq_arm()
1271 #define mlx5e_dbg(_IGN, _priv, ...) mlx5_core_dbg((_priv)->mdev, __VA_ARGS__)