Lines Matching +full:gpio +full:- +full:7 +full:- +full:segment
1 /*-
2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
48 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
53 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf…
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1…
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
57 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
184 MLX5_PCI_CMD_XPORT = 7,
224 MLX5_PERM_UMR_EN = 1 << 7,
256 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
270 MLX5_MKEY_MASK_PD = 1ull << 7,
291 MLX5_UMR_INLINE = (1 << 7),
295 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
310 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
442 * - ctrl segment (16 bytes)
443 * - rdma segment (16 bytes)
444 * - scatter elements (16 bytes each)
446 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
525 u8 reserved1[7];
634 __be32 raw[7];
640 struct mlx5_eqe_gpio gpio; member
658 __be32 rsvd2[7];
736 return (cqe->op_own >> 4); in get_cqe_opcode()
741 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1; in get_cqe_lro_timestamp_valid()
746 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; in get_cqe_lro_tcppsh()
751 return (cqe->l4_hdr_type_etc >> 4) & 0x7; in get_cqe_l4_hdr_type()
756 return be16_to_cpu(cqe->vlan_info) & 0xfff; in get_cqe_vlan()
761 memcpy(smac, &cqe->rss_hash_type , 4); in get_cqe_smac()
762 memcpy(smac + 4, &cqe->slid , 2); in get_cqe_smac()
767 return cqe->l4_hdr_type_etc & 0x1; in cqe_has_vlan()
772 return cqe->tls_outer_l3_tunneled & 0x1; in cqe_is_tunneled()
777 return (cqe->tls_outer_l3_tunneled >> 3) & 0x3; in get_cqe_tls_offload()
870 /* This is a two bit field occupying bits 31-30.
949 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7,
1051 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1054 MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1057 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1060 MLX5_GET(cmd_hca_cap_2, mdev->hca_caps_cur[MLX5_CAP_GENERAL_2], cap)
1064 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1068 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1071 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1074 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1077 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1080 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1083 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1086 MLX5_GET64(flow_table_nic_cap, (mdev)->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1089 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1129 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1133 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1161 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1165 (mdev)->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1169 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1173 mdev->hca_caps_cur[MLX5_CAP_PORT_SELECTION], cap)
1177 mdev->hca_caps_max[MLX5_CAP_PORT_SELECTION], cap)
1181 mdev->hca_caps_cur[MLX5_CAP_ADV_VIRTUALIZATION], cap)
1185 mdev->hca_caps_max[MLX5_CAP_ADV_VIRTUALIZATION], cap)
1194 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1197 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1201 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1205 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1209 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1213 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1217 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1221 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1225 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1229 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1232 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1235 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1238 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1241 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1244 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1247 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1250 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1253 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1256 MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap)
1259 MLX5_ADDR_OF(device_event_cap, (mdev)->hca_caps_cur[MLX5_CAP_DEV_EVENT], cap)
1262 MLX5_GET(ipsec_cap, (mdev)->hca_caps_cur[MLX5_CAP_IPSEC], cap)
1393 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2; in mlx5_get_cqe_format()