1021 	/* NUM OF CAP Types */
1050 #define MLX5_CAP_GEN(mdev, cap) \  argument
1051 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1053 #define	MLX5_CAP_GEN_64(mdev, cap)					\  argument
1054 	MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1056 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1057 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1059 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1060 	MLX5_GET(cmd_hca_cap_2, mdev->hca_caps_cur[MLX5_CAP_GENERAL_2], cap)
1062 #define MLX5_CAP_ETH(mdev, cap) \  argument
1064 		 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1066 #define MLX5_CAP_ETH_MAX(mdev, cap) \  argument
1068 		 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1070 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1071 	MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1073 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1074 	MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1076 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1077 	MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1079 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1080 	MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1082 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1083 	MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1085 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1086 	MLX5_GET64(flow_table_nic_cap, (mdev)->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1088 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \  argument
1089 	MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1091 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1092 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1094 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \  argument
1095 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1097 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1098                 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1100 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \  argument
1101         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1103 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1104         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1106 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \  argument
1107         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1109 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1110         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1112 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \  argument
1113         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1115 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1116         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1118 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \  argument
1119         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap)
1121 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1122         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1124 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \  argument
1125         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap)
1127 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1129 		 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1131 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \  argument
1133 		 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1135 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1136 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1138 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \  argument
1139 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1141 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1142 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1144 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \  argument
1145 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1147 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1148 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1150 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \  argument
1151 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1153 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1154         MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap)
1156 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2_MAX(mdev, cap) \  argument
1157         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, ft_field_support_2_esw_fdb.cap)
1159 #define MLX5_CAP_ESW(mdev, cap) \  argument
1161 		 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1163 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1165 		   (mdev)->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1167 #define MLX5_CAP_ESW_MAX(mdev, cap) \  argument
1169 		 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1171 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \  argument
1173 		 mdev->hca_caps_cur[MLX5_CAP_PORT_SELECTION], cap)
1175 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \  argument
1177 		 mdev->hca_caps_max[MLX5_CAP_PORT_SELECTION], cap)
1179 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \  argument
1181 		 mdev->hca_caps_cur[MLX5_CAP_ADV_VIRTUALIZATION], cap)
1183 #define MLX5_CAP_ADV_VIRTUALIZATION_MAX(mdev, cap) \  argument
1185 		 mdev->hca_caps_max[MLX5_CAP_ADV_VIRTUALIZATION], cap)
1187 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \  argument
1188 	MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1190 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION_MAX(mdev, cap) \  argument
1191 	MLX5_CAP_PORT_SELECTION_MAX(mdev, flow_table_properties_port_selection.cap)
1193 #define MLX5_CAP_ODP(mdev, cap)\  argument
1194 	MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1196 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1197 	MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1199 #define MLX5_CAP_SNAPSHOT(mdev, cap) \  argument
1201 		 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1203 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \  argument
1205 		 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1207 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \  argument
1209 		 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1211 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \  argument
1213 		 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1215 #define MLX5_CAP_DEBUG(mdev, cap) \  argument
1217 		 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1219 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \  argument
1221 		 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1223 #define MLX5_CAP_QOS(mdev, cap) \  argument
1225 		 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1227 #define MLX5_CAP_QOS_MAX(mdev, cap) \  argument
1229 		 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1249 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1250 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1252 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1253 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1255 #define	MLX5_CAP_TLS(mdev, cap) \  argument
1256 	MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap)
1258 #define	MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1259 	MLX5_ADDR_OF(device_event_cap, (mdev)->hca_caps_cur[MLX5_CAP_DEV_EVENT], cap)
1261 #define	MLX5_CAP_IPSEC(mdev, cap) \  argument
1262 	MLX5_GET(ipsec_cap, (mdev)->hca_caps_cur[MLX5_CAP_IPSEC], cap)