1020 	/* NUM OF CAP Types */
1049 #define MLX5_CAP_GEN(mdev, cap) \  argument
1050 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1052 #define	MLX5_CAP_GEN_64(mdev, cap)					\  argument
1053 	MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1055 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1056 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1058 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1059 	MLX5_GET(cmd_hca_cap_2, mdev->hca_caps_cur[MLX5_CAP_GENERAL_2], cap)
1061 #define MLX5_CAP_ETH(mdev, cap) \  argument
1063 		 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1065 #define MLX5_CAP_ETH_MAX(mdev, cap) \  argument
1067 		 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1069 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1070 	MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1072 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1073 	MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1075 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1076 	MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1078 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1079 	MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1081 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1082 	MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1084 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1085 	MLX5_GET64(flow_table_nic_cap, (mdev)->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1087 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \  argument
1088 	MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1090 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1091 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1093 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \  argument
1094 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1096 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1097                 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1099 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \  argument
1100         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1102 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1103         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1105 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \  argument
1106         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1108 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1109         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1111 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \  argument
1112         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1114 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1115         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1117 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \  argument
1118         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap)
1120 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1121         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1123 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \  argument
1124         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap)
1126 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1128 		 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1130 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \  argument
1132 		 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1134 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1135 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1137 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \  argument
1138 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1140 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1141 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1143 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \  argument
1144 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1146 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1147 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1149 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \  argument
1150 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1152 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1153         MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap)
1155 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2_MAX(mdev, cap) \  argument
1156         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, ft_field_support_2_esw_fdb.cap)
1158 #define MLX5_CAP_ESW(mdev, cap) \  argument
1160 		 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1162 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1164 		   (mdev)->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1166 #define MLX5_CAP_ESW_MAX(mdev, cap) \  argument
1168 		 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1170 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \  argument
1172 		 mdev->hca_caps_cur[MLX5_CAP_PORT_SELECTION], cap)
1174 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \  argument
1176 		 mdev->hca_caps_max[MLX5_CAP_PORT_SELECTION], cap)
1178 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \  argument
1180 		 mdev->hca_caps_cur[MLX5_CAP_ADV_VIRTUALIZATION], cap)
1182 #define MLX5_CAP_ADV_VIRTUALIZATION_MAX(mdev, cap) \  argument
1184 		 mdev->hca_caps_max[MLX5_CAP_ADV_VIRTUALIZATION], cap)
1186 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \  argument
1187 	MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1189 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION_MAX(mdev, cap) \  argument
1190 	MLX5_CAP_PORT_SELECTION_MAX(mdev, flow_table_properties_port_selection.cap)
1192 #define MLX5_CAP_ODP(mdev, cap)\  argument
1193 	MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1195 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1196 	MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1198 #define MLX5_CAP_SNAPSHOT(mdev, cap) \  argument
1200 		 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1202 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \  argument
1204 		 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1206 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \  argument
1208 		 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1210 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \  argument
1212 		 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1214 #define MLX5_CAP_DEBUG(mdev, cap) \  argument
1216 		 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1218 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \  argument
1220 		 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1222 #define MLX5_CAP_QOS(mdev, cap) \  argument
1224 		 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1226 #define MLX5_CAP_QOS_MAX(mdev, cap) \  argument
1228 		 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1248 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1249 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1251 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1252 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1254 #define	MLX5_CAP_TLS(mdev, cap) \  argument
1255 	MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap)
1257 #define	MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1258 	MLX5_ADDR_OF(device_event_cap, (mdev)->hca_caps_cur[MLX5_CAP_DEV_EVENT], cap)
1260 #define	MLX5_CAP_IPSEC(mdev, cap) \  argument
1261 	MLX5_GET(ipsec_cap, (mdev)->hca_caps_cur[MLX5_CAP_IPSEC], cap)