Lines Matching +full:0 +full:x0040
44 #define MII_NSPHYTER_PHYSTS 0x10 /* PHY status */
45 #define PHYSTS_REL 0x8000 /* receive error latch */
46 #define PHYSTS_CIML 0x4000 /* CIM latch */
47 #define PHYSTS_FCSL 0x2000 /* false carrier sense latch */
48 #define PHYSTS_DEVRDY 0x0800 /* device ready */
49 #define PHYSTS_PGRX 0x0400 /* page received */
50 #define PHYSTS_ANEGEN 0x0200 /* autoneg. enabled */
51 #define PHYSTS_MIIINTR 0x0100 /* MII interrupt */
52 #define PHYSTS_REMFAULT 0x0080 /* remote fault */
53 #define PHYSTS_JABBER 0x0040 /* jabber detect */
54 #define PHYSTS_NWAYCOMP 0x0020 /* NWAY complete */
55 #define PHYSTS_RESETSTAT 0x0010 /* reset status */
56 #define PHYSTS_LOOPBACK 0x0008 /* loopback status */
57 #define PHYSTS_DUPLEX 0x0004 /* full duplex */
58 #define PHYSTS_SPEED10 0x0002 /* speed == 10Mb/s */
59 #define PHYSTS_LINK 0x0001 /* link up */
61 #define PHYSTS_MP_REL 0x2000 /* receive error latch */
62 #define PHYSTS_MP_POLARITY 0x1000 /* polarity inverted */
63 #define PHYSTS_MP_FCSL 0x0800 /* false carrier sense latch */
64 #define PHYSTS_MP_SIGNAL 0x0400 /* signal detect */
65 #define PHYSTS_MP_DESCRLK 0x0200 /* de-scrambler lock */
66 #define PHYSTS_MP_PGRX 0x0100 /* page received */
67 #define PHYSTS_MP_MIIINTR 0x0080 /* MII interrupt */
68 #define PHYSTS_MP_REMFAULT 0x0040 /* remote fault */
69 #define PHYSTS_MP_JABBER 0x0020 /* jabber detect */
70 #define PHYSTS_MP_NWAYCOMP 0x0010 /* NWAY complete */
72 #define MII_NSPHYTER_MIPSCR 0x11 /* MII interrupt PHY specific
75 #define MIPSCR_INTEN 0x0002 /* interrupt enable */
76 #define MIPSCR_TINT 0x0001 /* test interrupt */
78 #define MII_NSPHYTER_MIPGSR 0x12 /* MII interrupt PHY generic
80 #define MIPGSR_MINT 0x8000 /* MII interrupt pending */
82 #define MIPGSR_MSK_LINK 0x4000 /* mask link status event */
83 #define MIPGSR_MSK_JAB 0x2000 /* mask jabber event */
84 #define MIPGSR_MSK_RF 0x1000 /* mask remote fault event */
85 #define MIPGSR_MSK_ANC 0x0800 /* mask auto-neg complete event */
86 #define MIPGSR_MSK_FHF 0x0400 /* mask false carrier half full event */
87 #define MIPGSR_MSK_RHF 0x0200 /* mask RX error half full event */
89 #define MII_NSPHYTER_DCR 0x13 /* Disconnect counter */
91 #define MII_NSPHYTER_FCSCR 0x14 /* False carrier sense counter */
93 #define MII_NSPHYTER_RECR 0x15 /* Receive error counter */
95 #define MII_NSPHYTER_PCSR 0x16 /* PCS configuration and status */
96 #define PCSR_SINGLE_SD 0x8000 /* single-ended SD mode */
97 #define PCSR_FEFI_EN 0x4000 /* far end fault indication mode */
98 #define PCSR_DESCR_TO_RST 0x2000 /* reset descrambler timeout counter */
99 #define PCSR_DESCR_TO_SEL 0x1000 /* descrambler timer mode */
100 #define PCSR_DESCR_TO_DIS 0x0800 /* descrambler timer disable */
101 #define PCSR_LD_SCR_SD 0x0400 /* load scrambler seed */
102 #define PCSR_TX_QUIET 0x0200 /* 100Mb/s transmit true quiet mode */
103 #define PCSR_TX_PATTERN 0x0180 /* 100Mb/s transmit test pattern */
104 #define PCSR_F_LINK_100 0x0040 /* force good link in 100Mb/s */
105 #define PCSR_CIM_DIS 0x0020 /* carrier integrity monitor disable */
106 #define PCSR_CIM_STATUS 0x0010 /* carrier integrity monitor status */
107 #define PCSR_CODE_ERR 0x0008 /* code errors */
108 #define PCSR_PME_ERR 0x0004 /* premature end errors */
109 #define PCSR_LINK_ERR 0x0002 /* link errors */
110 #define PCSR_PKT_ERR 0x0001 /* packet errors */
112 #define PCSR_MP_BYP_4B5B 0x1000 /* bypass encoder */
113 #define PCSR_MP_FREE_CLK 0x0800 /* free funning RX clock */
114 #define PCSR_MP_TQ_EN 0x0400 /* enable True Quiet mode */
115 #define PCSR_MP_SD_FORCE_B 0x0200 /* force signal detection */
116 #define PCSR_MP_SD_OPTION 0x0100 /* enhanced signal detection alg. */
117 #define PCSR_MP_NRZI_BYPASS 0x0004 /* NRZI bypass enabled */
120 #define MII_NSPHYTER_LBR 0x17 /* loopback and bypass */
121 #define LBR_BP_STRETCH 0x4000 /* bypass LED stretching */
122 #define LBR_BP_4B5B 0x2000 /* bypass encoding/decoding */
123 #define LBR_BP_SCR 0x1000 /* bypass scrambler/descrambler */
124 #define LBR_BP_RX 0x0800 /* bypass receive function */
125 #define LBR_BP_TX 0x0400 /* bypass transmit function */
126 #define LBR_100_DP_CTL 0x0380 /* 100Mb/s data patch control */
127 #define LBR_TW_LBEN 0x0020 /* TWISTER loopback enable */
128 #define LBR_10_ENDEC_LB 0x0010 /* 10Mb/s ENDEC loopback */
131 #define MII_NSPHYTER_10BTSCR 0x18 /* 10baseT status and control */
132 #define BTSCR_AUI_TPI 0x2000 /* TREX operating mode */
133 #define BTSCR_RX_SERIAL 0x1000 /* 10baseT RX serial mode */
134 #define BTSCR_TX_SERIAL 0x0800 /* 10baseT TX serial mode */
135 #define BTSCR_POL_DS 0x0400 /* polarity detection and correction
137 #define BTSCR_AUTOSW_EN 0x0200 /* AUI/TPI autoswitch */
138 #define BTSCR_LP_DS 0x0100 /* link pulse disable */
139 #define BTSCR_HB_DS 0x0080 /* heartbeat disabled */
140 #define BTSCR_LS_SEL 0x0040 /* low squelch select */
141 #define BTSCR_AUI_SEL 0x0020 /* AUI select */
142 #define BTSCR_JAB_DS 0x0010 /* jabber disable */
143 #define BTSCR_THIN_SEL 0x0008 /* thin ethernet select */
144 #define BTSCR_TX_FILT_DS 0x0004 /* TPI receive filter disable */
146 #define MII_NSPHYTER_PHYCTRL 0x19 /* PHY control */
147 #define PHYCTRL_TW_EQSEL 0x3000 /* TWISTER e.q. select */
148 #define PHYCTRL_BLW_DS 0x0800 /* TWISTER base line wander disable */
149 #define PHYCTRL_REPEATER 0x0200 /* repeater mode */
150 #define PHYCTRL_LED_TXRX_MODE 0x0180 /* LED TX/RX mode */
151 #define PHYCTRL_LED_DUP_MODE 0x0040 /* LED DUP mode */
152 #define PHYCTRL_FX_EN 0x0020 /* Fiber mode enable */
153 #define PHYCTRL_PHYADDR 0x001f /* PHY address */
155 #define PHYCRTL_MP_PSR_15 0x0800 /* BIST sequence select */
156 #define PHYCTRL_MP_BIST_STAT 0x0400 /* BIST passed */
157 #define PHYCTRL_MP_BIST_START 0x0200 /* start BIST */
158 #define PHYCTRL_MP_BP_STRETCH 0x0100 /* bypass LED stretching */
159 #define PHYCTRL_MP_PAUSE_STS 0x0080 /* pause status */
162 #define MII_MACPHYTER_TBTCTL 0x1a /* 10baseT Control */
163 #define TBTCTL_LOOPBACK_10_DIS 0x0100 /* loopback 10Mb/s disable */
164 #define TBTCTL_LP_DIS 0x0080 /* link pulse disable */
165 #define TBTCTL_FORCE_LINK_10 0x0040 /* force 10Mb/s link good */
166 #define TBTCTL_FORCE_POL_COR 0x0020 /* force polarity correction */
167 #define TBTCTL_INV_POLARITY 0x0010 /* inverted polarity */
168 #define TBTCTL_AUTOPOL_DIS 0x0008 /* auto-polarity disable */
169 #define TBTCTL_HEARTBEAT_DIS 0x0002 /* heartbeat disable */
170 #define TBTCTL_JABBER_DIS 0x0001 /* jabber disable */