Lines Matching +full:half +full:- +full:duplex +full:- +full:capable

1 /*-
2  * SPDX-License-Identifier: BSD-4-Clause
18  * 4. Neither the name of the author nor the names of any co-contributors
50 #define	BRGPHY_BMCR_FDX		0x0100	/* Duplex mode */
63 #define	BRGPHY_BMSR_ANEG	0x0008	/* Autoneg capable */
72 #define	BRGPHY_ANAR_PC		0x0400	/* Pause capable */
79 #define	BRGPHY_ANLPAR_PC	0x0400	/* Pause capable */
89 #define	BRGPHY_ANER_LPAN	0x0001 	/* Link partner autoneg capable */
100 #define	BRGPHY_1000CTL_AFD	0x0200	/* Advertise full duplex */
101 #define	BRGPHY_1000CTL_AHD	0x0100	/* Advertise half duplex */
113 #define	BRGPHY_EXTSTS_X_FD_CAP	0x8000	/* 1000base-X FD capable */
114 #define	BRGPHY_EXTSTS_X_HD_CAP	0x4000	/* 1000base-X HD capable */
115 #define	BRGPHY_EXTSTS_T_FD_CAP	0x2000	/* 1000base-T FD capable */
116 #define	BRGPHY_EXTSTS_T_HD_CAP	0x1000	/* 1000base-T HD capable */
119 #define	BRGPHY_PHY_EXTCTL_MAC_PHY	0x8000	/* 10BIT/GMI-interface */
124 #define	BRGPHY_PHY_EXTCTL_BY_45		0x0400	/* Bypass 4B5B-Decoder */
220 #define	BRGPHY_AUXSTS_PRR	0x0002	/* Pause resolution-RX */
221 #define	BRGPHY_AUXSTS_PRT	0x0001	/* Pause resolution-TX */
223 #define	BRGPHY_RES_1000FD	0x0700	/* 1000baseT full duplex */
224 #define	BRGPHY_RES_1000HD	0x0600	/* 1000baseT half duplex */
225 #define	BRGPHY_RES_100FD	0x0500	/* 100baseT full duplex */
227 #define	BRGPHY_RES_100HD	0x0300	/* 100baseT half duplex */
228 #define	BRGPHY_RES_10FD		0x0200	/* 10baseT full duplex */
229 #define	BRGPHY_RES_10HD		0x0100	/* 10baseT half duplex */
243 #define	BRGPHY_ISR_DUP_CHG	0x0008	/* Duplex mode change */
260 #define	BRGPHY_IMR_DUP_CHG	0x0008	/* Duplex mode change */
295  * Aux control shadow register, bits 0-2 select function (0x00 to
307  * bits 14-10 select function (0x00 to 0x1F).
320 /* When set, Regs 0-0x0F are 1000X, else 1000T */
404 /* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */