Lines Matching +full:100 +full:base +full:- +full:fx

1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
48 #define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */
51 #define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */
53 #define AUX_STS_100BASE_LINK 0x0100 /* 1 = 100base link */
63 #define MII_BMTPHY_RXERROR_CTR 0x12 /* 100base-X Rx error counter */
66 #define MII_BMTPHY_FCS_CTR 0x13 /* 100base-X false carrier counter */
69 #define MII_BMTPHY_DIS_CTR 0x14 /* 100base-X disconnect counter */
81 #define AUX_CSR_ANEG 0x0008 /* auto-negotiation activated */
82 #define AUX_CSR_F100 0x0004 /* force 100base */
83 #define AUX_CSR_SPEED 0x0002 /* 1 = 100, 0 = 10 */
84 #define AUX_CSR_FDX 0x0001 /* full-duplex */
87 #define AUX_SS_ACOMP 0x8000 /* auto-negotiation complete */
88 #define AUX_SS_ACOMP_ACK 0x4000 /* auto-negotiation compl. ack */
89 #define AUX_SS_AACK_DET 0x2000 /* auto-neg. ack detected */
90 #define AUX_SS_ANLPAD 0x1000 /* auto-neg. link part. ability det */
95 #define AUX_SS_HCD_10T_FDX 0x0200 /* 10baseT-FDX */
96 #define AUX_SS_HCD_100TX 0x0300 /* 100baseTX-FDX */
97 #define AUX_SS_HCD_100T4 0x0400 /* 100baseT4 */
98 #define AUX_SS_HCD_100TX_FDX 0x0500 /* 100baseTX-FDX */
102 #define AUX_SS_LPANA 0x0010 /* link partner auto-neg able */
103 #define AUX_SS_SPEED 0x0008 /* 1 = 100, 0 = 10 */
105 #define AUX_SS_ANEN 0x0002 /* auto-neg. enabled */
109 #define INTR_FDX_LED 0x8000 /* full-duplex led enable */
111 #define INTR_FDX_MASK 0x0800 /* full-dupled intr mask */
115 #define INTR_FDX_CHANGE 0x0008 /* full-duplex change */
122 #define AUX2_ANPDQ 0x0100 /* auto-neg parallel detection Q mode */
125 #define AUX2_HS_TOKEN 0x0010 /* high-speed token ring mode */
126 #define AUX2_AUTO_LP 0x0008 /* auto low-power mode */
135 #define AUXERR_F100 0x0004 /* force 100base */
136 #define AUXERR_SPEED 0x0002 /* 1 = 100, 0 = 10 */
137 #define AUXERR_FDX 0x0001 /* full-duplex */
145 #define AUXMPHY_HCD_TX_FDX 0x8000 /* res. is 100baseTX-FDX */
146 #define AUXMPHY_HCD_T4 0x4000 /* res. is 100baseT4 */
147 #define AUXMPHY_HCD_TX 0x2000 /* res. is 100baseTX */
148 #define AUXMPHY_HCD_10T_FDX 0x1000 /* res. is 10baseT-FDX */
150 #define AUXMPHY_RES_ANEG 0x0100 /* restart auto-negotiation */
151 #define AUXMPHY_ANEG_COMP 0x0080 /* auto-negotiation complete */
155 #define AUXMPHY_SUPER_ISO 0x0008 /* super-isolate mode */