Lines Matching +full:0 +full:x0040
41 #define MII_BMTPHY_AUX_CTL 0x10 /* auxiliary control */
42 #define AUX_CTL_TXDIS 0x2000 /* transmitter disable */
43 #define AUX_CTL_4B5B_BYPASS 0x0400 /* bypass 4b5b encoder */
44 #define AUX_CTL_SCR_BYPASS 0x0200 /* bypass scrambler */
45 #define AUX_CTL_NRZI_BYPASS 0x0100 /* bypass NRZI encoder */
46 #define AUX_CTL_RXALIGN_BYPASS 0x0080 /* bypass rx symbol alignment */
47 #define AUX_CTL_BASEWANDER_DIS 0x0040 /* disable baseline wander correction */
48 #define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */
50 #define MII_BMTPHY_AUX_STS 0x11 /* auxiliary status */
51 #define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */
52 #define AUX_STS_LOCKED 0x0200 /* descrambler locked */
53 #define AUX_STS_100BASE_LINK 0x0100 /* 1 = 100base link */
54 #define AUX_STS_REMFAULT 0x0080 /* remote fault */
55 #define AUX_STS_DISCON_STATE 0x0040 /* disconnect state */
56 #define AUX_STS_FCARDET 0x0020 /* false carrier detected */
57 #define AUX_STS_BAD_ESD 0x0010 /* bad ESD detected */
58 #define AUX_STS_RXERROR 0x0008 /* Rx error detected */
59 #define AUX_STS_TXERROR 0x0004 /* Tx error detected */
60 #define AUX_STS_LOCKERROR 0x0002 /* lock error detected */
61 #define AUX_STS_MLT3ERROR 0x0001 /* MLT3 code error detected */
63 #define MII_BMTPHY_RXERROR_CTR 0x12 /* 100base-X Rx error counter */
64 #define RXERROR_CTR_MASK 0x00ff
66 #define MII_BMTPHY_FCS_CTR 0x13 /* 100base-X false carrier counter */
67 #define FCS_CTR_MASK 0x00ff
69 #define MII_BMTPHY_DIS_CTR 0x14 /* 100base-X disconnect counter */
70 #define DIS_CTR_MASK 0x00ff
72 #define MII_BMTPHY_PTEST 0x17 /* PTEST */
74 #define MII_BMTPHY_AUX_CSR 0x18 /* auxiliary control/status */
75 #define AUX_CSR_JABBER_DIS 0x8000 /* jabber disable */
76 #define AUX_CSR_FLINK 0x4000 /* force 10baseT link pass */
77 #define AUX_CSR_HSQ 0x0080 /* SQ high */
78 #define AUX_CSR_LSQ 0x0040 /* SQ low */
79 #define AUX_CSR_ER1 0x0020 /* edge rate 1 */
80 #define AUX_CSR_ER0 0x0010 /* edge rate 0 */
81 #define AUX_CSR_ANEG 0x0008 /* auto-negotiation activated */
82 #define AUX_CSR_F100 0x0004 /* force 100base */
83 #define AUX_CSR_SPEED 0x0002 /* 1 = 100, 0 = 10 */
84 #define AUX_CSR_FDX 0x0001 /* full-duplex */
86 #define MII_BMTPHY_AUX_SS 0x19 /* auxiliary status summary */
87 #define AUX_SS_ACOMP 0x8000 /* auto-negotiation complete */
88 #define AUX_SS_ACOMP_ACK 0x4000 /* auto-negotiation compl. ack */
89 #define AUX_SS_AACK_DET 0x2000 /* auto-neg. ack detected */
90 #define AUX_SS_ANLPAD 0x1000 /* auto-neg. link part. ability det */
91 #define AUX_SS_ANEG_PAUSE 0x0800 /* pause operation bit */
92 #define AUX_SS_HCD 0x0700 /* highest common denominator */
93 #define AUX_SS_HCD_NONE 0x0000 /* none */
94 #define AUX_SS_HCD_10T 0x0100 /* 10baseT */
95 #define AUX_SS_HCD_10T_FDX 0x0200 /* 10baseT-FDX */
96 #define AUX_SS_HCD_100TX 0x0300 /* 100baseTX-FDX */
97 #define AUX_SS_HCD_100T4 0x0400 /* 100baseT4 */
98 #define AUX_SS_HCD_100TX_FDX 0x0500 /* 100baseTX-FDX */
99 #define AUX_SS_PDF 0x0080 /* parallel detection fault */
100 #define AUX_SS_LPRF 0x0040 /* link partner remote fault */
101 #define AUX_SS_LPPR 0x0020 /* link partner page received */
102 #define AUX_SS_LPANA 0x0010 /* link partner auto-neg able */
103 #define AUX_SS_SPEED 0x0008 /* 1 = 100, 0 = 10 */
104 #define AUX_SS_LINK 0x0004 /* link pass */
105 #define AUX_SS_ANEN 0x0002 /* auto-neg. enabled */
106 #define AUX_SS_JABBER 0x0001 /* jabber detected */
108 #define MII_BMTPHY_INTR 0x1a /* interrupt register */
109 #define INTR_FDX_LED 0x8000 /* full-duplex led enable */
110 #define INTR_INTR_EN 0x4000 /* interrupt enable */
111 #define INTR_FDX_MASK 0x0800 /* full-dupled intr mask */
112 #define INTR_SPD_MASK 0x0400 /* speed intr mask */
113 #define INTR_LINK_MASK 0x0200 /* link intr mask */
114 #define INTR_INTR_MASK 0x0100 /* master interrupt mask */
115 #define INTR_FDX_CHANGE 0x0008 /* full-duplex change */
116 #define INTR_SPD_CHANGE 0x0004 /* speed change */
117 #define INTR_LINK_CHANGE 0x0002 /* link change */
118 #define INTR_INTR_STATUS 0x0001 /* interrupt status */
120 #define MII_BMTPHY_AUX2 0x1b /* auliliary mode 2 */
121 #define AUX2_BLOCK_RXDV 0x0200 /* block RXDV mode enabled */
122 #define AUX2_ANPDQ 0x0100 /* auto-neg parallel detection Q mode */
123 #define AUX2_TRAFFIC_LED 0x0040 /* traffic meter led enable */
124 #define AUX2_FXMTRCV_LED 0x0020 /* force Tx and Rx LEDs */
125 #define AUX2_HS_TOKEN 0x0010 /* high-speed token ring mode */
126 #define AUX2_AUTO_LP 0x0008 /* auto low-power mode */
127 #define AUX2_TWOLINK_LED 0x0004 /* two link LEDs */
128 #define AUX2_SQE_DIS 0x0002 /* disable SQE pulse */
130 #define MII_BMTPHY_AUXERR 0x1c /* auxiliary error */
131 #define AUXERR_MANCHESTER 0x0400 /* Manchester code error */
132 #define AUXERR_EOF 0x0200 /* EOF detection error */
133 #define AUXERR_POLARITY 0x0100 /* polarity inversion */
134 #define AUXERR_ANEG 0x0008 /* autonegotiation enabled */
135 #define AUXERR_F100 0x0004 /* force 100base */
136 #define AUXERR_SPEED 0x0002 /* 1 = 100, 0 = 10 */
137 #define AUXERR_FDX 0x0001 /* full-duplex */
139 #define MII_BMTPHY_AUXMODE 0x1d /* auxiliary mode */
140 #define AUXMODE_ACT_LED_DIS 0x0010 /* activity LED disable */
141 #define AUXMODE_LINK_LED_DIS 0x0008 /* link LED disable */
142 #define AUXMODE_BLOCK_TXEN 0x0002 /* enable block TXEN */
144 #define MII_BMTPHY_AUXMPHY 0x1e /* auxiliary multiple phy register */
145 #define AUXMPHY_HCD_TX_FDX 0x8000 /* res. is 100baseTX-FDX */
146 #define AUXMPHY_HCD_T4 0x4000 /* res. is 100baseT4 */
147 #define AUXMPHY_HCD_TX 0x2000 /* res. is 100baseTX */
148 #define AUXMPHY_HCD_10T_FDX 0x1000 /* res. is 10baseT-FDX */
149 #define AUXMPHY_HCD_10T 0x0800 /* res. is 10baseT */
150 #define AUXMPHY_RES_ANEG 0x0100 /* restart auto-negotiation */
151 #define AUXMPHY_ANEG_COMP 0x0080 /* auto-negotiation complete */
152 #define AUXMPHY_ACK_COMP 0x0040 /* acknowledge complete */
153 #define AUXMPHY_ACK_DET 0x0020 /* acknowledge detected */
154 #define AUXMPHY_ABILITY_DET 0x0010 /* waiting for LP ability */
155 #define AUXMPHY_SUPER_ISO 0x0008 /* super-isolate mode */
156 #define AUXMPHY_10T_SERIAL 0x0002 /* 10baseT serial mode */
158 #define MII_BMTPHY_TEST 0x1d /* Broadcom test register */